JP2755516B2 - Automatic identification decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic identification decoding device for automatically identifying and decoding digital data of a plurality of different systems, and more particularly to a decoding processing speed for digital data. The present invention relates to an automatic identification decoding device.

[0002]

2. Description of the Related Art Conventionally, in an information processing system in which a plurality of types of digital data of different systems coexist, the types of these digital data are automatically determined so that any type of digital data can be decoded. For example, in a system in which the configured automatic identification decoding device is used and barcode information is used as the digital data, the barcode may be "JAN" or "C39" depending on the field in which it is used. ”,“ NW
7 ”,“ ITF ”, etc., the decoding system that reads and decodes the barcode is a barcode that can decode any of the barcodes with different systems. An automatic identification decoding device is used.

A bar code automatic identification decoding apparatus of this type is disclosed, for example, in Japanese Patent Application Laid-Open No. 62-10781.
Are disclosed in US Pat.

FIG. 8 is a block diagram showing a barcode automatic identification decoding apparatus according to the above disclosure.

In FIG. 8, reference numeral 71 denotes a count value memory;
72 is a barcode decoder of JAN system, 73 is ITF
A bar code decoder of a system, 74 is a bar code decoder of an NW7 system, 75 to 77 are AND gates, 78 is an OR gate, 79 is a read start signal input terminal, and 80 is a clock signal input terminal.

The operation of the barcode automatic identification decoding device is as follows.

When a bar code is read by an optical head (not shown), a binary signal obtained in accordance with the reading is created, and then the bar code obtained from the binary signal is read. The count value indicating the width of each bar of the code is sequentially written to the count value memory 71. When the reading of the bar code is completed and the count value N representing the width of all the bars is written into the count value memory 71, the read start signal SR supplied to the read start signal input terminal 79 causes the count value memory to be read. The count value N written in 71 is read out in the order of writing, and is supplied to each bar code decoder 72, 73, 74.

At this time, each bar code decoder 72, 7
3 and 74, the bar code decoder 72 starts the processing of the count value N according to the instruction of the supplied read start signal SR and decodes the value N. Therefore, the barcode decoder 72 of the JAN system successfully decodes the count value N, and generates decode data DD at its output and generates a decode end signal E1 at the end of decoding.

[0009] On the other hand, the read bar code is JA
If it is not the N system, the bar code decoder 72 of the JAN system cannot decode the count value N, so that a decoding end signal E1 and a decoding failure signal F1 are generated at its output. Next, these signals E1 and F1 are supplied to the error signal ER via the AND gate 75.
1 and this error signal ER1 is
It is supplied to the count value memory 71 via the OR gate 78 and to the bar code decoder 73 of the ITF system.

When the start signal (error signal ER1) is supplied, the count value memory 71 stores the count value N again.
To read the barcode decoder 7 of the ITF system.
3 starts processing of the count value N and decodes the value N. At this time, if the read barcode is of the ITF system, the barcode decoder 73 of the ITF system successfully decodes the count value N. Sometimes, a decode end signal E2 is generated.

On the other hand, if the read bar code is not of the ITF system, the bar code decoder 73 of the ITF system cannot decode the count value N. E2
And a decoding failure signal F2 are generated.
2. F2 receives the error signal ER2 via the AND gate 76.
become. This error signal ER2 is also supplied again as a start signal to the count value memory 71 via the OR gate 78, and is also supplied to the next NW7 system bar code decoder 74.

In the same manner, decoding of the count value N is attempted in the next barcode decoder 74 of the NW7 system. If decoding is successful, decode data DD is generated at the output, and decoding failure occurs. In this case, an error signal ER3 indicating that decoding is impossible is transmitted.

As described above, the bar code automatic identification and decoding apparatus can automatically identify and decode a bar code system,
Since decoding is performed repeatedly in the order of 2, 73, and 74, there is an unsolved problem that it takes a considerable amount of time from the start of reading a barcode to the decoding of the barcode. .

Therefore, in order to solve the above-mentioned problem, the applicant of the present invention has proposed the following barcode automatic identification decoding device as Japanese Patent Application No. 3-72045.

FIG. 9 is a block diagram showing a barcode automatic identification decoding device according to the above proposal.

In FIG. 9, reference numerals 81, 82 and 83 denote decode memories, reference numerals 84, 85, 86 and 87 denote AND gates, and other components which are the same as those shown in FIG.

This bar code automatic identification decoding apparatus
The following operation is performed.

When the reading of the bar code is completed and the count value N representing the width of all the bars is written into the count value memory 71, the count value memory is read by the read start signal SR supplied to the read start signal input terminal 79. The count value N written in 71 is read out in the order of writing,
It is supplied to each bar code decoder 72, 73, 74 simultaneously.

At this time, each bar code decoder 72, 7
Reference numerals 3 and 74 denote the decode data DD decoded at that time by starting the processing of the count value N according to the instruction of the supplied read start signal SR and decoding the count value N.
1, DD2 and DD3 are supplied to decode memories 84, 85 and 86, respectively, which are arranged correspondingly.

Now, the read bar code is JA.
In the case of the N system, the bar code decoder 72 of the JAN system succeeds in decoding the count value N.
The decode data DD1 generated at the output is sent to the decode memory 84, and only the decode end signal E1 is generated at the end of the decode. However, the remaining barcode decoders 73 and 74 cannot decode the count value N. At the end of the decoding, the decoding end signal E
2, E3 and decode failure signals F2 and F3 are generated.

For this reason, error signals ER2 and ER3 are generated at the outputs of the AND gates 76 and 77, respectively. These error signals ER2 and ER3 are decoded end signals E1.
Is supplied to the AND gate 84 to generate a read start signal R1 at the output thereof, so that the decode data DD1 sent to the decode memory 81 is immediately read out.
It is extracted as decoded data DD. In this case, since the AND gates 85 and 86 do not receive the input from the AND gate 75 among the inputs, the read start signals R2 and R3 are not generated and the decode data DD2 and
Reading of DD3 is not performed.

Next, the read bar code is used for the IT
In the case of the F system, the count value N as described above is stored only in the bar code decoder 73 of the ITF system.
, The decoding data DD2 is generated, the decoding data DD2 is written into the decoding memory 82, and the decoding data DD is read. The read barcode is of the NW7 system. For example, an NW7 system barcode decoder 7
4 and the decoding memory 83 alone.

As described above, the barcode automatic identification and decoding device according to the above proposal can shorten the time from the start of reading a barcode to the decoding of the barcode.

[0024]

However, each of the automatic barcode identification decoding device (the former) according to the above disclosure and the barcode automatic identification decoding device (the latter) according to the above-mentioned proposal has the disadvantage that each of the read barcodes has its own configuration. The count value N representing the width of the bar is temporarily stored in the count value memory 7.
1 and then by reading the written count value N, each bar code decoder 72, 73,
74, the decoding is not performed while the count value N is being written into the count value memory 71 at least. It is.

As described above, not only the former but also the latter are insufficient to solve the problem of shortening the time from when barcode reading is started until it is decoded. It is.

Since the count value memory 71 used for the former and the latter requires a relatively large-capacity RAM (random access memory), the size of the bar code automatic identification decoding device can be reduced accordingly. There is also a problem that hindrance is prevented and cost reduction is hindered.

The present invention solves these problems, minimizes the time from the start of reading digital data until it is decoded, and has a large capacity RAM as a RAM to be used. It is an object of the present invention to provide an automatic identification decoding device which does not require a device.

[0028]

Means for Solving the Problems] To the accomplishment of the above object, the present invention sequentially selects a plurality of decoders and the plurality of decoders having different digital data system for decoding digital data read, selected I
The decoded data of the digital data from the decoded data
A decoder including a decoder selector to output said and a counter for the selection of the plurality of decoders selector sequentially progressive, digital to each of the plurality of decoders of the decoder unit is read the data
Is supplied, and in this case, the digital data is decoded in any of the plurality of decoders.
When the code data is obtained, that is, when the decoding is successful, the decoded data is output, and the selected decoder decodes the digital data.
If no data is available, i.e., decoding fails, an error signal is provided to the counter, thereby causing the selection of the plurality of decoders to proceed by only one,
The above operation is repeatedly performed.

Further, in order to achieve the above object, the present invention is, between the said decoder counter, the decode order setting means for changing the decoder selection order to the plurality of decoders in the decoder unit Means for selecting the actual output value from the counter or the output value of the counter at the time of the previous successful decoding; and a decoding selection order switching means for selecting the actual decoded data of the decoder unit at the output side of the decoder unit. and it has placed the decoded data comparing means for comparing the decoded data of the previous successful decoding, the decoded data comparing means, before
Successful decoding when two decoded data match
When a signal is output and a decoding success signal is output, the next time the decoder used at that time is selected again to decode digital data.

[0030]

The decoder section is provided with a plurality of decoders capable of separately decoding digital data of different systems, and these decoders are sequentially selected by a decoder selector, and the selected decoder reads data. Digital data is supplied directly. If the digital data is successfully decoded by the selected decoder, the decoded data is output.
On the other hand, if the decoding of the digital data fails in the selected decoder, an error signal is output,
The error signal advances the decoder selection order of the decoder selector by one to select the next decoder, and the processing operation is repeated in the selected decoder.

Therefore, the read digital data is supplied to the plurality of decoders provided in the decoder section without passing through the count value memory used in the conventional device of this type, and the digital data is supplied to the plurality of decoders. Since the above-described processing operation is performed, it is possible to shorten the time from when the reading of digital data is started to when it is decoded, and furthermore, a small memory capacity is sufficient. It is.

In addition, if the immediately preceding decoding or the previous decoding is successful, the next time the digital data is decoded by using the decoder used at that time again, the data can be obtained in addition to the above-described operation. Reliability is improved.

[0033]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block circuit diagram showing a first embodiment of the automatic identification decoding apparatus according to the present invention.

In each of the embodiments described below,
The case where digital data is bar code data and the bar code data is decoded will be described as an example.

In FIG. 1, 1 is a decoder unit, 2 is a counter, 3 is an OR gate, 4 is a bar code data input line, 5 is a decode data output line, 6 is a decode success signal output line, and 7 is an all error signal output line. , 8
Is an error signal output line, 9 is a reset signal input line, and 10 is a count signal output line.

In the decoder section 1, the input is connected to the bar code data input line 4 and the output is connected to the decode data output line 5. Counter 2
Are connected to the decoder unit 1 via the error signal output line 8 and the count signal output line, and are also connected to the output of the OR gate 3. Also, OR gate 3
Are connected to a decoding success signal output line 6, an all error signal output line 7, and a reset signal input line 9, respectively.

FIG. 2 is a block circuit diagram showing an example of the internal configuration of the decoder section 1. As shown in FIG.

In FIG. 2, 11 is a barcode decoder of the JAN system, 12 is a barcode decoder of the C39 system, 13 is a barcode decoder of the NW7 system, and 14 is an I / O barcode decoder.
A bar code decoder of the TF system, 15 is a decode selector, 16 is a maximum decode number constant memory, 17 is a decode number comparator, 18 is an inverter, and other components that are the same as those shown in FIG. Is attached.

The bar code decoders 11 to 14
, Their inputs are connected to a barcode data input line 4 and their outputs are connected to a decode data output line 5. In the decode selector 15, each output is connected to the operation selector of the bar code decoders 11 to 14, and the input is a count signal output line 10.
Connected to. The decoding success signal output line 6 is connected directly to the bar code decoders 11 to 14, and the error signal output 8 is connected via an inverter line 18. The decode number comparator 17 has an input connected to the maximum decode number constant memory 16 and the count signal output line 10, and an output connected to the all error signal output line 7, respectively.

The first embodiment according to the above configuration operates as described below.

The bar code data input line 4 is a binary code obtained by binarizing the bar code read by a bar code reading unit (not shown) at the white and black levels.
By generating a digitized signal and supplying the binarized signal to a timer circuit (not shown), barcode data bc converted to a value (count value) representing the width of each bar of the barcode is added, The barcode data bc is supplied directly from the barcode data input line 4 to each of the barcode decoders 11 to 14 of the decoder unit 1.

At this time, in each of the bar code decoders 11 to 14, only one of the bar code decoders 11 to 14 is selected to perform the decoding operation by the operation selection signals dc1 to dc4. The output order of the operation selection signals dc1 to dc4 corresponds to the magnitude of the count signal value input to the decode selector 15 via the count signal output line 10, and the initial state of the automatic identification decoding device is dc1. (Count signal value is minimum, eg, 1), next is dc2 (count signal value is increased by one, eg, 2), next is dc3 (count signal value is further increased by one, eg, 3), The last is dc
4 (the maximum count signal value is, for example, 4).

When the bar code data bc is supplied from the bar code data input line 4 in the initial state of the automatic identification decoding device, the bar code data bc
First, decoding is performed in the JAN system barcode decoder 11 which is selectively in a decoding operable state. In this case, the barcode data is of the JAN system and the barcode decoder 11 performs the decoding. If the decoding of the bar code data bc is successful, the decoded data dd is output to the decoded data output line 5.
Is output, and at the same time, a decoding success signal (ok signal) is output to the decoding success signal output line 6. And
This ok signal is supplied to the counter 2 via the OR gate 3, and the counter 2 is reset to clear its count value, so that the automatic identification decoding device returns to the initial state.

On the other hand, if the bar code data is not in the JAN system, the bar code data bc cannot be decoded by the bar code decoder 11, so that no ok signal is output to the decode success signal output line 6, The state of the decoding success signal output line 6 generates an error signal on the error signal output line 8 via the inverter 18. Next, this error signal is supplied to the counter 3 via the error signal output line 8 and the count value thereof is advanced by one, so that the count signal value of the count signal output line 10 is also increased by one to two. .
Subsequently, when the increased count signal value is input to the decode selector 15, the decode selector 15 replaces the operation selection signal dc1 output up to that time with the operation selection signal d.
c2, and by supplying this operation selection signal dc2,
The barcode decoder 12 of the C39 system can perform the decoding operation.

At this time, the bar code data input line 4
Supplies the bar code data bc, the bar code data bc is decoded by the C39 system bar code decoder 12 which is in a state in which the decoding operation can be selectively performed this time. Is a C39 system, and if the barcode data bc is successfully decoded by the barcode decoder 12, the decode data dd is output to the decode data output line 5, and at the same time, the decode success signal output line 6 Output an ok signal. And this o
The k signal is supplied to the counter 2 via the OR gate 3, and resets the counter 2 to clear its count value.

On the other hand, if the bar code data is C
Otherwise, the bar code decoder 12 cannot decode the bar code data bc. Therefore, no ok signal is output to the decoding success signal output line 6 and the state of the decoding success signal output line 6 is determined by the inverter. An error signal is generated on an error signal output line 8 via 18. This error signal is then supplied to the counter 3 via the error signal output line 8 and the count value is advanced by one again, so that the count signal value on the count signal output line 10 is further increased by one. become. Next, when the increased count signal value is input to the decode selector 15, the decode selector 15
Outputs an operation selection signal dc3 instead of the operation selection signal dc2 that has been output up to that time, and this operation selection signal d
By supplying c3, NW7 barcode decoder 1
3 can be decoded.

Thereafter, similarly, decoding of the bar code data bc is attempted in the bar code decoder 13 of the NW7 system, and if the bar code data bc is successfully decoded, the decode data dd
Is transmitted and if the decoding of the bar code data bc fails, the bar code decoder 1 of the next ITF system is used.
A similar attempt is made at 4.

When the decoding attempt in all the bar code decoders 11 to 14 fails, the count signal value of the count signal output line 10 (for example,
4) matches the output signal value (for example, 4) of the maximum decoding number constant memory 16, whereby the decoding number comparator 1
7, a coincidence signal is output. At this time, the coincidence signal is supplied as an all error signal from the all error signal output line 7 to the counter 3 through the OR gate 3, and the counter 3 is reset to clear the counter value. Returning to the initial state, the above operation is repeated again.

As described above, according to the present embodiment, the bar code data read without passing through the count value memory is supplied to each of the bar code decoders 11 to 14, and the bar code data is supplied to each of the bar code decoders 11 to 14. To 14
, The time required to write barcode data in the count value memory is saved, and the time from when barcode data reading is started until it is decoded can be shortened. In addition, since the count value memory is not used, a small memory (RAM) is required.

FIG. 3 is a block circuit diagram showing a second embodiment of the automatic identification decoding apparatus according to the present invention.

In FIG. 3, 19 is a current decoding order memory, 20 is a current decoding order switch, 21 is a first decoding data memory, 22 is a decoding data comparator, and 23 is a decoding data comparator.
Is a second decoding success signal output line;
The same components as those shown in FIGS. 1 and 2 are denoted by the same reference numerals.

The current decoding order memory 19 stores
The input is connected to the counter 2 and the output is currently connected to the decoding order switch 20. The current decoding order switch 20 is connected to the output of the counter 2, the OR gate 3, and the decoding success signal output line 6, and its output is connected to the count signal output line 10. First, the decode data memory 21 has an input connected to the decoder unit 1 and an output connected to one input of the decode data comparator 22. The other input of the decode data comparator 22 is connected to the decoder unit 1, and the output is connected to a second decode success signal output line 23. The second decoding success signal output line 23 is connected to the input of the OR gate 3. Here, the current decoding order memory 19 and the current decoding order switching unit 20 constitute a decoding selection order switching unit, and the first decoding data memory 21 and the decoding data comparator 22 constitute a decoding data comparing unit. Also in this example, the internal configuration of the decoder unit 1 has the same configuration as that of the first example.

In this case, the current decoding order memory 19
Performs the storage of the current count value cnt of the counter 2 and the first count value cnt1 corresponding to the stored content.
Occurs. When receiving the reset signal from the OR gate 3, the current decoding order switch 20 receives the count value c.
nt is output as a second count value cnt2, and upon receiving a decoding success signal from the decoder unit 1, the first count value cnt1 is output. When the decode data memory 21 first receives the decode success signal,
The decoded data dd output from the decoder unit 1 is stored, the stored content is output as the second decoded data dd1, and the stored decoded data dd is cleared by supplying a reset signal. The decode data comparator 22 outputs a second decode success signal ok1 when the decode data dd matches the second decode data dd1.

In the second embodiment according to the above configuration, the following operation is performed.

First, a binary signal obtained by binarizing the bar code read by the bar code reading unit at the white and black levels is supplied to a bar code data input line 4 to a timer circuit. Is added to the bar code data bc converted into a count value representing the width of each bar. This bar code data bc is supplied directly from the bar code data input line 4 to each of the bar code decoders 11 to 14 of the decoder unit 1. Is the same as in the first embodiment.

Further, the current decoding order switch 20 changes the count value cnt from the counter 2 to the second count value cn.
The operation of the circuit including the decoder unit 1, the counter 2, and the OR gate 3 when switching to output as t2 is the same as in the case of the first embodiment.

Here, the operation unique to the present embodiment will be described.
For example, if the barcode data bc is successfully decoded by the C39 system barcode decoder 12, the decode data dd is output to the decode data output line 5.
Is output and the decoding success signal output line 6
Output an ok signal. Among these outputs, the decode data dd is first supplied to the decode data memory 21 and stored therein, and the ok signal is supplied to the current decode order switch 20 via the decode success signal output line 6. You. Further, upon receiving the ok signal, the current decoding order switching unit 20 replaces the count value cnt of the counter 2 previously output as the second count value cnt2 with the current decoding order memory 19.
Is switched so as to output the stored content cnt1. It should be noted that the current decoding order memory 19 at the time of this switching is used.
Is stored in C39 where the decoding was successful.
Since the operation selection signal dc2 for selecting the bar code decoder 12 of the C39 system is generated, when the bar code data bc is subsequently decoded in the decoder unit 1, the bar code decoder 12 of the C39 system is selected again. Is done.

Subsequently, the bar code data bc is supplied to the decoder section 1. If the bar code data bc is of the C39 system, the C code selected at this time is output.
The bar code data bc is decoded by the bar code decoder 12 of 39 systems, and the decoded data d
d is output to the decode data output line 5. At this time, the decoder data comparator 22 compares the decode data dd with the decode data dd initially stored in the decode data memory 21. If the comparison results match, the current bar code data bc Assuming that decoding is successful, a second decoding success (ok) signal ok1 is generated at the output of the decoder data comparator 22. Next, the ok signal ok1 is supplied to the counter 2 via the OR gate 3, and the counter 2 is reset to clear its contents, thereby returning the automatic identification decoding device to the initial state.

On the other hand, in this embodiment, after one bar code data bc is successfully decoded by one decoder in the decoder unit 1, for example, the bar code decoder 12 of the C39 system, decoding of the subsequent bar code data bc is unsuccessful. , The current decode order switch 2
0 is switched to output the count value cnt of the counter 2 as the second count value cnt2, and the same operation as the operation of the first embodiment is performed.

In the present embodiment, an example in which the bar code data bc is successfully decoded in the C39 system bar code decoder 12 in the decoder unit 1 has been described. Barcode decoder, for example, barcode decoder 11 of JAN system, barcode decoder 1 of NW7 system
3. The same applies to the case where the barcode data bc is successfully decoded in the barcode decoder 14 of the ITF system.

In general, when barcode data of a certain system is supplied, barcode data supplied subsequently is very often barcode data of the system. The present embodiment is configured by focusing on such points. That is, in this embodiment, when the barcode data bc is successfully decoded,
When the subsequent barcode data bc is decoded, the barcode decoder having the same system as the previous one is used again, and the success of the decoder is determined by comparison with the previous decode data. Time to write barcode data to the count value memory is saved,
It is possible to further reduce the time from when the reading of the barcode data is started to when it is decoded. Further, the reliability of the decoded data can be improved in addition to the effect of the first embodiment that the required capacity of the memory (RAM) is small because the count value memory is not used. There is also the effect of becoming.

Next, FIG. 4 is a block circuit diagram showing a third embodiment of the automatic identification decoding apparatus according to the present invention.

In FIG. 4, reference numeral 24 denotes a decoding order setting section, and other components which are the same as those shown in FIGS. 1 and 2 are denoted by the same reference numerals.

The decoding order setting section 24 has an input connected to the counter 2 and an output connected to the decoder 1.
Are connected to the decoding success signal output line 6 and the reset signal input line 9, respectively. Also in this example, the internal configuration of the decoder unit 1 has the same configuration as that of the first example.

In this case, the decoding order setting section 24
Upon receiving the count value cnt and the ok signal of the counter 2, the contents of the decoding order memory described below are changed.

FIG. 5 is a block circuit diagram showing an example of the internal configuration of the decoding order setting section 24.

In FIG. 5, reference numeral 25 denotes a decoding order switching signal generator, 26 denotes a first decoding order memory, and 27 denotes a first decoding order memory.
A decoding order switch 28, a second decoding order memory,
29 is a second decoding order switch, 30 is a third decoding order memory, 31 is a third decoding order switch, and 32 is a fourth decoding order switch.
A decoding order memory, 33 is a fourth decoding order switch,
34 is a decoding order switching unit.

The decoding order switching signal generator 25
Has one input and eight outputs, and the input is counter 2
, Each output is a corresponding decoding order memory 26, 2
8, 30, 32 and decode order switchers 27, 29, 3
1 and 33, and also to the decoding success signal output line 6. Each decoding order memory 2
6, 28, 30, 32 and decode order switch 27, 2
9, 31, and 33 are alternately arranged and connected in a loop through preset signal lines. The decode order switch 34 has four inputs and one output, and each output is connected to the corresponding decode order memory 2.
6, 28, 30, and 32, respectively, and the output is connected to the decoder unit 1. Also in this example, the internal configuration of the decoder unit 1 has the same configuration as that of the first example.

In this case, the first decoding order memory 26
The first preset signal pr1 is stored by the application of the first write signal w1, and the stored content is output as the first order signal od1. The reset value is reset to a predetermined initial value by applying a reset signal from the reset signal input line 9. The first decoding order switch 27 applies the first write signal w1 to the first order signal od.
1 is supplied as a second preset signal pr2 to the subsequent second decoding order memory 28, and the first write signal w1
The first order signal od1 is supplied to the first decoding order memory 26 as a first preset signal pr1 by simultaneous application of the first setting signal s1 and the first setting signal s1. The second decoding order memory 28 receives the second write signal w2,
Is stored, and the stored content is output as a second order signal od2. The reset value is reset to a predetermined initial value by the application of the reset signal. Second
The decode order switch 29 applies a second write signal w2 to the third decode order memory 30 which continues the second order signal od2 as a third preset signal pr3.
And the second write signal w2 and the second setting signal s
2 by using the second order signal od2 as a first preset signal pr1.
6 Hereinafter, the third and fourth decoding order memories 3
0, 32 and third and fourth decoding order switches 31, 33
This also achieves the same functions as those of the first and second decoding order memories 26 and 28 and the first and second decoding order switches 27 and 29 described above. Further, the decoding order switch 34
Selects and outputs one of the input first to fourth order signals od1 to od4 according to the count value cnt of the counter 2.

FIG. 6 is a block diagram showing an example of the internal configuration of the decoding order switching signal generator 25.

In FIG. 6, 35 is a counter memory, 3
6 is a first decoding order constant memory, 37 is a first decoding order comparator, 38 is a second decoding order constant memory, 39
Is a second decoding order comparator, 40 is a third decoding order constant memory, 41 is a third decoding order comparator, and 42 is a fourth decoding order constant memory.
A decoding order constant memory, 43 is a fourth decoding order comparator, 44, 45, 46 are inverters, 47, 48, 4
9 and 50 are AND gates.

The first to fourth decoding order comparators 37, 39, 41, and 43 receive the counter memory 35 as an input.
The first to fourth decoding order constant memory 36 corresponding to
The outputs are connected to the inputs of AND gates 47, 48, 49, 50, either directly or via inverters 44, 45, 46, respectively.

In this case, the counter memory 35 stores the count value of the counter 2 and stores the stored value as the count value c.
Output as ntc. First decoding order constant memory 3
6 is a predetermined value, for example, 1 is a first constant value cd1
Output as The first decoding order comparator 37 compares the count value cnt with the first constant value cd1 when the ok signal of the decoding success signal output line 6 is supplied, and performs first writing when cntc ≧ cd1. Signal w
Outputs 1. The second decoding order constant memory 38 outputs a predetermined value, for example, 2 as a second constant value cd2. The second decoding order comparator 39 compares the count value cntc with the second constant value cd2 when the ok signal is supplied, and outputs a second write signal signal w2 when cntc ≧ cd2. . Hereinafter, the functions of the third and fourth decoding order constant memories 39 and 41 and the third and fourth decoding order comparators 41 and 43 are also the same as those of the first and second decoding order constant memories 36 and 38 and the first and second decoding order constant memories 36 and 38. The function is the same as that of the two decode order comparators 37 and 39.

The third embodiment according to the above-described configuration operates as described below.

Here, the bar code data input line 4
Supplies a timer circuit with a binarized signal obtained by binarizing the bar code read by the bar code reading unit at its white and black levels, and converts the bar code into a count value representing the width of each bar of the bar code. In the case of the above-described first embodiment, the bar code data bc is added to the bar code data bc, and the bar code data bc is supplied directly from the bar code data input line 4 to each of the bar code decoders 11 to 14 of the decoder unit 1. Is the same as

This embodiment is different from the first embodiment in that the order of operation selection in each of the barcode decoders 11 to 14 of the decoder unit 1 is set so that the order of the barcode decoders 11 to 14 which succeeded in decoding last time is the earliest. The operation at the time of this setting will be described below. However, after the decoding order setting unit 24 determines the operation selection order of the barcode decoders 11 to 14 of the decoder unit 1, the decoder unit 1 , The operation of the circuit including the counter 2 and the OR gate 3 is the same as that of the first embodiment, and the description of the operation at this point is omitted.

The operation of setting the operation selection order in each of the bar code decoders 11 to 14 in the decoding order setting section 24 will be described. In this case, too, one decoder in the decoder section 1 last time, for example, , Barcode data bc is successfully decoded by the barcode decoder 12 of the C39 system. In this case, each decoding order memory 2
6, 28, 30, and 32, that is, the first to fourth storage contents
It is assumed that the order signals od1 to od4 are set so that the respective barcode decoders 11 to 14 are selectively operated in this order.

When the bar code decoder 12 successfully decodes the bar code data bc, the decode data dd is output to the decode data output line 5 and the ok signal is output to the decode success signal output line 6. The ok signal is output to the decoding order setting unit 24.
Is supplied to the decoding order switching signal generator 25. At this time, when receiving the ok signal, the decoding order switching signal generator 25 receives the first and second decoding order comparators 37 and 39.
Generates an output and outputs first and second write signals w1, w1
2 results. On the other hand, the third and fourth decoding order comparators 4
Since the outputs 1 and 43 do not generate an output, only the AND gate 47 satisfies the logical product condition, and the second setting signal s2 is generated at the output of the AND gate 47. Then, these signals w
When s2 and s2 are supplied to the second decoding order memory 28 and the second decoding order switching unit 29, the second decoding order memory 28 stores the first preset signal pr1 and transfers the signal pr1 to a new preset signal pr1. This is output as the second order signal od2. Also, the second decoding order switch 29
Supplies the second rank signal od2 that has been output so far to the first decode rank memory 26, which stores the second rank signal od2 and converts the signal pr2 to a new one. The first order signal od1 is output. For this reason, the storage contents of the first decoding order memory 26 and the second decoding order memory 28 are inverted, and the new first order signal od1 selects the bar code decoder 12 of the C39 system first. After that, the barcode decoder 11 of the JAN system operates selectively.

In the present embodiment, an example was described in which the bar code data bc was successfully decoded by the C39 system bar code decoder 12 in the decoder unit 1 last time.
As well as other barcode decoders, such as JAN
Barcode decoder 11, NW7 barcode decoder 13, ITF system barcode decoder 14
The same applies to the case where the decoding of the barcode data bc has been successful.

In general, when barcode data of a certain system was supplied last time, the barcode data supplied next time is also very often barcode data of the above system. The present embodiment is configured by paying attention to this point.

That is, in this embodiment, when the barcode data bc is successfully decoded the previous time, when the next barcode data bc is decoded, the barcode decoder of the same system as the previous system is selected again. Not only saves the time for writing barcode data to the count value memory, but also makes it possible to considerably reduce the time from when barcode data reading is started until it is decoded. Required memory (RAM) due to non-use of the count value memory
The effect is that a small capacity is sufficient.

FIG. 7 is a block circuit diagram showing a fourth embodiment of the automatic identification decoding apparatus according to the present invention.

In FIG. 7, the same components as those shown in FIGS. 1, 2 and 4 are denoted by the same reference numerals.

This embodiment is a combination of the above-described second and third embodiments. In the second embodiment, a decoding order setting unit is provided on the output side of the counter 2. It is a configuration that is arranged.

The operation of the present embodiment is performed by combining the operation of the above-described second embodiment and the operation of the third embodiment, and the effect thereof is the same as that of the above-described second embodiment. Since it has the effect of the third embodiment and the effect of the third embodiment, the description of the operation and the effect is omitted.

[0087]

As described above, according to the present invention,
The read barcode data is supplied to each of the barcode decoders 11 to 14 without passing through the count value memory, and the barcode data is decoded by the sequentially selected barcode decoders 11 to 14.

Therefore, the time required to write barcode data in the count value memory is saved, and the time from when barcode data is read to when it is decoded can be shortened. There is. Further, since the count value memory is not used, there is also an effect that a small memory (RAM) is required.

[Brief description of the drawings]

FIG. 1 is a block circuit configuration diagram showing a first embodiment of an automatic identification decoding apparatus according to the present invention.

FIG. 2 is a block circuit configuration diagram showing an example of a configuration of a decoder unit in the embodiment of FIG.

FIG. 3 is a block circuit diagram showing a second embodiment of the automatic identification decoding apparatus according to the present invention.

FIG. 4 is a block circuit diagram showing a third embodiment of the automatic identification decoding apparatus according to the present invention.

FIG. 5 is a block circuit configuration diagram showing an example of a configuration of a decoding order setting unit in the embodiment of FIG. 4;

6 is a block circuit configuration diagram showing an example of a configuration of a decoding order switching signal generation section in the decoding order setting section of FIG. 5;

FIG. 7 is a block circuit configuration diagram showing a fourth embodiment of the automatic identification decoding device according to the present invention.

FIG. 8 is a block diagram showing one example of a conventional automatic identification decoding device.

FIG. 9 is a block circuit diagram showing another example of a conventional automatic identification decoding device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Decoder part 2 Counter 3 OR gate 4 Barcode data input line 5 Decode data output line 6 Decoding success signal output line 7 All error signal output line 8 Error signal output line 9 Reset signal input line 10 Count signal output line 11 JAN system bar Code decoder 12 Barcode decoder of C39 system 13 Barcode decoder of NW7 system 14 Barcode decoder of ITF system 15 Decode selector 16 Maximum decoding number constant memory 17 Decoding number comparator 18 Inverter 19 Current decoding order memory 20 Current decoding order switching Device 21 first decode data memory 22 decode data comparator 23 second decode success signal output line 24 decode order setting unit 25 decode order switching signal generating unit 26 first Code order memory 27 First decode order switch 28 Second decode order memory 29 Second decode order switch 30 Third decode order memory 31 Third decode order switch 32 Fourth decode order memory 33 Fourth decode order switch 34 Decode order switch 35 Counter memory 36 First decode order constant memory 37 First decode order comparator 38 Second decode order constant memory 39 Second decode order comparator 40 Third decode order constant memory 41 Third decode order comparator 42 Fourth decoding order constant memory 43 Fourth decoding order comparator 44, 45, 46 Inverter 47, 48, 49, 50 AND gate

Claims (4)

(57) [Claims] A plurality of decoders of different digital data systems for decoding read digital data and a plurality of the decoders are sequentially selected and selected.
The decoded data of the digital data from the decoded data
A decoder including a decoder selector to output the composed a plurality of counters for sequentially progressive selection decoder selector, digital data read said each of said plurality of decoders of the decoder unit Supplied, and when decoded data of the digital data is obtained in any of the plurality of decoders, the decoded data is output, and the decoded data of the digital data is output by the selected decoder. An automatic identification decoding apparatus characterized in that when decoded data is not obtained, an error signal is supplied to the counter, whereby the selection of the plurality of decoders is advanced by only one. Between wherein said counter and said decoder unit, arranged to decode selection order switching means for selecting the output value of the real said counter output value or the previous decoding success from said counter, said decoder Decoding data comparing means for comparing the actual decoding data of the decoder section with the decoding data of the previous successful decoding, on the output side of the decoding section;
Is decoded when the two decoded data match.
2. The automatic identification decoding device according to claim 1, wherein the automatic identification decoding device outputs a data success signal . Wherein between the said decoder unit counter, automatic according to claim 1, characterized in that a decoding order setting means for changing the decoder selection order to the plurality of decoders in the decoder unit Identification decoding device. 4. A between the said decoder unit counter, a decoding order setting means for changing the decoder selection order to the plurality of decoders in the decoder unit
A decode selection order switching means for selecting the output value of the real said counter output value or the previous decoding success from said counter is arranged, on the output side of the decoder unit,
The decoded data comparing means for comparing the decoded data of the real decoding data and the previous successful decoding of the decoder unit arranged, the decoded data comparing means, before
Successful decoding when two decoded data match
Automatic identification decoding apparatus according to claim 1, wherein the outputting the signal.