JP2752928B2 - DSU-terminal connection method for INS net 64 - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
Information (Information N serviced by NTT)
basic interface of the network system, 6
The B channel of 4 Kbit / S is composed of two channels and the D channel of 16 Kbit / S is composed of one channel.
DSU (Digital) of K bit / S line
In particular, the present invention relates to a connection method applied when a DSU and a terminal are installed in a short distance, such as in the same device.

[0002]

2. Description of the Related Art FIG. 4 shows a frame format of a transmission signal in a conventional interface between a DSU for an INS network 64 and a terminal. FIG. 3 shows an example of the interface configuration between the DSU and the terminal.

A method of connecting a terminal interface of a DSU for the INS net 64 is described in ITU-I. It is recommended in the 400 series and is provided in a form conforming to this recommendation. Also, this interface is generally
User-network interface, or It is called an interface. (See ISDN, I Series International Standards and Technologies, Telecommunications Association P65-140;
NS corresponds to ISDN in an international standard. In FIG. 3, DSU 5 and terminal 6 are connected to data signal line 80.
Are connected by two pairs of signal lines. The DSU 5 is connected to the subscriber line 70 of the INS exchange, and has a function of terminating a signal on the subscriber line and converting a 2-wire half-duplex data signal into 4-wire data signals 201 and 202. And
Terminal 6 performs signal termination processing with DSU side and data signal 2
01, 202 into B1, B2, and D channels,
It is composed of a terminal adapter section 61 for converting the signal into a parallel signal and sending it out to the terminal internal bus 23, and a DTE main body 62.

A data signal 201 is a signal from the DSU to the terminal, and a data signal 202 is a signal from the terminal to the DSU, each having a frame format as shown in FIG. This frame format is composed of two B channels (B1 and B2 channels) of 16 bits per frame (64K bits / S) and 4 bits per frame (16K bits / S).
Bits / S) of D channel and frames such as F and L,
A signal for extracting bit synchronization or a 12-bit signal for controlling transmission / reception is added. A total of 48 bits per frame is a data signal of 192 Kbit / S.

[0005]

As described above, the conventional IN
The DSU-terminal interface for the S-net 64 is connected by two pairs of data signal lines, and the data signal on this signal line is a multiplexed 192 Kbit / S data signal. There is a problem in that the circuit becomes complicated due to the high speed of the data signal and the need for conversion such as multiplexing and extraction of a synchronous clock, and the size and cost of the device are increased.

[0006]

The INS net 6 of the present invention is provided.
The DSU-to-terminal connection method for 4 uses an interface between the DSU and the terminal in the 64 kHz line of the INS network by using a frame clock signal of 4 kHz synchronized with the line and 64 bytes for data transfer synchronized with the frame clock.
A pair of clock signal lines for transmitting a KHz transfer clock from the DSU to the terminal, and two B channel data signals of 16 bits per frame synchronized with the transfer clock and bidirectionally transmitted. And INFO3 for calling and terminating control.
The DSU from the terminal combined with information and Q bits
Direction D-channel data signal and two pairs of data-system signal lines for transmitting the D-direction D-channel data signal from the DSU combined with the DSU and line status indication, echo, and S bits to the terminal. doing.

[0007]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment. FIG. 2 is a configuration diagram showing a frame format of the data signal in FIG.

In FIG. 1, DSU 1 and terminal 2 are connected to six pairs of data signal lines 42 and two pairs of clock signal lines 41.
They are connected by a pair of signal lines. DSU1 is connected to the subscriber line 30 of the INS exchange, and performs signal termination processing on the subscriber line side and data signals of the two-wire half-duplex system B1, B.
The terminal 2 has a function of separating the signals into four channels of data signals 103 to 108 and a function of generating clock signals 101 and 102, respectively.
Signal termination processing with U side and clock signals 101 and 10
A terminal adapter unit 21 for converting the data signals 103 to 108 into parallel signals by the load timing signal 110 generated by the terminal adapter 2 and sending the parallel signals to the terminal internal bus 23;
And a main body 22.

Data signals 104, 106 and 108 and clock signals 101 and 102 are signals from the DSU to the terminal, and data signals 103, 105 and 107 are transmitted from the terminal to the DS.
Each of the U-direction signals has a frame format as shown in FIG. In FIG. 2, each signal is 250 μm.
s, a 16-bit signal per frame, with a transmission rate of 64
It is a K bit / S signal. That is, a clock signal 101 of a 4 KHz frame clock, a clock signal 102 of bit synchronization, and B data signals 103 to 1 of two B channels (B1 and B2 channels) of 16 bits per frame.
06 and SI1, S in the D channel of 4 bits per frame
This is a total of eight signals of D data signals 107 and 108 to which each signal for transmission / reception control such as I2 and SI3 is added.

[0010]

As described above, according to the present invention, although the number of data signal lines increases, each data signal is a low-speed signal of 64 Kbit / S, and the frame structure is simplified. Since the data is continuous in bit units, particularly in the terminal 2, when the S → P conversion, the P → S conversion, or the load timing signal 110 of the TA 21 of the terminal adapter unit is generated, the terminal 2 can be configured with a general-purpose small MSI. . Therefore, there is an effect that the H / W scale of the DSU and the terminal can be reduced and the price can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a frame format in FIG. 1;

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a configuration diagram showing a frame format in FIG. 3;

[Explanation of symbols]

 1 DSU 2 Terminal 21 TA 22 DTE main body 23 Terminal internal bus 30 Subscriber line 41 Clock signal line 42 Data signal line

Continuation of the front page (56) References JP-A-4-68648 (JP, A) JP-A-63-305651 (JP, A) JP-B-6-40647 (JP, B2) Patent 2540824 (JP, B2) Trademark Registration No. 3045806 Trademark registration No. 3084131 (58) Fields investigated (Int.Cl. ⁶ , DB name) H04L 12/02 H04M 11/00 303 H04J 3/00

Claims (1)

(57) [Claims] 1. An interface between a DSU and a terminal in a 64 kHz line of an INS network, a frame clock signal of 4 kHz synchronized with the line and a transfer clock of 64 kHz for data transfer synchronized with the frame clock are transmitted from the DSU to the terminal. 2 for transmission to
A pair of clock-system signal lines, four pairs of data-system signal lines for synchronizing with the transfer clock and transmitting two B-channel data signals of 16 bits per frame bidirectionally, and The DSU data signal in the direction of the DSU from the terminal combined with the INFO3 information and Q bit of
A DSU-terminal connection method for the INS network 64, wherein the connection is made with two pairs of data-system signal lines for transmitting a D-channel data signal from the DSU combined with bits to the terminal.