JP2752278B2 - Timing control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a high-speed power supply and equipment provided in the fields of nuclear fusion devices and particle accelerators.
The present invention relates to a timing control device that performs timing control with high accuracy.

[0002]

2. Description of the Related Art A nuclear fusion device will be described as an example of the prior art. Generally, a fusion device performs two-stage heating in order to raise the temperature of generated plasma. One of the means is heating by a neutral particle injection device.

[0003] This neutral particle injector has a configuration as shown in FIG. 3 and operates as follows. That is, the hydrogen gas (A) is ionized by the arc current I of several thousand A into hydrogen ions (B) in the ion source 1 and accelerated as a hydrogen ion (B) beam by the acceleration electrode 2 of several tens of KV. The hydrogen ion (B) beam accelerated in the ion source 1 is converted into a neutral particle (A) beam by charge exchange in the neutralization cell 3. This neutral particle (A) beam passes through the vacuum container 4 of the neutral particle injector and additionally heats the plasma P inside the vacuum container 5 of the fusion device.
At this time, hydrogen (B) not neutralized in the neutralization cell 3
The deflecting magnet 6 prevents the beam from being incident on the plasma P.
The hydrogen (B) beam is forcibly deflected by the magnetic field generated by the current (deflecting magnet current), and collides with the beam damper 7 to be cooled, thereby capturing the hydrogen (B) beam that has not been neutralized.

The high-speed shutter 8 separates the vacuum container 4 of the neutral particle injector from the vacuum container 5 of the fusion device, and maintains the inside of the vacuum container 5 of the fusion device at a high vacuum. It is normally closed and is only opened for a very short time when the neutral (A) beam is incident. The vacuum pump 9 of the neutral particle injector is a device for maintaining the vacuum container 4 of the neutral particle injector at a high vacuum.

Such a neutral particle injector needs to be operated at an output of several tens of MW in order to additionally heat the plasma P to a high temperature, and the arc current and acceleration voltage in the ion source 1 are large currents. High voltage. Further, the confinement time of the plasma P generated by the nuclear fusion device is only a few hundred msec at present. In order to make the neutral particle (A) beam incident efficiently within this short time,
Injection start timing and injection stop timing are mse
It must be set in units of c. That is, in the neutral particle injection device, the operation pause time and the operation continuation time of the arc current, the acceleration voltage, the deflecting magnet current, the high-speed shutter, etc. are set to ms.
It must be set in units of ec.

Next, a method of setting the timings of the operation pause time and the operation continuation time of the power supply and equipment such as the arc current, acceleration voltage, deflection magnet current, and high-speed shutter of the neutral particle injector will be described with reference to the time chart of FIG. It will be described using FIG.

[0007] The master pulse is a pulse serving as a reference for the incident timing of the neutral particle (A) beam output from the control device of the fusion device main body. After the input of the master pulse, each timer operates to generate each timing signal, and based on these, a control signal is sent to each power supply and device, so that a neutral particle (A) beam is incident. Note that the operation pause time described here is the time after the master pulse is input.
It is a waiting time until each power supply and device operates, and the operation continuation time is a continuation time during which each power supply and device operates.

[0008] Further, after the master pulse is input, the arc current becomes
After the arc current operation stop time Ta passes, the operation is performed for the arc current operation continuation time Tb. The acceleration voltage operates for the acceleration voltage operation continuation time Td after the acceleration voltage operation pause time Tc elapses after the input of the master pulse. After the input of the master pulse, the deflecting magnet current operates for the deflecting magnet current operation continuation time Tf after the deflecting magnet current operation suspension time Te elapses.
In the high-speed shutter, the high-speed shutter operation pause time Tg elapses after the master pulse is input, and the high-speed shutter operation continuation time T
Only h works.

The operation suspension time T of each power supply and device
a, Tc, Te, Tg are from the minimum number msec to the maximum number sec.
c, the operation continuation times Tb, Td, Tf, and Th are the minimum number of ms.
It is possible to arbitrarily set a time of about 10 msec from ec. The control of the operation pause times Ta, Tc, Te, Tg and the operation continuation times Tb, Td, Tf, Th for outputting each control signal of such a time chart is performed by a timing control device.

Next, a conventional timing control device for a neutral particle injector will be described with reference to FIG. In this figure, for simplicity of description, a timing control device for controlling an operation pause time of a certain control signal for each power supply and device of the neutral particle injector is taken.

In this timing control device, it is necessary to preset a set value corresponding to the operation suspension time in order to control the operation suspension time. First, the set value is manually input to the setter 10, and the setter 10 outputs the counter setting data as the operation pause time calculated internally based on the set value to the memory 12 via the data bus 11a for setting. I do.
In this conventional example, a part of the timing control device is taken up, and a plurality of similar circuits are actually provided. Therefore, the counter setting data corresponding to each memory of a plurality of timing controllers (not shown) is
0 is set, and the time for this setting is usually several tens
It takes about 0 ms. Then, after outputting the counter setting data to the memory 12, the setting device 10 outputs the OR circuit 1
The OR circuit 13 outputs the preset pulse m to the down counter 14 as the preset pulse n. When the down counter 14 receives the preset pulse n, the counter setting data in the memory 12 is set as a count value via the data bus 11b, and the operation of the timing control device can be started.

An operation switch 15 for operating the operation of the timing control device is a switch that outputs a latch signal in an alternate type. By the closing operation of the operation switch 15, the operation start signal a is output to one input terminal of the AND circuit 16 and the inverter 17. The inverter 17 inputs the operation start signal a and outputs it as an operation stop signal c to one input terminal of the OR circuit 18 after the inversion processing. This OR circuit 1
Reference numeral 8 inputs the operation stop signal c and the timing pulse 1 to perform an OR process, and outputs a reset signal d to one input terminal R of the SR flip-flop 19 and the D flip-flops 20 and 21.

The master pulse b is output from the control unit of the main body of the fusion device (not shown) as a reference signal for the timing of incidence of the neutral particle beam at a predetermined time period during operation. Entered at the end. The AND circuit 16 performs an AND process on the input operation start signal a and the master pulse b, and outputs a start pulse e to the set input terminal S of the SR flip-flop 19. In the SR flip-flop 19, when a start pulse e is input to the set input terminal S, the output terminal Q
Outputs the latched start signal f. On the other hand, when the reset signal d is input to the reset input terminal R, the output is reset.

Since the master pulse b and the clock g output by the clock generator 22 are aperiodic signals, the D-type flip-flop 20 serves as a synchronization circuit for synchronizing the signal from the master pulse b with the clock g. , 2
1 is provided. In this D-type flip-flop 20,
The start signal f is input to the input terminal D, the clock g is input to the input terminal CK, and the logical level of the start signal f is latched at the rising edge of the clock g (where the logical level changes from the logical level L to the logical level H). From the output terminal Q, a one-stage synchronization output signal h in which the start signal f and the clock g are synchronized within one clock is output. However, when the rising edge of the clock g is input while the start signal f input to the D-type flip-flop 20 changes from the logical level L to the logical level H, the one-stage synchronous output signal h becomes Incorrect outgoing output. To prevent this, a D-type flip-flop 21 is provided, and this D-type flip-flop 21 outputs a two-stage synchronous output signal i obtained by synchronizing the one-stage synchronous output signal h and the clock g without any illegal transmission output with one clock. Output. The D-type flip-flops 20, 2
Clock g as the synchronization processing time TT of the synchronization circuit by
It takes time from one clock to two clocks.

On the other hand, when the reset signal d is input to the reset input terminal R, the output signals of the D-type flip-flops 20 and 21 are reset. The AND circuit 23 receives the two-stage synchronous output signal i and the clock g, performs an AND process, and outputs a synchronous clock j. The down counter 14 receives the synchronous clock j and subtracts it from the preset count value for each synchronous clock j. When the count value of the down counter 14 becomes zero, a counter output pulse k is output to the pulser 24, and the pulser 24 outputs a timing pulse 1 having a predetermined pulse width to a control device (not shown).

The OR circuit 13 inputs a timing pulse 1 for resetting the count value of the down counter 14 and outputs the same to the down counter 14 as a preset pulse n. In the down counter 14, the preset pulse n
Is input, the counter setting data of the memory 12 is set as the count value via the data bus 11b.

Next, the operation of the conventional apparatus will be described with reference to a time chart shown in FIG. First, the frequency of the clock g output from the clock generator 22 is selected. This frequency serves as a reference for the minimum unit of the counter setting data by the down counter 14. If the clock generator 22 of 1 KHz is selected, the minimum unit (cycle time of one clock) in this case is 1/1 KHz = 1 ms. At this time, in order to set the set value, the contact of the operation switch 15 of the timing control device is in an open state, and the operation stop signal c is at the logic level H, and the timing control device is stopped.

Next, for example, the setter 10 sets a 5-count delay time TDA (5 × 1) as counter setting data.
/ 1KHz = 5ms). The set value is the synchronization processing time TT (1 clock to 2 clocks) as described above.
Is set in the setting device 10. The deviation within one clock caused by the synchronization processing time TT becomes an error time, which can be adjusted by changing the clock g of the clock generator 22.

At time t0, the counter setting data is stored in the memory 1
When setting to 2 is started, a setting processing time TS of about several hundred ms is required. Thereafter, when the setting unit 10 outputs the setting pulse m at the time point t1, the setting pulse m is input to the down counter 14 as the preset pulse n via the OR circuit 13. Thereby, the count value (5 counts) of the memory 12 is input. When the setting of the counter setting data is completed in this way, the operation preparation of the timing control device is completed.

Thereafter, when the operation start signal a of the logic level H is output as the closing operation of the contact of the operation switch 15 at time t2, the operation stop signal c and the reset signal d become the logic level L.

Subsequently, when a master pulse b is input from the control device side of the fusion device at the time t3, the start pulse e becomes a logic level H having only the same pulse width as the master pulse b, and the start signal f is output as a latched signal of logic level H. D-type flip-flop 2
At 0, after the start signal f becomes the logic level H, 1
At the rising edge of the clock g of KHz, the latched one-stage synchronization output signal h of logic level H is output at time t4.
Then, from the time t3, the D-type flip-flop 21
At the time point t4 when the one-stage synchronization output signal h becomes the logic level H, the latched two-stage synchronization output signal i of the logic level H is output at the rising edge of the clock g of 1 KHz. That is, the D-type flip-flop 21 outputs the two-stage synchronization output signal i at the time point t2 after the elapse of the synchronization processing time TT from the time point t3.

In the AND circuit 23, the two-stage synchronous output signal i
Becomes the logic level H, the signal of the master pulse b and 1K
A 1 KHz synchronous clock j synchronized with a 1 Hz clock g is output during TDA. The down counter 14 is 1K
Hz synchronous clock j is input, and a preset 5
The count value is subtracted every clock (1 ms), and the counter output pulse k is output when the count value becomes zero, that is, at time t6 after 5 ms. This counter output pulse k has a delay time from the rising edge of master pulse b of 6 ms to 7 ms = 5 ms + (1 ms to 2 ms).
ms). This counter output pulse k is applied to the pulser 24
Is input, and the timing pulse l is set to O with a predetermined pulse width.
Output to the R circuit 13 and the OR circuit 18. The down counter 14 receives the preset pulse n from the OR circuit 13 and resets 5 counts in the memory 12. Also, SR
Type flip-flop 19, D-type flip-flop 20,
21 is reset by a reset signal d from the OR circuit 18. In the operation from the time point t0 to the time point t6, each time the master pulse b is input, the timing of the neutral beam injector for each power supply and device is controlled.

When the timing is changed, it is necessary to stop the operation by setting the operation stop signal c to the logic level H by opening the contact of the operation switch 15 of the timing control device. The reason is that the set processing time TS
Takes about several hundred milliseconds, and since it is not known when the setting process is performed, the down counter 14 may perform the setting process while the count value is being subtracted. At this time, there is a danger that the down counter 14 operates abnormally and outputs abnormal timing to each power supply and equipment of the neutral particle injector. Therefore, after the timing control device is put into the operation stop state at the time point tx, from the time point t7 to the time point t8, the setting unit 10 sets the counter setting data as a delay time TDB (3 × 1/1
KHz = 3 ms). After a setting processing time TS of about several hundred ms for setting the counter setting data in the memory 12, the setting device 10 outputs a setting pulse m,
The preset pulse n is input to the down counter 14,
Thereby, three counts of the memory 12 are input, and the setting of the counter setting data is completed. Thereafter, when the contact of the operation switch 15 is closed at time t9, the operation start signal a
Becomes the logic level H. Then, the master pulse b is input at the time t10, and the time t10 is t1 in the same manner as described above.
At time t11 after the synchronization processing time TT at one time, the down counter 14 counts three counts of the delay time TDB (3 ms) by one.
Decrease by count. At time t12 after the delay time TDB,
A timing pulse 1 is output. This controls the timing of the neutral particle injector for each power supply and equipment. This series of operations is performed every time the master pulse b is input.

[0024]

However, in the above-described conventional apparatus, when changing the timing of a control signal for each power supply and equipment of the neutral particle injector, the timing control apparatus must be stopped. There is such a problem.

That is, since a plurality of set values for each of the above-mentioned timings are manually changed by the setter 10, it takes several minutes to several tens of minutes as a change time. Also need to be stopped. Therefore, after changing the set value of the neutral beam injector,
Even if the operation is restarted, it takes an aging time until the temperature of the ion source 1 of the neutral particle injector rises and a stable neutral particle beam is incident. As described above, every time the set value is changed, the operation of stopping and starting the operation and the aging time are required, and there is a problem that operability and efficiency are poor.

It is therefore an object of the present invention to provide an efficient timing control device capable of reliably changing a counter set value for outputting a timing signal during operation.

[0027]

According to the present invention, counter setting data is set in a counter , and the counter setting data is
Count operation synchronized with the set counter to the reference clock
Are allowed, at a timing controller for controlling timing of device operation by generating a timing signal based on the counter setting data of the counter, and the first and second memory for setting counter setting data to said counter, said the first or one of the main of the second memory
Select the counter setting data of the memory
There a switcher that enables read, the timing control instrumentation
When changing the counter setting data during operation of the
New memory in the other memory not selected by the switch.
Counter data, and select the switch.
A setting device for switching the selection to the other memory side .

[0028]

According to the above configuration, the change of the counter setting value from the current counter setting data to the new counter setting data can be switched in a short time by hardware processing.
When the set value is changed during operation in the conventional one-stage configuration memory, the software is stored in the memory by software while the counter is not operating so that the new counter setting data and the current count setting data are not mixed. Counter setting data had to be input, but there is no time limit for such software processing, and new counter setting data and current counter setting data can be reliably set during operation of the timing controller. The value can be changed.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a timing control device showing one embodiment of the present invention. The same reference numerals as those in FIG. 5 indicate the same or corresponding parts. 5 is different from FIG. 5 in that a first memory 25 and a second memory 26 are provided instead of the memory 12, and a switch 27 for switching these memories under predetermined conditions is provided. Data buses 28a, 28 are provided between the setting device 10, the first memory 25, the second memory 26, the switching device 27, and the down counter 14, respectively.
b, 28c and 28d.

In this embodiment, the setting device 1 is used when the operation is stopped.
When a set value is manually input from 0, the data bus 28
The first counter setting data is output only to the first memory 25 via a. When the operation is stopped, the switching signal o is at the logical level L, and the switch 27 selects the first memory 25 based on the switching signal o. Thereafter, the setting device 10 outputs the setting pulse m, and the count value is set in the down counter 14. Next, when the set value is manually input from the setting device 10 during operation, the data bus 28a is transferred to either the first memory 25 or the second memory 26 not selected from the state of the switching signal o at this time. Via the first counter setting data or the second counter setting data. Thereafter, when the master pulse b is input, the setting device 10 switches the switching signal o and outputs the setting pulse m,
The first memory 25 or the second memory 25 within one cycle of the clock g
Of the down counter 14 via the data bus 28b or the data bus 28c and the data bus 28d. As described above, during the operation of the present embodiment, when a new set value is input and the master pulse b is input, the mode is switched to either the first memory 25 or the second memory 26, and The setting value is changed from the counter setting data to the current counter setting data.

Next, the operation of this embodiment will be described with reference to the time chart of FIG.

First, the frequency of the clock generator 22 is selected to be, for example, 1 KHz. At this time, the operation stop signal c is at the logical level H, and the timing control device is stopped.
Here, the setting unit 10 sets the first counter setting data as the first counter setting data in the setting processing time TS of about several 100 ms from the time point t0 to the time point t1, for example, a delay time TDA of 5 count values.
(5/1 KHz = 5 ms) is input and set only in the memory 25. Thereafter, when the setter 10 outputs the set pulse m at the time point t1, the preset pulse n is input to the down counter 14 via the OR circuit 13. As a result, 5 counts of the first memory 25 are set in the down counter 14. When the setting of the counter setting data is completed in this way, the operation preparation of the timing control device is completed.

In this state, the contact of the operation switch 15 is set at t2.
When the operation start signal a of the logic level H is output as the closing operation at the time, the operation stop signal c and the reset signal d become the logic level L. Next, when the master pulse b is input from the control device side of the fusion device main body to the AND circuit 16 at time t3, the start pulse e is input to the SR flip-flop 19, and the same amount of pulses as the master pulse b is input. Only the width becomes the logic level H, and the start signal f is output as a latched signal of the logic level H.

The D-type flip-flop 20 outputs the latched one-stage synchronous output signal h of the logic level H at the rising edge of the clock g of 1 KHz at the time t4 after the start signal f becomes the logic level H. Then, the D-type flip-flop 21 outputs the latched two-stage synchronization output signal i of the logic level H at the rising edge of the clock g of 1 KHz at the time t5 after the one-stage synchronization output signal h becomes the logic level H. .

When the two-stage synchronization output signal i attains the logic level H, the AND circuit 23 outputs the signal from the master pulse b and 1
The synchronous clock j of 1 KHz synchronized with the clock g of KHz is output as five counts of the delay time TDA. When the down counter 14 receives the 1 KHz synchronous clock j,
Subtraction is performed every clock (1 ms) from the preset 5 counts, and when the count value becomes zero, that is, 5 m
At t6 after s, the counter output pulse k is output. This counter output pulse k has a delay time from the rising edge of master pulse b of 6 ms to 7 ms = 5 m +
(1 ms to 2 ms). This counter output pulse k
The pulser 24 that has input the pulse signal outputs a timing pulse 1 with a predetermined pulse width. The down counter 14 receives the preset pulse n from the OR circuit 13 and resets 5 counts in the first memory 25.

The operation from time t0 to time t6 is as follows.
It repeats every time the master pulse b is input. Thus t
Until the time point x, the same operation as the time chart of FIG. 6 described in the conventional apparatus is performed, and the down counter 14 is set and operated using only the first memory 25.

Next, at time tx, for example, the delay time T as the second counter setting data of three count values
DB (3/1 kHz = 3 ms) is input during operation. In this case, since the switching signal o is at the logic level L, the second memory 26 not used in the current operation is stored in the second memory 26 for several hundred ms from time t7 to time t8. Set processing time TS
Later, it is set.

Thereafter, when the master pulse b is input at time t9, the setter 10 switches the switching signal o to the logic level H because new data of the delay time TDB is input as the second counter setting data. Be replaced. Then, the set pulse m is output, and the down counter 14 inputs three counts of the second memory 26 by the preset pulse n.

The set value change time TU from the input of the master pulse b to the change of the memory to change the count value of the down counter 14 is equal to one cycle (1) of the clock g.
ms). Next, the start pulse e is set to SR
The type flip-flop 19 receives and outputs the two-stage synchronous output signal i latched at the logical level H at the rising edge of the clock g of 1 KHz by the D-type flip-flops 20 and 21 at time t10 in the same manner as described above. At this time, the synchronization processing time T by the D-type flip-flops 20 and 21
Since T is within two clocks from one clock, the setting value change time TU described above is shorter than the synchronization processing time TT, so that the setting is performed without any trouble in the control time operation of the timing control device.

Next, the AND circuit 23 outputs 2 at time t10.
When the stage synchronization output signal i becomes the logic level H, the signal from the master pulse b and the clock g of 1 KHz
Hz synchronous clock j is output. Down counter 14
When a synchronous clock j of 1 KHz is input, a preset 3 count value is subtracted every clock (1 ms),
The counter output pulse k is output at time t11 when the count value becomes zero, that is, after 3 ms. This counter output pulse k has a delay time from the rising edge of the master pulse b of 4 ms to 5 ms = 3 ms + (1 ms to
2 ms). When the counter output pulse k is input, the pulser 24 outputs the timing pulse 1 with a predetermined pulse width, and the down counter 14 receives the preset pulse n from the OR circuit 13 and outputs the three count values of the second memory 26. To reset.

Thereafter, during operation with the three counts of the second memory 26, a new count of 6 is stored in the first memory 25.
When the count is stored in the first memory 25 by the setting device 10 and the master pulse b is input, the switching signal o to the switching device 27 becomes the logic level H. Then, the setting pulse m is input, and 6 counts of the first memory 25 are set in the down counter 14.

The above-described series of operations is repeated every time the master pulse b is input, and the neutral particle injector is operated by controlling the timing of each power supply and equipment. In this manner, in this embodiment, the timing setting memory has a two-stage configuration of the first memory 25 and the second memory 26, detects the master pulse which is a reference of the operation cycle, and sets the setting value for change. When input, the first
Is switched from the current setting value as the first counter setting data of the memory 25 to the new setting value of the second memory 26 as the second counter setting data, and the counter setting data of the first memory is changed. Can be set. Therefore,
Since the set value can be changed efficiently and in a short time during operation,
The operation of stopping the timing control device and the neutral particle injector for changing the set value, the operation for restarting the operation after stopping the operation, the aging time of the neutral particle injector, and the like become unnecessary.

The present embodiment can be applied to change of set values for analog control or the like by the same means as described above.

[0045]

As described above, according to the present invention, a timing control device for generating a timing signal, a stop operation of a device controlled by the timing control device, and a drive operation for restarting after stopping the operation. And the time required for the operation becomes unnecessary. Therefore, an efficient and reasonable timing control device can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a timing control device showing one embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of FIG. 1;

FIG. 3 is a schematic diagram illustrating a neutral particle injector.

FIG. 4 is a time chart for explaining the operation of the neutral particle injector.

FIG. 5 is a configuration diagram showing one example of a timing control device showing a conventional example.

FIG. 6 is a time chart for explaining the operation of FIG. 5;

[Explanation of symbols]

 Reference Signs List 10 Setting device 13, 18 OR circuit 14 Down counter 15 Operation switch 16, 23 AND circuit 17 Inverter 19 SR type flip-flop 20, 21 D type flip-flop 22 Clock generator 24 Pulser 25 First memory 26 Second memory 27 Switch

Claims (1)

(57) [Claims] 1. A counter setting data is set in a counter, and the counter is set based on the counter in which the counter setting data is set.
A timing control device that performs a counting operation in synchronization with a quasi-clock, generates a timing signal based on counter setting data of the counter, and controls the timing of device operation, a first control device for setting counter setting data in the counter. And a second memory, and one of the first and second memories.
Selects the counter setting data and reads the counter.
Switch that can be output and counter setting data during the operation of the timing controller.
Is not selected by the switch when the other
When writing new counter setting data to the memory of
The selection of the switch is switched to the other memory side.
Timing control apparatus characterized by comprising a obtaining setter.