JP2748478B2 - Constant voltage generator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant voltage generating circuit, and more particularly to a constant voltage circuit using a Schottky gate type field effect transistor (MESFET).

[Conventional technology]

Conventionally, the output of a semiconductor circuit is connected to a source-coupled FE
When configured with a T-logic (SCFL) or source follower, a field-effect transistor (FE
A predetermined voltage is applied to the gate of T) by, for example, the circuits shown in FIGS. 8A and 8B, and a predetermined gate-source voltage is obtained between the gate and the source connected to the negative power supply Vss. It has become.

FIG. 3A shows that a power supply voltage is divided by resistors R1 and R2 connected in series between a negative power supply Vss and ground, and a desired voltage is obtained from a terminal OUT at a connection point between the resistors R1 and R2. This is applied to the gate of a current source FET (not shown).

FIG. 3B shows that a resistor R is connected between the negative power supply Vss and the ground.
3 and a plurality of diodes D1 to D3 connected in series. And these diodes D1 to D3
Using the sum of the forward voltages generated between the terminals, a constant voltage of a desired value is applied to the terminal at the connection point between the diode D1 and the resistor R3.
It is obtained from OUT and applied to the gate of the current source FET.

[Problems to be solved by the invention]

However, in the conventional voltage supply circuit based on the resistance division shown in FIG. 8A having the above configuration, the voltage appearing at the output terminal OUT changes due to the voltage fluctuation of the negative power supply Vss, and is always constant with respect to the negative power supply Vss. There is a problem that a stable voltage cannot be obtained. Further, in the voltage supply circuit using a plurality of diodes D shown in FIG. 6 (b), the forward voltage of each diode D fluctuates due to a change in ambient temperature, and the voltage supply circuit shown in FIG. Similarly, there is a problem that a stable voltage cannot always be obtained with respect to the negative power supply Vss.

The present invention has been made in order to solve such a problem, and is not affected by a change in the ambient temperature, and constantly keeps a stable voltage with respect to the power supply voltage in accordance with the power supply voltage fluctuation. An object of the present invention is to provide a constant voltage circuit that generates the voltage.

[Means for solving the problem]

The present invention provides a first resistor having one end connected to a reference potential, a second resistor connected in series with the first resistor, an anode connected to one end of the second resistor, and a diode connected to a power supply at a cathode. , A voltage-dividing resistor connected in parallel to divide the voltage between the anode and the cathode of the diode to generate a divided voltage, a drain connected to the reference potential, and a gate connected to the first and second gates. A first FET connected to a connection point of the resistor of the first FET, a second FET having a drain connected to the source of the first FET, a gate connected to the anode of the diode, and a drain connected to the source of the second FET A third FET connected to the power supply and having a source connected to the power supply and a gate receiving the divided voltage, wherein the voltage dividing resistor has a voltage that reduces the drain-source current of the third FET from being affected by the ambient temperature change. Is the gate of the third FET It applied to, and voltage drain-source current of the second FET when the current flows through the second FET is greatly affected by the ambient temperature changes the second FE
The second FET and the third
Adjust the gate width ratio with the FET, and use the first and second
Are set so that the drain-source voltage of the second FET is the same as that of the third FET.

[Action]

The change in the forward voltage of the diode due to the change in the ambient temperature is almost constant regardless of the change in the ambient temperature. Is compensated by the fluctuation of the gate-source voltage of the second FET which is greatly affected by the above. Further, the power supply voltage fluctuation hardly affects the voltage between the terminals of the diode and the operation of the source follower.

Further, as for the drain-source voltage applied to each of the second and third FETs, the voltage divided by the first and second resistors is transmitted to the drain of the second FET via the first FET. As a result, the drain and source currents of the second and third FETs are close to each other with respect to the temperature characteristics.

〔Example〕

 Next, the present invention will be described in detail below with reference to the drawings.

 FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In the figure, one end of a resistor R4 is grounded and becomes a reference potential, and a resistor 5 is connected to the resistor R4 in series.
The other end of the resistor R5 is connected to the anode of the diode D. The cathode is connected to the negative power supply Vss, and a forward voltage is applied between the terminals of the diode D. The drain of the first Schottky gate field effect transistor FET1 is grounded, and the gate is connected to the connection point between the resistors R4 and R5. The source of this FET1 is connected to the drain of the second Schottky gate field effect transistor FET2, the gate is connected to the anode of the diode D, and the source is connected to the output terminal OUT. For this reason, the voltage between the terminals of the diode D, that is, the anode potential of the diode D is applied to the gate of the FET 2, and the gate of the FET 2
The signal is transmitted to the output terminal OUT via the source.

The drain of the third Schottky gate field effect transistor FET3 is connected to the source of FET2.
The source of FET3 is connected to the negative power supply Vss. The threshold voltage Vth of FET3 is set at about -0.3 [V], and a voltage obtained by dividing the voltage between the terminals of diode D by resistors R6 and R7 is applied to the gate of FET3. Vg applied between gate and source of
The resistance values of the resistors R6 and R7 are set so that s is about 0.3 to 0.5 [V]. Therefore, as described later, FET3
The drain-source current Ids is less affected by changes in ambient temperature. Note that FET2 and FET3
The series circuit constituted by constitutes a source follower circuit, and FET1 constitutes a source follower circuit together with FET3.
Sets the drain voltage of FET2.

FIG. 2 is a graph showing the voltage-current characteristics of the diode D shown in FIG. 1. The horizontal axis represents the forward voltage V, and the vertical axis represents the forward current I.

In the figure, a curve 1 shown by a solid line represents a characteristic when the ambient temperature is at room temperature, and a curve 2 shown by a broken line represents a characteristic when the ambient temperature rises to some extent from room temperature. As can be understood from the figure, when a current Ia is applied to the diode D in the forward direction at room temperature, the voltage appearing between these terminals becomes Va, but when the ambient temperature where the diode D is placed rises, the same current Ia is applied. Even if current is applied in the forward direction, the voltage appearing between the terminals drops to Vb.

Therefore, the diode D in the circuit shown in FIG.
Since a substantially constant forward current flows through the negative power supply Vss, the anode potential decreases as the ambient temperature increases, and has a negative characteristic with respect to a change in the ambient temperature.

Fig. 3 shows the gate-source voltage Vgs of a general MESFET.
6 is a graph showing the relationship between (horizontal axis) and drain / source current Ids (vertical axis).

In the figure, a curve 3 indicated by a solid line indicates characteristics when the ambient temperature is at room temperature, and a curve 4 indicated by a broken line indicates characteristics when the ambient temperature has risen to some extent from the room temperature. As can be understood from the figure, the drain-source current Id of the MESFET
s is the gate-source voltage Vgs is the threshold voltage Vth
It flows at the above time, and increases with an increase in the voltage Vgs. Also,
The fluctuation of the current Ids with respect to the change of the ambient temperature is largest when the voltage Vgs is near (voltage Vth + 0.2 to 0.4) [V], the current Ids increases with the temperature rise, and the voltage Vgs increases to (voltage Vt
h + 0.8-1.0) Nearly no change near [V]. For example, in the case of a MESFET having a voltage Vth of about -0.3 [V] as shown in the figure, the fluctuation of the current Ids is the largest when the voltage Vgs is around 0 [V], and almost not affected when the voltage Vgs is around 0.5 [V]. Characteristics.

For this reason, in the FET 3 in which the threshold voltage Vth is around -0.3 [V] and the gate-source voltage Vds is set to about 0.3 to 0.5 [V], the influence of the drain-source current Ids on the ambient temperature is affected. Is in a low state.

Further, the structure of the FET 2 is formed such that the gate width is 2 to 10 times the gate width of the FET 3, for example, when the gate width of the FET 3 is 10 μm, the gate width of the FET 2 is 40 μm . Further, the drain / source current Ids having the same value as that of FET3 flows through FET2, and the voltage Vgs of FET3 is 0.
Since the voltage is set to 3 to 0.5 [V], the voltage Vgs of the FET 2 is set to 0, which is greatly affected by the ambient temperature change, as shown in FIG.
[V].

Further, the resistance values of the resistors R4 and R5 are set such that the drain-source voltage Vds of the FET2 is substantially equal to the drain-source voltage Vds of the FET3. That is, the voltage obtained by subtracting the gate-source voltage Vgs of FET1 from the voltage appearing at the connection point of the resistors R4 and R5 becomes the potential at the drain of FET2, and by adjusting this drain potential, the voltage of each FET2 and FET3 is adjusted. Vds is set equal.

In such a configuration, a forward voltage V is applied between the terminals of the diode D, and a forward current I flows into the negative power supply Vss. Further, the anode potential of the diode D is transmitted to this source via the gate of the FET2,
By the stable voltage generated between the PN junctions, a voltage that is stabilized to the negative power supply Vss is output to the output terminal OUT.

As described above, when the ambient temperature rises, the anode potential of the diode D decreases (the anode-cathode voltage decreases) as described above. However, the source follower composed of the FET1, FET2, and FET3 operates as follows. The reduction in the potential is compensated, and a stable voltage is always output to the negative power supply Vss.

That is, a substantially constant drain-source current Ids flows through the FET 3 regardless of the rise in the ambient temperature. That is, FET
The drain / source current Ids of No. 2 is supplied with almost no change. For this reason, the gate-source voltage Vgs of the FET2 decreases under the influence of the ambient temperature change, and the gate potential of the FET2 increases with the temperature rise, and has a positive characteristic with respect to the temperature change. Therefore, the decrease in the anode potential of the diode D having a negative characteristic with respect to the ambient temperature is compensated for by the increase in the gate potential of the FET 2 having the positive characteristic, and the voltage output from the output terminal OUT is always constant regardless of the ambient temperature change. Be kept constant.

Further, a decrease in the voltage between the terminals of the diode D due to an increase in the ambient temperature results in a decrease in the resistance divided voltage by the resistors R6 and R7, which is also transmitted to the gate of the FET3. But this
The decrease in the gate potential of the FET D is slight, and the function of promoting the positive characteristic of the gate potential of the FET D is as follows. Therefore, in conjunction with the above-described operation of the source follower, the negative potential of the anode potential of the diode D is reduced. This compensates for the characteristics.

In other words, a slight drop in the gate potential of FET3 causes FET3
, The drain-source current Ids also slightly decreases. This FET
The decrease in the current Ids of 2 directly results in a decrease in the current Ids of the FET2, and the gate-source voltage Vgs of the FET2 decreases with a slight decrease in the current Ids. Therefore, the gate potential of FET2 rises slightly, which promotes this positive characteristic.

Also, even if the voltage of the negative power supply Vss fluctuates, the diode D
Since the voltage generated between the terminals has no effect, and the operation of the source follower is hardly affected by the fluctuation of the power supply voltage, the voltage output to the output terminal OUT is affected by the fluctuation of the negative power supply Vss. Following this, the voltage is always kept constant with respect to the negative power supply Vss.

Therefore, the voltage output from the constant voltage circuit according to the above embodiment is not affected by the change in the ambient temperature, and is always constant with respect to the power supply voltage following the power supply voltage fluctuation.

Further, as described above, since the drain-source voltage Vds of each FET2 and FET3 is equal, the output terminal O
The voltage output to the UT is output after being stabilized with respect to a change in the ambient temperature. This is understood as follows.

For example, suppose the circuit shown in FIG. 4 in which one resistor R8 is connected instead of the resistors R4 and R5 without the FET1 in FIG. 1, and a circuit in which the drain potential of the FET2 is not adjusted by the resistors R4 and R5. Considering each FE in this circuit
The drain-source voltage Vds of T2 and FET3 is different,
As described below, the stability of the voltage obtained at the output terminal OUT decreases.

In general, the relationship between the drain-source voltage Vds and the drain-source current Ids of the FET shows the characteristic schematically shown in FIG. In the figure, the horizontal axis represents the voltage Vds, and the vertical axis represents the current Ids. Curve 5 indicated by a solid line is a characteristic when the ambient temperature is room temperature, and curve 6 indicated by a broken line is a characteristic when the ambient temperature is increased from room temperature to some extent. Represents As can be understood from the figure, the current varies according to the voltage Vds applied to the FET.
The characteristics of Ids with respect to changes in ambient temperature are different, and the drain-source voltage applied to FET2 in the circuit shown in Fig. 4
Vds2 becomes larger than the drain-source voltage Vds3 applied to the FET3 of the same circuit, and the variation width ΔIds2, ΔIds3 of the current Ids with respect to the ambient temperature differs according to each of these voltages Vds2, Vds3.

Therefore, in the circuit shown in FIG.
The voltage obtained slightly changes depending on the ambient temperature as follows. That is, the decrease in the voltage between the terminals of the diode D due to the change in the ambient temperature is caused by the FET 3 via the resistors R6 and R7.
The current Ids slightly fluctuates, and a change in the ambient temperature of the FET 2 is transmitted through the fluctuation of the current Ids, thereby promoting the positive characteristic of the gate potential of the FET 2. Moreover, if the ambient temperature characteristics of the drain / source currents Ids of FET2 and FET3 are different, the change in ambient temperature cannot be accurately transmitted from FET3 to FET2.
Therefore, the fluctuation of the gate-source voltage Vds of the FET 2 does not correspond to the temperature detected by the diode D, and the fluctuation of the potential due to the ambient temperature appearing at the anode of the diode D cannot be accurately compensated.

However, in the present embodiment having the circuit configuration shown in FIG. 1, since the drain-source voltages Vds applied to the FET2 and the FET3 are almost equal to each other as described above, the anode of the diode D Potential fluctuations are more accurately compensated and the output voltage is more stable against changes in ambient temperature.

In general, since various characteristics of FETs are often measured for each specific drain-source voltage, the drain-source voltages Vds applied to FET2 and FET3 are set equal. Then, simulation of various circuit operations at the time of circuit design can be easily performed, and circuit design becomes easier.

In the above embodiment, the gate-source voltage Vgs of the FET 3 is set to 0.3 to 0.5 [V].
Is -0.3 [V], and the influence of the change in the ambient temperature is small, which is around 0.3 to 0.5 [V]. Therefore, it is necessary to appropriately change the gate-source voltage Vgs of the FET 3 according to the threshold voltage of the FET used. FE also uses the gate width of FET2 to FET3.
Similarly, it is necessary to change appropriately according to the characteristics of T.

FIG. 6 is a circuit diagram showing a second embodiment of the present invention.
The same parts as those in FIG. 1 are denoted by the same reference numerals and their description is omitted.

This figure shows that three diodes D5 to D7 are connected between the resistor R5 and the negative power supply Vss in place of the diode D in the first embodiment, and the gate of the FET2 is connected to the connection point between the resistor R5 and the diode D5. Connected. Other circuit connections and circuit operations are the same as in the first embodiment. The feature of this embodiment is that the voltage obtained at the output terminal OUT can be adjusted by the number of diodes connected. In the case of this embodiment, the order of three diodes with respect to the negative power supply Vss is considered. A voltage higher by the direction voltage is obtained, and a voltage three times higher than that of the first embodiment using one diode is obtained. Note that the number of connected diodes can be arbitrarily selected.

Also in this embodiment, the voltage obtained from the output terminal OUT is always constant without being affected by changes in the ambient temperature due to the action of the source follower constituted by the FET1 to FET3. In addition, it follows the power supply voltage, and is always constant with respect to the power supply voltage.
Furthermore, the drain-source voltage Vds of FET2 and FET3
Are set equal to each other, so that the circuit is more stabilized against a change in ambient temperature, and the circuit design is easier.

FIG. 7 is a circuit diagram showing a third embodiment of the present invention.
The same parts as those in FIG. 6 are denoted by the same reference numerals, and description thereof is omitted.

This figure shows that the FE in the second embodiment shown in FIG.
2 additional source followers composed of T1 to FET3
In this embodiment, three stages of source followers are provided. That is, the source of FET2, which is the output of source follower 1, is connected to the gate of FET2, which is the input of source follower 2, and the source of FET2, which is the output of source follower 2, is connected to the gate of FET2, which is the input of source follower 3. And
The source of FET2, which is the output of source follower 3, is the output terminal
Connected to OUT.

The gate of the FET1 of each stage is connected to each other, and the voltage divided by the resistors R4 and R5 is equally applied.The drain potential of the FET2 of each stage is equal to the drain-source voltage Vds of the FET3 of each stage. They are set to be equal. In addition, the gates of the FETs 3 of each stage are also connected to each other, and the voltages divided by the resistors R6 and R7 are equally applied to these gates, and the influence of the ambient temperature change on the drain-source current Ids of each FET 3 is reduced. It is set as follows.

In such a configuration, each of the three diodes D5 to D7
Is applied with a forward voltage by the negative power supply Vss, and a sum voltage of stable voltages generated between the PN junctions appears at the anode of the diode D5. This sum voltage is applied to the source follower 1 at each stage.
The voltage is transmitted between the gate and the source of the FET2, and the output terminal OUT stabilizes and outputs a voltage higher than the negative power supply Vss by this sum voltage.

Also, when the ambient temperature rises, each of the diodes D5 to D7 depends on the temperature characteristic of each of the diodes D5 to D7.
, The forward voltage drops, and the potential appearing at the anode of the diode D5 drops significantly. This decrease in potential corresponds to three times that in the case of using one diode D in the first embodiment shown in FIG. However, the lowering of the potential due to the change of the ambient temperature is compensated by the three-stage source followers 1 to 3 as follows.

That is, despite the rise in the ambient temperature, a substantially constant drain / source current Ids flows through the FET 3 in each stage, and this current Ids is equally applied to the FET 2 in each stage. The gate-source voltage Vgs of FET2 in each stage is equal to the current Ids
Is hardly changed, and thus decreases under the influence of a change in ambient temperature. Accordingly, the gate potential of the FET2 in each stage rises, and the sum of these potential rises is commensurate with the drop in the forward voltage of three diodes that appears at the anode of the diode D5, and the voltage obtained at the output terminal OUT is It is not affected by changes in the ambient temperature.

Further, a decrease in the voltage between the terminals of the diode D7 due to an increase in the ambient temperature results in a decrease in the resistance divided voltage by the resistors R6 and R7, and is transmitted to the gate of the FET 3 in each stage. However, the gate potential of the FET 3 in each stage is slightly reduced, and the positive effect of the gate potential of the FET 2 in each stage is promoted as described above. Accordingly, the negative characteristic of the anode potential of the diode D5 is compensated for, and the voltage obtained at the output terminal OUT is more stabilized with respect to the ambient temperature change.

In addition, the voltage output from the constant voltage circuit according to the third embodiment also follows the fluctuation of the negative power supply Vss, and always keeps the power supply voltage Vss.
Is constant. This is for each diode D5 ~
This is because the forward voltage generated between the terminals of D7 is not affected by the voltage fluctuation of the negative power supply Vss and does not exist.

Also in this embodiment, the drain and
Since the source-to-source voltage Vds is set to be equal to the drain-to-source voltage Vds of the FET3 in each stage, the characteristics of the drain-source current Ids of the FET2 and FET3 in each stage with respect to the ambient temperature change are approximated. The voltage obtained at the output terminal OUT is more stabilized with respect to a change in the ambient temperature, which facilitates circuit design.

In the above embodiment, three diodes D5 to D7
Is compensated for by using three stages of source followers 1 to 3, but each FET constituting each source follower
By changing the gate structure, the number of constituent steps of the source follower can be changed, and the number of constituent steps of the source follower can be arbitrarily selected. In addition, the respective ratios of the gate widths of the FETs of the source followers 1 to 3 may be different, and the same effects as in the above embodiment can be obtained.

〔The invention's effect〕

As described above, according to the present invention, a resistor and a diode are connected in series between a reference potential and a power supply, and a second FET having a large influence of a temperature change and a third FET having a small influence of a temperature change.
Are connected in series to form a source follower, and the anode potential of the diode is output to this source through the gate of the second FET, whereby the forward voltage of the diode fluctuates due to a change in ambient temperature. Is the third FET
Since the drain-source current of the transistor hardly changes regardless of the ambient temperature change, the drain
The compensation is made by the change in the gate-source voltage of the second FET, which is greatly affected by the ambient temperature change according to the source current. Further, the power supply voltage fluctuation hardly affects the voltage between the terminals of the diode and the operation of the source follower.

Therefore, it is possible to provide a constant voltage circuit which is not affected by a change in the ambient temperature and which constantly generates a constant voltage with respect to the power supply voltage by following the power supply voltage fluctuation. Have.

The power supply voltage is divided by a resistor, and this voltage is divided by the first FET.
To the drain of the second FET via the second FET so as to make the drain-source voltage of the second FET equal to the drain-source voltage of the third FET. The FET has the effect of approximating the drain-source current with respect to the temperature characteristic, and has an effect that the output voltage becomes more stable against a change in the ambient temperature, and also has an effect that the circuit setting becomes easier.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a graph showing a voltage V-current I characteristic of a diode D used in this embodiment, and FIG. FIG. 4 is a graph showing the relationship between the gate-source voltage Vgs and the drain-source current Ids of the MESFET used in the first embodiment, FIG. 4 is a circuit diagram for explaining the effect of the FET 1 in the first embodiment, and FIG. FIG. 6 is a graph showing the relationship between the drain-source voltage Vds and the drain-source current Ids of the MESFET used in the present embodiment, FIG. 6 is a circuit diagram showing a second embodiment of the present invention, and FIG. 8 is a circuit diagram showing a third embodiment of the present invention, and FIGS. 8A and 8B are circuit diagrams showing a conventional configuration. D: Diode, R4, R5 ... Resistance, FET1, FET2, FET3 ...
... First, second, and third Schottky gate field-effect transistors, Vss..., A negative power supply, OUT...

Claims (1)

(57) [Claims] A first resistor having one end connected to a reference potential; a second resistor connected in series to the first resistor; an anode connected to one end of the second resistor; A diode connected to a power supply that outputs a voltage lower than the reference potential; and a diode connected in parallel with the diode, which divides a voltage between an anode and a cathode of the diode to generate a divided voltage. A voltage dividing resistor, a drain connected to the reference potential, and a gate connected to the first potential.
And a first field effect transistor connected to a connection point of the second resistor and a second field effect transistor having a drain connected to a source of the first field effect transistor and a gate connected to an anode of the diode. A third field effect transistor having a drain connected to the source of the second field effect transistor, a source connected to the power supply, and a gate receiving the divided voltage, Applying a voltage between the gate and the source of the third field-effect transistor that reduces the influence of the drain-source current of the third field-effect transistor from a change in ambient temperature; This third
The ratio of the field effect transistor to the gate width is the third
When the drain-source current of the second field-effect transistor is less affected by a change in ambient temperature, the drain-source current of the second field-effect transistor is greatly affected by the change in ambient temperature.
The resistance value of each of the first and second resistors is set so that the drain-source voltage of the second field effect transistor is equal to the third value.
A voltage which is set to be equal to the voltage between the drain and the source of the field effect transistor, and which is constantly stabilized with respect to the power supply by the forward voltage generated between the terminals of the diode.
A constant-voltage generating circuit for outputting to the source of the field-effect transistor.