JP2743779B2 - Photodiode - Google Patents

Photodiode

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Publication number
JP2743779B2
JP2743779B2 JP5183114A JP18311493A JP2743779B2 JP 2743779 B2 JP2743779 B2 JP 2743779B2 JP 5183114 A JP5183114 A JP 5183114A JP 18311493 A JP18311493 A JP 18311493A JP 2743779 B2 JP2743779 B2 JP 2743779B2
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JP
Japan
Prior art keywords
layer
semiconductor film
type
photodiode
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP5183114A
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Japanese (ja)
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JPH0738134A (en
Inventor
一郎 藤枝
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NEC Corp
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NEC Corp
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Publication of JPH0738134A publication Critical patent/JPH0738134A/en
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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明はフォトダイオードに関
し、特に光起電型のフォトダイオードに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photodiode, and more particularly to a photovoltaic photodiode.

【0002】[0002]

【従来の技術】従来のフォトダイオードの第1の例は、
図5に示すように、ガラス基板等の絶縁基板(図示せ
ず)上にp型のアモルファスシリコン(以下a−Siと
記す)膜41と、光電変換用半導体膜となるa−Si膜
40と、n型のa−Si膜42とを順次堆積して積層し
た後、パターニングし、a−Si膜40への電子の注入
を阻止する電極となるp型a−Si膜41と、a−Si
膜40への正孔の注入を阻止する電極となるn型a−S
i膜42とで光電変換用のa−Si膜40を両側から挟
んだ構造の光起電力型フォトダイオードを構成してい
た。
2. Description of the Related Art A first example of a conventional photodiode is as follows.
As shown in FIG. 5, a p-type amorphous silicon (hereinafter abbreviated as a-Si) film 41 and an a-Si film 40 serving as a photoelectric conversion semiconductor film are formed on an insulating substrate (not shown) such as a glass substrate. , An n-type a-Si film 42 are sequentially deposited and laminated, and then patterned to form a p-type a-Si film 41 serving as an electrode for preventing injection of electrons into the a-Si film 40;
N-type aS serving as an electrode for preventing injection of holes into the film 40
A photovoltaic photodiode having a structure in which the a-Si film 40 for photoelectric conversion is sandwiched between the i film 42 and the i film 42 from both sides.

【0003】このフォトダイオードにおいて、p型a−
Si膜41がn型a−Si膜42に対してマイナスにな
るように両者の間に電圧を印加すると、両電極からの電
荷の注入が阻止されるので、自由に移動できる電子と正
孔が存在しない空乏層がa−Si膜40中に形成され
る。十分な電圧が印加されたとき、a−Si膜40全域
が空乏層化される。光43がa−Si膜40に入射する
と、空乏層の中では電界が存在するので、光43により
生成される電子と正孔が、それぞれn型a−Si膜4
2,p型a−Si膜41の方へ移動することができる。
このような電荷の移動がa−Si膜40の中で起こるこ
とにより、p型a−Si膜41あるいはn型a−Si膜
42に接続された外部電子回路に光信号が生成される。
光起電力型フォトダイオードでは、光により生成される
電荷以上の光信号を得ることはできない、即ち、量子効
率が1を越えることはない。
In this photodiode, a p-type a-
When a voltage is applied between the n-type a-Si film 42 and the n-type a-Si film 42 so that the charge is injected between the two electrodes, electrons and holes that can move freely are prevented. A non-existent depletion layer is formed in the a-Si film 40. When a sufficient voltage is applied, the entire region of the a-Si film 40 is depleted. When the light 43 enters the a-Si film 40, an electric field exists in the depletion layer, so that the electrons and holes generated by the light 43 are respectively converted into the n-type a-Si film 4.
2. It can move toward the p-type a-Si film 41.
When such charge transfer occurs in the a-Si film 40, an optical signal is generated in an external electronic circuit connected to the p-type a-Si film 41 or the n-type a-Si film 42.
In a photovoltaic photodiode, an optical signal higher than the charge generated by light cannot be obtained, that is, the quantum efficiency does not exceed 1.

【0004】従来のフォトダイオードの第2の例は、図
6に示すように、絶縁基板(図示せず)上に形成して長
方形にパターニングしたa−Si層10の対向する2辺
のそれぞれにa−Si層10への正孔の注入を阻止する
n型a−Si層12a,12bを形成して光導電型フォ
トダイオードを構成している。
As shown in FIG. 6, a second example of a conventional photodiode is formed on each of two opposing sides of an a-Si layer 10 formed on an insulating substrate (not shown) and patterned in a rectangular shape. The n-type a-Si layers 12a and 12b for preventing injection of holes into the a-Si layer 10 are formed to constitute a photoconductive photodiode.

【0005】ここで、n型a−Si層12a,12b間
に電圧を印加すると、光43が入射しない時は、a−S
i膜10に空乏層が広がって高抵抗な状態になるので、
ダイオードに流れる電流値は小さい。光43が入射する
と、a−Si膜10の導電度が上がり、マイナス側に接
続されたn型a−Si層からの電子の注入が促進されて
大電流がダイオードに流れる。このように、光導電フォ
トダイオードの量子効率は10〜100程度の値を取り
うる。
Here, when a voltage is applied between the n-type a-Si layers 12a and 12b, when light 43 is not incident, a-S
Since the depletion layer spreads in the i-film 10 and becomes a high resistance state,
The current flowing through the diode is small. When the light 43 is incident, the conductivity of the a-Si film 10 increases, the injection of electrons from the n-type a-Si layer connected to the minus side is promoted, and a large current flows through the diode. As described above, the quantum efficiency of the photoconductive photodiode can take a value of about 10 to 100.

【0006】従来のフォトダイオードの第3の例として
は、ジャバニーズ・ジャーナル・オブ・アプライド・フ
ィジィクス(Japanese Journal of
Applied Physics)1993年1月、
第32巻、L39−L41頁に記載されている電子増倍
型フォトダイオードがあり、図7(a)に示すように、
下面にアモルファスSiC層31を形成した真性a−S
i層32の上にp型a−Si層33,真性a−Si層3
4,n型a−Si層35,窒化シリコン膜36,アルミ
ニウム電極37を順次積層した多層構造を有しており、
図7(b)の曲線38に示すような電界強度分布を有し
ている。
[0006] As a third example of a conventional photodiode, Japanese Journal of Applied Physics is available.
Applied Physics, January 1993,
There is an electron multiplying photodiode described in Vol. 32, pp. L39-L41, and as shown in FIG.
Intrinsic aS having an amorphous SiC layer 31 formed on the lower surface
A p-type a-Si layer 33 and an intrinsic a-Si layer 3 on the i-layer 32
It has a multilayer structure in which a 4, n-type a-Si layer 35, a silicon nitride film 36, and an aluminum electrode 37 are sequentially laminated.
It has an electric field intensity distribution as shown by a curve 38 in FIG.

【0007】この電界強度分布は、通常の結晶Siで形
成するリーチスルー型電子増倍型フォトダイオードと同
等であり、真性a−Si層32で吸収された光が生成す
る電子が真性a−Si層34に到達すると、ここに存在
する高電界により電子なだれを引き起こす。従って、電
子増倍型フォトダイオードの量子効率は1を超える。
This electric field intensity distribution is equivalent to that of a reach-through type electron multiplying photodiode formed of ordinary crystalline Si, and electrons generated by light absorbed by the intrinsic a-Si layer 32 are converted to intrinsic a-Si. Upon reaching the layer 34, the high electric field present therein causes an avalanche of electrons. Therefore, the quantum efficiency of the electron multiplying photodiode exceeds 1.

【0008】[0008]

【発明が解決しようとする課題】上述した従来のフォト
ダイオードは、第1の例の多層構造を実現させるには複
数の成膜工程が必要で、製造工程が複雑になるという問
題があり、第2の例の光導電型フォトダイオードは、光
起電力型フォトダイオードに比べて、光強度の時間変化
に対する追従性が劣っているという問題がある。
The above-described conventional photodiode has a problem that a plurality of film forming steps are required to realize the multilayer structure of the first example, and the manufacturing process becomes complicated. The photoconductive photodiode of the second example has a problem that the followability to the time change of the light intensity is inferior to that of the photovoltaic photodiode.

【0009】また、a−Si系の材料で電子増倍型フォ
トダイオードを実現するには、複数材料の多層構造が必
要で、複雑で高度な製造工程を必要とするという問題が
ある。
Further, in order to realize an electron multiplying photodiode using an a-Si-based material, there is a problem that a multilayer structure of a plurality of materials is required, and a complicated and sophisticated manufacturing process is required.

【0010】本発明の目的は、単純な構成で高性能なフ
ォトダイオードを提供することにある。
An object of the present invention is to provide a high-performance photodiode with a simple configuration.

【0011】[0011]

【課題を解決するための手段】本発明の第1のフォトダ
イオードは、絶縁基板上に長方形に形成した光電変換用
の半導体膜と、前記半導体膜の対向する2辺の一方に形
成して前記半導体膜への電子の注入を阻止するマイナス
側電極と、前記対向する2辺の他方に形成して前記半導
体膜への正孔の注入を阻止するプラス側電極と、前記マ
イナス側電極とプラス側電極との中間の前記半導体膜に
前記マイナス側電極およびプラス側電極と平行に形成し
た固定空間電荷を保持する領域とを有する。
According to a first aspect of the present invention, a first photodiode is formed by forming a rectangular semiconductor film for photoelectric conversion on an insulating substrate and forming one of two opposing sides of the semiconductor film. A minus-side electrode for preventing injection of electrons into the semiconductor film; a plus-side electrode formed on the other of the two opposite sides to prevent injection of holes into the semiconductor film; A region holding fixed space charge formed in parallel with the minus side electrode and the plus side electrode in the semiconductor film intermediate with the electrode.

【0012】本発明の第2のフォトダイオードは、絶縁
基板上に長方形に形成した光電変換用の半導体膜と、前
記半導体膜の対向する2辺のそれぞれに形成して前記半
導体膜への電子の注入を阻止するマイナス側電極(又は
前記半導体膜への正孔の注入を阻止するプラス側電極)
と、対向する二つの前記マイナス側電極(又はプラス側
電極)の中間の前記半導体膜に前記マイナス側電極(又
はプラス側電極)と平行に配置した島状のプラス側電極
(又はマイナス側電極)とを有する。
According to a second photodiode of the present invention, a rectangular semiconductor film for photoelectric conversion is formed on an insulating substrate, and electrons are transferred to the semiconductor film by forming the semiconductor film on two opposing sides of the semiconductor film. A negative electrode for preventing injection (or a positive electrode for preventing injection of holes into the semiconductor film)
And an island-shaped plus-side electrode (or minus-side electrode) disposed in parallel with the minus-side electrode (or plus-side electrode) on the semiconductor film between two opposed minus-side electrodes (or plus-side electrodes). And

【0013】[0013]

【実施例】次に、本発明について図面を参照して説明す
る。
Next, the present invention will be described with reference to the drawings.

【0014】図1(a),(b)は本発明の第1の実施
例を示す斜視図およびダイオード内の電界強度分布を示
す図である。
FIGS. 1A and 1B are a perspective view showing a first embodiment of the present invention and a diagram showing an electric field intensity distribution in a diode.

【0015】図1(a)に示すように、ガラス基板等の
絶縁基板(図示せず)の上にCVD法によりa−Si層
10を堆積してパターニングし、長方形の光電変換用の
半導体膜を形成する。次に、フォトリソグラフィ技術と
イオン注入法によりa−Si層10の対向する一方の辺
にホウ素を選択的に導入してa−Si層10への電子の
注入を阻止する電極となるp型a−Si層11を形成
し、対向する他方の辺にリンを選択的に導入してa−S
i層10への正孔の注入を阻止する電極となるn型a−
Si層12を形成する。また同様の工程によりこの対向
する2辺の中間にp型a−Si層11およびn型a−S
i層12に平行に低濃度のp型a−Si層13を帯状に
形成してラテラル型のフォトダイオードを形成する。
As shown in FIG. 1A, an a-Si layer 10 is deposited on an insulating substrate (not shown) such as a glass substrate by a CVD method and patterned to form a rectangular semiconductor film for photoelectric conversion. To form Next, boron is selectively introduced into one of the opposing sides of the a-Si layer 10 by a photolithography technique and an ion implantation method to form a p-type a electrode serving as an electrode for preventing injection of electrons into the a-Si layer 10. -Si layer 11 is formed, and phosphorus is selectively introduced into the other opposite side to form a-S
n-type a- serving as an electrode for preventing injection of holes into i-layer 10
An Si layer 12 is formed. Further, the p-type a-Si layer 11 and the n-type a-S
A low-concentration p-type a-Si layer 13 is formed in a strip shape in parallel with the i-layer 12 to form a lateral photodiode.

【0016】一般に、光電変換膜中に一定量の固定空間
電荷が存在する場合、光電変換膜の全域を空乏層化する
には、光電変換膜の長さの2乗に比例した外部電圧を印
加する必要がある。
Generally, when a fixed amount of fixed space charge exists in a photoelectric conversion film, an external voltage proportional to the square of the length of the photoelectric conversion film is applied to deplete the entire region of the photoelectric conversion film. There is a need to.

【0017】図1(b)に示すように、いま、p型a−
Si層13が形成されていない場合には、フォトダイオ
ード内の電界強度は曲線21のように、p型a−Si層
11とa−Si層10の界面Aで最大となり、n型a−
Si層12に近づくにつれて線形に減衰する。この傾き
は、a−Si層10中の固定空間電荷密度に比例する。
例えば、DC電圧印加時のa−Si層中には約1×10
15cm-3の正の固定空間電荷が存在するので、電極間距
離10μmのダイオードを空乏層化するには少なくとも
75Vの電圧を印加する必要がある。従って、長いラテ
ラル型の光起電力型フォトダイオードを低電圧で空乏層
化するのは困難である。
As shown in FIG. 1B, a p-type a-
When the Si layer 13 is not formed, the electric field strength in the photodiode becomes maximum at the interface A between the p-type a-Si layer 11 and the a-Si layer 10 as shown by a curve 21, and the n-type a-
It decreases linearly as it approaches the Si layer 12. This inclination is proportional to the fixed space charge density in the a-Si layer 10.
For example, when a DC voltage is applied, about 1 × 10
Since a fixed fixed space charge of 15 cm -3 exists, it is necessary to apply a voltage of at least 75 V to deplete a diode having a distance between electrodes of 10 μm. Therefore, it is difficult to deplete a long lateral photovoltaic photodiode at a low voltage.

【0018】そこで、この実施例のように、p型a−S
i層13を形成すると、p型a−Si層13中には、マ
イナスの固定空間電荷が存在するので、実現される電界
分布は、曲線22のようにp型a−Si層13中で電界
の位置微分が反転し、印加する電圧値はこれらの電界強
度分布を積分して得られる。曲線21と曲線22とで
は、それぞれとx軸とで囲まれる面積が等しいので、同
じ電圧が印加されていることがわかる。即ち、この実施
例のn型a−Si層12付近の低電界領域が少ない。
Therefore, as in this embodiment, the p-type a-S
When the i-layer 13 is formed, since a negative fixed space charge exists in the p-type a-Si layer 13, the realized electric field distribution is as shown in a curve 22 in the p-type a-Si layer 13. Is inverted, and the applied voltage value is obtained by integrating these electric field intensity distributions. Since the areas enclosed by the curves 21 and 22 and the x axis are equal, it can be seen that the same voltage is applied. That is, the low electric field region near the n-type a-Si layer 12 of this embodiment is small.

【0019】図2(a),(b)は本発明の第2の実施
例を示す斜視図およびダイオード内の電界強度分布を示
す図である。
FIGS. 2A and 2B are a perspective view showing a second embodiment of the present invention and a view showing an electric field intensity distribution in a diode.

【0020】図2(a)に示すように、第1の実施例と
同様の工程で形成した長方形のa−Si層10の対向す
る2辺の双方にp型a−Si層11a,11bを形成
し、この中間のa−Si層10に島状のn型a−Si層
14をp型a−Si層11a,11bに平行に配置して
形成する。
As shown in FIG. 2A, p-type a-Si layers 11a and 11b are provided on both sides of a rectangular a-Si layer 10 formed in the same process as in the first embodiment. The island-shaped n-type a-Si layer 14 is formed on the intermediate a-Si layer 10 by being arranged in parallel with the p-type a-Si layers 11a and 11b.

【0021】ここで、島状に形成したn型a−Si層1
4から発した電気力線は、帯状に形成したp型a−Si
層11に到達する。両電極の面積が異なるので、面積の
小さい島状の電極の近傍で、電気力線の密度、即ち、電
界が強くなる。これが幾何学的な電界制御の効果であ
る。実際には、上述したa−Si層10中の固定空間電
荷の効果によりp型a−Si層11近傍の電界が強めら
れる。図2(a)の構成では、幾何学的な電界制御の効
果とa−Si層10内の固定空間電荷の効果が相殺す
る。実現される電界強度分布は、図2(b)の曲線23
に示すように、島状のn型a−Si層14近傍で電界強
度が増加して、a−Si層10内の固定空間電荷による
電界の減衰を逆転できることがわかる。
Here, the n-type a-Si layer 1 formed in an island shape
4 are p-type a-Si formed in a belt shape.
The layer 11 is reached. Since the two electrodes have different areas, the density of the lines of electric force, that is, the electric field becomes strong near the island-shaped electrode having a small area. This is the effect of the geometric electric field control. In practice, the electric field near the p-type a-Si layer 11 is strengthened by the effect of the fixed space charge in the a-Si layer 10 described above. In the configuration of FIG. 2A, the effect of the geometric electric field control and the effect of the fixed space charge in the a-Si layer 10 cancel each other. The realized electric field intensity distribution is represented by a curve 23 in FIG.
As shown in FIG. 5, it can be seen that the electric field intensity increases near the island-shaped n-type a-Si layer 14 and the attenuation of the electric field due to fixed space charges in the a-Si layer 10 can be reversed.

【0022】図3(a),(b)は本発明の第3の実施
例を示す斜視図およびダイオード内の電界強度分布を示
す図である。
FIGS. 3A and 3B are a perspective view showing a third embodiment of the present invention and a diagram showing an electric field intensity distribution in a diode.

【0023】図3(a)に示すように、第1の実施例と
同様の工程で形成した長方形のa−Si層10の対向す
る一方の辺にp型a−Si層11を形成し、対向する他
方の辺にn型a−Si層12を形成し、p型a−Si層
11の近傍のa−Si層10内にp型a−Si層11と
平行に帯状の低濃度のn型a−Si層15を形成してお
り、図3(b)に示すように、ダイオード内の電界強度
分布は曲線24のように、p型a−Si層11の近傍で
高い電界を得ることができる。
As shown in FIG. 3A, a p-type a-Si layer 11 is formed on one opposite side of a rectangular a-Si layer 10 formed in the same process as in the first embodiment. An n-type a-Si layer 12 is formed on the other opposite side, and a strip-shaped low-concentration n is formed in the a-Si layer 10 near the p-type a-Si layer 11 in parallel with the p-type a-Si layer 11. Since the type a-Si layer 15 is formed, as shown in FIG. 3B, the electric field intensity distribution in the diode is such that a high electric field is obtained near the p-type a-Si layer 11 as shown by a curve 24. Can be.

【0024】図4(a),(b)は本発明の第4の実施
例を示す斜視図およびダイオード内の電界強度分布を示
す図である。
FIGS. 4A and 4B are a perspective view showing a fourth embodiment of the present invention and a view showing an electric field intensity distribution in a diode.

【0025】図4(a)に示すように、第1の実施例と
同様の工程で形成した長方形のa−Si層10の対向す
る2辺の双方に帯状のn型a−Si層12a,12bを
それぞれ形成し、この中間のa−Si層10内に島状の
p型a−Si層16をn型a−Si層12a,12bに
平行に配置して形成する。
As shown in FIG. 4A, strip-shaped n-type a-Si layers 12a, 12a are formed on two opposing sides of a rectangular a-Si layer 10 formed in the same process as in the first embodiment. 12b are formed, and an island-shaped p-type a-Si layer 16 is formed in the intermediate a-Si layer 10 by being arranged in parallel with the n-type a-Si layers 12a and 12b.

【0026】図4(b)の曲線25に示すように、ダイ
オード内の電界強度分布は、電界に対する固定空間電荷
の効果と幾何学的な効果とが強めあい、島状のp型a−
Si層15の近傍で高い電界が得られる。
As shown by the curve 25 in FIG. 4B, the electric field strength distribution in the diode is such that the effect of the fixed space charge on the electric field and the geometrical effect reinforce each other, and the island-shaped p-type a-
A high electric field is obtained near the Si layer 15.

【0027】[0027]

【発明の効果】以上説明したように本発明は、光電変換
用半導体膜中に帯状に形成した低濃度のp型a−Si層
により、半導体膜中の固定空間電荷の影響を相殺するこ
とができ、また、島状に形成したp型a−Si層により
幾何学的に電界を強化して、半導体膜中の固定空間電荷
の影響を相殺することができ、低電圧で空乏層化が可能
になるという効果を有する。
As described above, according to the present invention, the influence of fixed space charge in the semiconductor film can be offset by the low-concentration p-type a-Si layer formed in the semiconductor film for photoelectric conversion in a strip shape. In addition, the electric field can be geometrically enhanced by the p-type a-Si layer formed in the shape of an island, the effect of fixed space charge in the semiconductor film can be offset, and the depletion layer can be formed at low voltage. Has the effect of becoming

【0028】また、同様に帯状に形成した低濃度のn型
a−Si層中の固定空間電荷の効果や島状電極による幾
何学的効果により、半導体膜中の固定空間電荷の影響を
強める構成にすることにより、構造が簡単な電子増倍型
フォトダイオードが実現できるという効果を有する。
A structure in which the effect of the fixed space charge in the semiconductor film is enhanced by the effect of the fixed space charge in the low-concentration n-type a-Si layer similarly formed in a belt shape and the geometric effect by the island-shaped electrode. Has an effect that an electron multiplying photodiode having a simple structure can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例を示す斜視図およびダイ
オード内の電界強度分布を示す図。
FIG. 1 is a perspective view showing a first embodiment of the present invention and a diagram showing an electric field intensity distribution in a diode.

【図2】本発明の第2の実施例を示す斜視図およびダイ
オード内の電界強度分布を示す図。
FIG. 2 is a perspective view showing a second embodiment of the present invention and a diagram showing an electric field intensity distribution in a diode.

【図3】本発明の第3の実施例を示す斜視図およびダイ
オード内の電界強度分布を示す図。
FIG. 3 is a perspective view showing a third embodiment of the present invention and a diagram showing an electric field intensity distribution in a diode.

【図4】本発明の第4の実施例を示す斜視図およびダイ
オード内の電界強度分布を示す図。
FIG. 4 is a perspective view showing a fourth embodiment of the present invention and a view showing an electric field intensity distribution in a diode.

【図5】従来のフォトダイオードの第1の例を示す斜視
図。
FIG. 5 is a perspective view showing a first example of a conventional photodiode.

【図6】従来のフォトダイオードの第2の例を示す斜視
図。
FIG. 6 is a perspective view showing a second example of a conventional photodiode.

【図7】従来のフォトダイオードの第3の例を示す斜視
図およびダイオード内の電界強度分布を示す図。
FIG. 7 is a perspective view showing a third example of a conventional photodiode and a diagram showing an electric field intensity distribution in the diode.

【符号の説明】[Explanation of symbols]

10,40 a−Si膜 11,11a,11b,13,15,16,33,41
p型a−Si層 12,12a,12b,14,35,42 n型a−
Si層 31 アモルファスSiC層 32,34 真性a−Si層 36 窒化シリコン膜 37 アルミニウム電極 43 光
10,40 a-Si film 11,11a, 11b, 13,15,16,33,41
p-type a-Si layer 12, 12a, 12b, 14, 35, 42 n-type a-Si layer
Si layer 31 Amorphous SiC layer 32, 34 Intrinsic a-Si layer 36 Silicon nitride film 37 Aluminum electrode 43 Light

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】絶縁基板上に長方形に形成した光電変換用
の半導体膜と、前記半導体膜の対向する2辺の一方に形
成して前記半導体膜への電子の注入を阻止するマイナス
側電極と、前記対向する2辺の他方に形成して前記半導
体膜への正孔の注入を阻止するプラス側電極とを有し
前記マイナス側電極とプラス側電極との中間の前記半導
体膜に前記マイナス側電極及びプラス側電極と同一平面
上に形成した固定空間電荷を保持する領域とを有し、ラ
テラル型であることを特徴とするフォトダイオード。
A semiconductor film for photoelectric conversion formed in a rectangular shape on an insulating substrate; a negative electrode formed on one of two opposing sides of the semiconductor film to prevent injection of electrons into the semiconductor film; , formed on the other two sides the opposed and a positive electrode that blocks injection of holes into the semiconductor film,
The same plane as the minus side electrode and the plus side electrode is provided on the semiconductor film between the minus side electrode and the plus side electrode.
And a region for holding the fixing space charges formed in the upper, La
Photodiode characterized by being of the teleral type .
【請求項2】絶縁基板上に長方形に形成した光電変換用
の半導体膜と、前記半導体膜の対向する2辺のそれぞれ
に形成して前記半導体膜への電子の注入を阻止するマイ
ナス側電極(又は前記半導体膜への正孔の注入を阻止す
るプラス側電極)と、対向する二つの前記マイナス側電
極(又はプラス側電極)の中間の前記半導体膜に前記
マイナス側電極(又はプラス側電極)と同一の平面上に
配置した島状のプラス側電極(又はマイナス側電極)と
有し、ラテラル型であることを特徴とするフォトダイ
オード。
2. A semiconductor film for photoelectric conversion formed in a rectangular shape on an insulating substrate, and a negative electrode (2) formed on each of two opposite sides of the semiconductor film to prevent injection of electrons into the semiconductor film. Alternatively, the minus-side electrode (or plus-side electrode) may be provided on the semiconductor film between the two opposed minus-side electrodes (or plus-side electrodes) that prevent injection of holes into the semiconductor film. A) a lateral-type photodiode having an island-like positive electrode (or negative electrode) disposed on the same plane as in (1).
JP5183114A 1993-07-26 1993-07-26 Photodiode Expired - Lifetime JP2743779B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5183114A JP2743779B2 (en) 1993-07-26 1993-07-26 Photodiode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5183114A JP2743779B2 (en) 1993-07-26 1993-07-26 Photodiode

Publications (2)

Publication Number Publication Date
JPH0738134A JPH0738134A (en) 1995-02-07
JP2743779B2 true JP2743779B2 (en) 1998-04-22

Family

ID=16130028

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5183114A Expired - Lifetime JP2743779B2 (en) 1993-07-26 1993-07-26 Photodiode

Country Status (1)

Country Link
JP (1) JP2743779B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6747638B2 (en) * 2000-01-31 2004-06-08 Semiconductor Energy Laboratory Co., Ltd. Adhesion type area sensor and display device having adhesion type area sensor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6161477A (en) * 1984-09-03 1986-03-29 Matsushita Electric Ind Co Ltd Amorphous high speed responding diode
JPS63272573A (en) * 1987-04-30 1988-11-10 Nec Corp Printer

Also Published As

Publication number Publication date
JPH0738134A (en) 1995-02-07

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