JP2742139B2 - DCME equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DCME (Digital Circuit Multiplication Equipment) device used to improve the efficiency of use of a PCM telephone line.

[0002]

2. Description of the Related Art In general, in a communication line in which a telephone call is made, the ratio of the time during which voice energy is present to the time in which the telephone line is occupied by the telephone call (hereinafter referred to as "voice ratio") is 40% or less. . For this reason, if only the section where the voice energy exists is effectively transmitted, information can be transmitted through a smaller number of trunk lines than the number of telephone communication lines, and the utilization efficiency of the trunk lines can be increased. Generally, this system is called a DSI system, and the DSI system is put into practical use as a DSI device for satellite links and the like. In recent years, this DSI system and a variable length bit rate ADPCM (Adaptive Diff) in which the encoding bit rate can be adaptively changed.
eriental Pulse Code Modul
) are being developed to perform more efficient line multiplexing and to effectively expand the transmission capacity. Further, this DCME device is characterized by dynamically allocating 64 Kbit / s data.

Here, an example of the conventional DSI system will be described with reference to FIG. The illustrated DIS device has a transmission-side input terminal 11 and a transmission-side output terminal 12. PCM signals corresponding to the number of communication lines are input to the transmission-side input terminal 11. This PCM signal is input to a line state detector 13 for detecting the presence or absence of voice energy. Here, when voice generation is detected, the allocation request generation circuit 14 generates a line connection request. This line connection request may occur on a number of telephone lines at the same time. However, there is a limit to the number of lines that can be processed by the allocation control circuit 15, that is, this line connection request is temporarily stored in the allocation request temporary storage unit 16 due to the limitation of the processing time. The allocation request temporary storage unit 16 stores the request generation channel numbers and the order of occurrence of each request generation channel number as a line connection request, and the oldest stored channel among the stored channel numbers has the highest priority and the highest priority. Assignment control circuit 15 as the request generation channel number
Is output to The assignment control circuit 15 determines the speech channel assignment according to the request generation channel number, and sends the assignment information to the high-speed switch circuit 17 and the assignment information encoder 18.
The high-speed switch circuit 17 allocates the input communication line to the trunk line according to the allocation information. As a result, the assignment information encoder 18
The PCM signal together with the assignment information code which is the output of
The signal is sent from the signal output terminal 12 to the transmission line. The allocation request temporary storage unit 16 stores, for example, a FIFO (First I
n First Out) memory.

[0004]

By the way, as described above, in the DIS device, the allocation request temporary storage section is provided with a storage circuit for storing only the request generation channel number and the generation time order, and has a variable length ADPCM. In the case of a DCME device that needs to perform dynamic control such as allocation of encoding and allocation of 64 Kbit / s data, the types of requests are diversified, and it is necessary to provide a storage circuit corresponding to the number of types of requests. Occurs. As a result, the hardware scale becomes very large. Further, in the assignment control circuit, it is necessary to determine which type of required storage circuit output from the plurality of storage circuits is prioritized, so that there is a problem that processing time is adversely affected. An object of the present invention is to provide a DCME device (allocation request temporary storage system) capable of performing a judgment process at high speed without increasing the hardware scale.

[0005]

According to the present invention, an input side and an output side are provided, and a call signal state of these lines is detected for each of a plurality of PCM telephone lines connected to the input side. In the DCME apparatus for allocating the telephone line to the trunk line connected to the output side based on the
Generating means for generating an allocation request based on the detected communication signal state; output means for selecting and outputting these allocation requests in descending order of priority; determining an encoding bit rate based on the selected allocation request; DC having allocation control means for performing allocation to a line
An ME device is obtained. The assignment request includes an assignment request generation channel number, an assignment occurrence time order, and a request type of the assignment request, and the output means determines a priority based on the assignment time order and the request type, and The number and the request type are output as a selective assignment request. In this case, the output unit refers to the first storage unit that stores the allocation request generation channel number and the allocation generation time order, the second storage unit that stores the request type, and the first and second storage units. Priority request selection means for selecting a request generation channel having a high priority and a request type. In addition to the allocation request, the generation unit compares the previous request type with the current request type at predetermined unit time intervals and generates first flag information indicating whether or not the types are equal. In such a case, the DCME device is newly provided with a unit for controlling writing to the first storage unit based on the first flag information. The first storage means has first and second FIFO memories, the first flag information is temporarily stored in the second storage means, and the request generation channel number is temporarily stored in the second FIFO memory. You. The control means stores the request generation channel number from the second FIFO memory into the first FIFO memory based on the first flag information.
Performs write control to transfer to memory. When the generating means further generates the second flag information for preventing double registration for each unit time, the DCME further generates a request to the first FIFO memory when the second flag information is on. A means for preventing registration of a channel number is provided.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments. With reference to FIG. 1, the illustrated DCME apparatus has an input terminal 11 and an output terminal 12, and PCM signals are input to the input terminal 11 from the telephone line in a time division manner in the order of channel numbers. The PCM signal is detected by the line state detector 13 as to which type of signal (for example, voice or FAX data in a voice band), the presence or absence of energy, and the like. Then, this detection result is input to the storage control unit 20. Further, the storage control unit 20 is connected to the input terminal 19 via the input terminal 19 to generate 64 kbit / s.
A line connection request / release request signal is provided. This 64k
The bit / s line connection request / release request signal is generated by an exchange (not shown), and is given in a time division manner in the order of channel numbers via a signaling processing unit (common unit different from the DSI unit). These detection results and connection request / release request signals are synchronously given as state information, and whether or not an allocation request is generated in a predetermined unit processing time is determined by the input communication line at that time (input time of the detection result or the like). It is determined by the connection status between the network and the transmission line side trunk line, and, if connected, by the bit rate of the connected trunk line. If it is already connected, no allocation request is made even if there is voice energy. The above connection status is IC / SC
It is provided from the type memory 21 to the control storage unit 20. The input signals to the storage section 20 are all input synchronously in a time-division manner for all channels in a predetermined unit processing time, for example, in the order of an input communication channel number (hereinafter referred to as IC ^# ).

Here, referring also to FIG.
0 has an allocation request generation circuit 22. The allocation request generation circuit 22 determines the ADPCM encoding bit rate to be applied to this speech line based on the above-mentioned input signal and the 64 Kb
It determines the type of allocation request such as an it / s line connection request / release request and generates an allocation request (consisting of an allocation request type and a request temporary storage control signal). This allocation request output is IC
^♯ allocation request temporary storage circuit in time division for each (Qmem) 23
Is output to The allocation request is stored as an address IC ^♯ the request type temporary storage circuit 23 for all IC ^♯. Further, for a new allocation request, the IC ^# is stored in the request generation channel number and generation time order temporary storage circuit 24 by a request temporary storage control signal. This I
The C ^$ and IC ^$ addresses are generated from the counter 25 in synchronization with the output data of the allocation request generation circuit 21.

Referring now to FIGS. 2 and 3, a request generation channel number and a generation time order temporary storage circuit 24 are shown.
Is, for example, two FIFO memories 24a and 24b and a memory read / write control unit (MEMCONT) 2
4c. When one unit processing time is divided into three frames of the allocation request generation and storage frame (I), the highest priority request selection frame (II), and the allocation control processing frame (III), first, the frame (I) is used for the FIFO memory 24b. Is M
Cleared by EMCONT 24c. Next, in the request generation frame (I), the selector 26 sets the selector control circuit (S
ELCONT) 27 and a second input 26
b is selectively output. That is, the output of the internal counter 25 is selected and supplied to the temporary storage circuit 24. MEMCONT2
4c for all IC ^♯, written into the FIFO memory 24a based on the required temporary storage control signal the IC ^♯ only for IC new allocation request occurs ^♯. At the same time, the FIFO memory 24 the IC ^♯ MEMCONT24c is that is already temporarily stored from the FIFO memory 24a
b and a new FI within this unit processing time.
IC ^♯ also all FIFO that have been added to the FO memory 24a
Transfer to the memory 24b.

Next, in the highest priority request selection frame (II), the selector 26 controls the first
Is selected. The MEMCONT 24c reads the IC ^# that has been moved to the memory 24b, sends this read IC ^# to the highest priority request latch circuit 28,
Further, the read IC ^# is inputted as an address to the request type temporary storage circuit 23 via the selector 26, and the request type (QUE ^# ) corresponding to the read IC ^# is read. Then, this request type is set to the highest priority request latch circuit 28
Enter In the latch circuit 28, first, the request type and I
Latch C ^♯ . Next, the I output from the memory 24b
C ^# and the corresponding request type are read from the storage circuit 23, and if the priority is lower than the request type of the ^immediately preceding IC ^# which is already latched, the latch is not performed. On the other hand, when it is high, the data of the latch circuit 28 is updated. If the priority of the reading IC ^♯ is low, since the turn to the next unit processing time, MEMCONT24c is kept back the read IC ^♯ the FIFO memory 24a. This operation IC ^♯ are transferred to the FIFO memory 24b is performed until empty. Highest priority request selection frame
In (II), based on a plurality of input data, the highest-priority request latch circuit 28 determines the highest-priority allocation request, that is, the highest-priority request type and the earliest requested allocation request. Select this latched request

The allocation control circuit 29 determines the allocation between the input speech line and the trunk line according to the type of request, outputs the ADPCM coded control information to the ADPCM coder 30, and transmits the allocation control information to the high-speed switch circuit 17 and the allocation circuit. Output to the information encoder 18. Further, the assignment control circuit 29 stores the connection status between the input communication line (IC) and the transmission line side trunk line (SC) and the IC /
The SC type memory 21 is updated. PC of input telephone line
The M signal is an ADPCM encoder 3 which has received the encoding control information.
0 is ADPCM coded, and the coded signal is allocated to the transmission line side trunk line by the high-speed switch circuit 17 which has received the allocation control information, and is transmitted from the output terminal 12 to the transmission line together with the allocation information code from the allocation information encoder 18. Sent out.

In the above embodiment, after the assignment control circuit 29 processes and assigns the highest priority request, it is necessary to remove the request from the request temporary storage circuit 23. Further, when an allocation request is simultaneously generated in a large number of communication lines and the allocation processing capacity of the allocation circuit is exceeded, a large number of allocation requests are stored in the request temporary storage circuit. In such a state, for example, if the state of the input communication line changes to a state where there is no voice energy, there is no need to allocate a relay line to this communication line. That is,
It is necessary to extract the assignment request for the telephone line from the request temporary storage circuit. Further, when the type of the allocation request changes, it is necessary to extract the allocation request temporarily stored in the allocation request temporary circuit and newly refill the allocation request. In such a case, it must be removed unnecessary IC ^♯ in a state where the request temporary storage circuit holds the request generation time sequential order. If you try to process as described above in software, firstly, by searching the IC ^♯ generation time rank to be removed, except for the unnecessary IC ^♯, the exiled IC ^♯
Shall its position is one by one shift for a later IC ^♯. In other words, it must be performed IC ^♯ min to remove such treatment. Therefore, the processing time becomes longer. As a result, there is a possibility that a series of processes from allocation request generation, allocation request temporary storage processing, and allocation control processing result allocation determination cannot be executed in real time in one unit processing time.

Next, a second embodiment of the present invention will be described with reference to FIGS. 4 is the same as that of FIG. 1 up to the signal input to the allocation request generation circuit 20. In this embodiment, the allocation request generation circuit 22 stores the type of allocation request and the previous unit processing time. A control flag (V-FL) indicating whether the request type is equal to the request type of the current output.
AG). The V-FLAG is stored together with the request type in the request type temporary storage circuit 23 by the IC ^@ address as described above. This storage operation is performed for all input communication lines in the allocation request type storage frame (I). That is, in the frame (I), the selector 26 outputs the second input 26
b is selectively output under the control of the SELCONT 27. Moreover, in this same frame (I), all the previous unit processing time previously MEMCONT24c the request channel number stored in the FIFO memory 24a as described above (IC ^♯), FIFO memories 24b
Transfer to

Next, in the FIFO memory rearrangement frame (II), as described above, the selector 26 sets the first input 26a.
Select MEMCONT24c is FIFO memory 2
4b while reading out the IC ^# transferred to the
C ^# is input as an address to the request type temporary storage circuit 23 through the selector 26, and the control FLAG is read out.
Determines whether transfer the IC ^♯ to the FIFO memory 24a in response to the AG. If the current request type is the same as the previous request and there is a request, the FIFO memory 24a stores
C ^♯ is moved, and if it is different,
Pull out the unnecessary IC ^♯ from O memory 24b. Perform this control for all IC ^♯ in the FIFO memory 24b.
This operation only IC ^♯ should withdrawn while holding request generation time sequential order can Nukiru. Next, in the new request generation channel number storage frame (III), the selector 26 selects and outputs the second input 26b. As a result, IC ^♯ the internal counter output is the address input to the request type temporary storage circuit 23 for all IC ^♯, request type and control FLAG is read, FIFO memories this time newly generated request channel number 24a is additionally written. In other words, the type that has been changed and that is the type that should be stored as requested is written. At the same time, the MEMCONT 24c stores the I memory in the FIFO memory 24a.
Including those of the C ^♯ have been added this time, FIF all IC ^♯
Transfer to the O memory 24b.

Finally, in the highest priority request selection frame (IV),
The selector 26 selects the first input 26a. As a result, the MEMCONT 24c uses the FIFO memory 24b.
While reading out the IC ^# , the IC ^# is output to the highest priority request latch circuit 28, and the read IC ^# is input as an address to the request type temporary storage circuit 23 to read the request type corresponding to the IC ^# . Then, this request type is input to the highest priority request latch circuit 28. This reading IC
^If the priority of ^$ is low, the IC ^$ is returned to the memory 24a in order to pass to the next unit processing time. This operation is performed until the IC ^# moved to the memory 24b becomes empty. In the highest priority request selection frame (IV), the highest priority request latch circuit 2
At step 8, the highest priority allocation request, that is, the request type that has the highest priority and is requested from the earliest, is selected and the type and channel number of the request are output to the allocation control circuit 29. . Subsequent allocation control processing frame
The assignment operation in (V) is the same as in the first embodiment, and a description thereof will be omitted.

A third embodiment of the DCME device according to the present invention will be described with reference to FIG. 6 in addition to FIG. In this embodiment, the storage control unit 20 further includes a selector 31. First, the allocation request generation frame
In (I), the selector 26 selects the second input 26b. As a result, the processing of all the IC ^♯ in accordance with the output of the internal counter 25 is started. The output of the internal counter 25 is input as an address to the request type storage circuit 23, and the request type stored in the previous unit time is read. This request type is input to the allocation request generation circuit 22. The allocation request generation circuit 22 updates and outputs a new request type based on the request type and the other input signal described above, and determines whether the request type stored in the previous unit processing time is equal to the current request type. Is output. At this time, the allocation request generation circuit 22 further performs QF
LAG = "0" is output. Selector control circuit (SE
(LCONT) 27, the selector 31 selects the second input 31b. As a result, the Q-FLAG is stored in the request type temporary storage circuit 23 together with the request type and the V-FLAG using IC ^# as an address. The above-described processing is performed for all input speech lines in the allocation request type storage frame (I). Further, in this allocation request type storage frame (I), all the request channel numbers (ICs) stored in the FIFO memory 24a before the immediately preceding unit processing time.
^♯) is transferred to the FIFO memory 24b under the control of MEMCONT24c.

In the FIFO memory reduction frame (II), the selector 26 controls the first input 2 under the control of the SELCONT 27.
6a is selectively output. F by MEMCONT24c
The IC ^# transferred to the IFO memory 24b is read,
These IC ^♯ are address inputs to the request type temporary storage circuit 23. Then, the request type, the control FLAG, and the Q-FLAG are read from the request type temporary storage circuit 23. The MEMCONT 24c determines a corresponding IC based on the read request type, the control FLAG, and the Q-FLAG.
^Is transferred to the FIFO memory 24a. In other words, if the current request type is the same as the previous request type and should be stored and Q-FLAG = "0", the MEMCONT 24c writes the corresponding IC ^# into the FIFO memory 24a. In other cases, FIFO
Not written into the FIFO memory 24a by simply reading the IC ^♯ from the memory 24b, withdrawn unnecessary IC ^♯. At this time, under the control of the SELCONT 27, the selector 31 selects and outputs the first input 31a. As a result, the FIF
The request type (QUE ^# ) and V-FLAG corresponding to only IC ^# written in the O memory 24a are written in the request type temporary storage circuit 23, and Q-FLAG is Q-
FLAG = "1" is written to the request type temporary storage circuit 23. Then, the write operation is performed for all the IC ^♯ in the FIFO memory 24b.

By such a write operation, it is possible to extract only the unnecessary IC ^# while holding the request generation time sequence. In addition, for the IC ^# temporarily transferred to the FIFO memory 24a by the Q-FLAG, the FI ^#
It is not written again in the FO memory organizing frame (II). In other words, double registration in the FIFO memory 24a can be avoided.

Next, in the new request generation channel number storage frame (III), the selector 26 selects and outputs the second input 26b under the control of the SELCONT 27. as a result,
IC ^# from internal counter 25 is input to request type temporary storage circuit 23 as an address. As a result, the request type and the control FLAG are read from the request type temporary storage circuit 23, and the MEMCONT 24c is the request type to be stored and is not registered in the FIFO memory 24a.
^♯ is written into the FIFO memory 24a. At the same time, M
FIFO memory 24b everything EMCONT24c also including an additional portion of the IC ^♯ stored in the FIFO memory 24a
Transfer to In the highest priority request selection frame (IV), the selector 26 controls the first input 26a under the control of the SELCONT 27.
Is selected and output. Thereby, the FIFO memory 24b
IC ^♯ is read from the read IC ^♯ is output to the highest priority request selection circuit 28. Further, the read IC ^# is addressed to the request type temporary storage circuit 23, and the request type corresponding to the read IC ^# is read and input to the highest priority request selection circuit 28 at the same time. When low priority for IC ^♯, it is necessary to be processed in the next unit processing time, this IC ^♯ is FI
The data is returned to the FO memory 24a. Such an operation is
The process is performed until the O memory 24b becomes empty.

According to the data input in the highest priority request selection frame (IV), the highest priority request selection latch circuit 28 causes the highest priority allocation request, that is, the allocation request of the highest priority request type and the earliest requested. Are selected and latched, and the request type and channel number are output to the assignment control circuit 29. Subsequent allocation control processing frame V)
Are the same as those in the first embodiment, and a description thereof will be omitted.

[0020]

As described above, the DCM according to the present invention is used.
In the E device, even if the types of requests are diversified, it is not necessary to have the same number of storage circuits, and the amount of hardware can be reduced.
The processing load on the assignment control circuit can be reduced by the highest priority request selection circuit, and the processing time is not adversely affected. Further, in the DCME device according to the present invention, it is possible to extract the unnecessary allocation request channel number from the temporary storage circuit while maintaining the order of the allocation request generation time by using only the hardware. As a result, the processing time is greatly reduced. Significant reduction can be achieved. In addition, the processing time load on the assignment control circuit can be reduced, and adverse effects are extremely small. Further, double registration of an allocation request to the temporary storage unit due to malfunction due to noise or the like and double registration due to memory uncertainty at power-on can be prevented, and time and effort for memory initialization can be saved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a transmitting side of an embodiment of a DCME device according to the present invention.

FIG. 2 is a block diagram showing a first embodiment of a storage control unit in detail.

FIG. 3 is a diagram illustrating an example of a processing procedure of a storage control unit on a time axis.

FIG. 4 is a block diagram showing a second embodiment of the storage controller in detail.

FIG. 5 is a diagram showing another example of the processing procedure of the storage control unit on a time axis.

FIG. 6 is a block diagram showing a third embodiment of the storage control unit in detail;

FIG. 7 shows a DI using a conventional allocation request temporary storage method.
FIG. 3 is a block diagram illustrating a transmitting side of the S device.

[Explanation of symbols]

Reference Signs List 11 PCM signal input terminal on transmission side 12 Output terminal on transmission side 13 Line state detector 17 High-speed switch circuit 18 Allocation information encoder 19 64 kbit / s line connection request / release request signal input terminal 20 Storage control unit 21 Channel type storage circuit 22 Assignment request generation circuit 23 Request type temporary storage circuit 24 Request generation channel number and its generation time order temporary storage unit 25 Internal counter 28 Highest priority request latch circuit 29 Allocation control circuit 30 ADPCM encoder

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-286029 (JP, A) JP-A-63-286030 (JP, A) JP-A-61-56533 (JP, A)

Claims (4)

(57) [Claims] An input side and an output side are provided, and a call signal state of each of a plurality of PCM telephone lines connected to the input side is detected, and the telephone line is connected based on the detected call signal state. DC assigned to the trunk line connected to the output side
In the ME device, generating means for generating an allocation request based on the detected call signal state, output means for selecting and outputting the allocation requests in descending order of priority, based on the selected allocation request, Assignment control means for determining an encoding bit rate predetermined according to the type of request, transmitting an encoding control signal to an encoding unit for encoding the speech signal, and allocating the encoded speech signal to the trunk line The generation means includes a communication signal state signal, a 64k line connection request / release signal, and a connection state signal to a relay line synchronized with the channel number in the unit processing time in a time division manner for all channels. The allocation request is input and output in the order of channel number, and the allocation request is repeatedly generated for all channels in the unit processing time unit. And the allocation request to the output device is inputted in a time division per all channels, wherein the output means is to identify the channel number allocation request is generated by the time slot position of the allocation request,
A first storage unit configured to store the specified channel number; a second storage unit configured to store the allocation request type at an address of the channel number where the allocation request has occurred; After the assignment request generation and temporary storage are performed for all input channels, the assignment request generation channel number is read from the first storage unit with reference to the first and second storage units, and the assignment request generation is performed. A high priority request selecting means for inputting a channel number to the second storage means, reading a corresponding request type, reading a request generation channel number and a request type having the highest priority at the unit processing time; A DCME device characterized by the above-mentioned. 2. The DCME apparatus according to claim 1, wherein the generation unit compares a previous request type with a current request type for each unit processing time in addition to the assignment request. Generating first flag information indicating whether or not are equal to each other. The output means stores the first flag information together with a request type in the second storage means using a channel number as an address for all channels. Extracting the channel number data from the first storage unit when the request types are different while retaining the allocation request generation time order in the first storage unit in the previous unit processing time based on the first flag information. And a means for adding the channel number to the first storage means after the need to request the request type as a new allocation request. A DCME device characterized by the above-mentioned. 3. The DCME device according to claim 2, wherein said first storage means includes first and second FIFO memories and a memory CONT unit, and said first storage means is provided in a request generation frame during a unit processing time. The first flag information generated by the generation unit is temporarily stored in the second storage unit together with the request type, and the request generation channel number that was not output to the allocation control unit during the previous unit processing time is temporarily stored in the second storage unit. From the first FIFO memory, the second F
The memory CONT is moved to an IFO memory, and in the FIFO organizing frame, the memory CONT reads the channel number from the second FIFO memory and inputs the channel number to the second storage means to read the first flag information. If the first flag information is the same as the previous time, the channel number is written to the first FIFO memory as it is, and if the first flag information is different, writing to the first FIFO memory is not performed and a request at the previous unit processing time is generated. The channel number is extracted from the first FIFO memory, and in the next new request channel number storage frame,
The first flag information and the request type are read from the second storage means in a time-division manner with respect to the input channel number, and the request type is different from that of the previous unit processing time, and the request type is an allocation request Means to output the corresponding channel number to the first
Additional writing to the FIFO memory of the first
The channel number in the FIFO memory including the one added this time is moved to the second storage means, and in the highest priority request selection frame, the highest priority request selection means stores the channel number starting from the head of the second FIFO memory. Number, latches the request type and the channel number, writes the channel number in the first FIFO memory, reads the second channel number from the second FIFO memory, reads the corresponding request type, and latches it. If the priority is lower than the first request type as compared with the first request type, the second request type is not latched and the first request type is left as it is, without latching the second request type. If the priority is higher than the first request type, the second request type is latched in place of the first request type. And the request types are compared for all the channel numbers in the second FIFO memory, and the channel number having the highest priority and the request type are finally latched. Wherein the channel numbers in the second FIFO memory are all transferred to the first FIFO memory. 4. The DCME device according to claim 3, wherein the generation unit is configured to prevent double registration for each unit processing time in addition to the allocation request type and the first flag information in the request generation frame. Is generated in the off state, and the second flag information is stored in the second storage means for all the channels using the channel number as an address. In the FIFO organizing frame, the memory CONT The unit also reads out the second flag information from the second storage means, and stores the channel number as it is only when the first flag information is the same as the previous time and the second flag information is in the off state. Writing to the first FIFO memory,
The allocation request type and the first flag information for the channel number written in the first FIFO memory are written in the second storage means, and the second flag information is turned on to be stored in the second storage means. A DCME device comprising means for writing to prevent double registration of a request generation channel number.