JP2737760B2 - Routing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a routing system used to connect a plurality of input lines to a plurality of output lines.

[0002]

2. Description of the Related Art Conventionally, this type of routing system generally uses an AT line from an input line as shown in FIG.
M (asynchronous transfer mode) is used to transfer cells to the output line. Therefore, the routing system includes a plurality of input ports (external input ports) 15 and a plurality of output ports (external output ports) 16, and further includes an ATM switch network 21 between the input and output ports 15 and 16. ing. The ATM switch network 21 has a switch circuit 22 and a buffer 23, and the switch circuit 22 is controlled by a switch control unit 27. The illustrated switch control unit 27 includes a switch controller 31 and a counter unit 32.

More specifically, the switch circuit 22
Forms an internal path between the internal input and internal output ports under the control of the switch controller 31. To this end, the switch circuit 22 has a plurality of switch units divided into a plurality of stages, and a buffer 23 provided corresponding to an input or output port.
And In this case, the buffer 23 holds ATM cells arriving at random, so that congestion does not occur even if ATM cells are concentrated on a specific input or output port.

Further, the routing system has an input section 25 on the input line side and an output section 26 on the output line side. The illustrated input unit 25 is an input cell (external input cell) provided from the external input port 15.
To the switch circuit 2 as the first output signal 01 as it is.
2 and separate the header of the external input cell,
It has a header separation unit that outputs the second output signal 02 to the routing table 29. Here, an output port number (internal output port number) of the switch network 21 is stored in the routing table 29 corresponding to each header.

In any case, the routing system is designed so that the probability of collision between ATM cells is as small as possible, for example, about 10 ^-10 . However, even in such a case, if collision occurs between ATM cells or between ATM cells, the buffer 23
Overflow occurs, ATM cells are discarded,
The discarded ATM cells will not be transmitted to the output line. Therefore, always monitor for collisions of ATM cells,
It is necessary to analyze the cause of ATM cell discard.

In order to detect the collision of ATM cells, each buffer 2 is counted by a counter unit 32 which counts the number of discarded cells caused by overflow of each buffer.
3 is monitored by a microprocessor 33. In this configuration, the number of discarded cells can be detected by monitoring the count value of the counter 32.

As another conventional routing system, external input cells each having a length of 53 bytes are multiplexed at an input section to form an internal multiplexed cell, and this internal multiplexed cell is input to an ATM switch network. Some types are provided to a switch circuit via a port (internal input port). In this case, each internal multiplexing cell is separated into a plurality of external output cells at the output section and transmitted via the output line.

As described above, in a system where external input cells are multiplexed, the internal multiplexed cells are supplied to the switch circuit at a higher speed than the external input cells. Therefore, the switch circuit needs to operate at a high speed, but such a high-speed operation is difficult with a normal switch circuit.

In consideration of this, it has been proposed to process each cell of the internal multiplexed cell in a switch circuit in parallel for each bit.

[0010]

However, as in the former case, merely counting the discarded ATM cells requires the external input port, output port number, VP, and VP associated with the discarded cells.
It is impossible to obtain header information such as I and VCI. Therefore, the cause of the discarded ATM cell cannot be sufficiently analyzed.

Also, in the latter system where external input cells are multiplexed and parallel processing is performed, each external input cell is composed of 53 bytes which is a prime number. The number of units has become extremely large, making it difficult to achieve.

On the other hand, in order to reduce the number of switch units for performing parallel processing, the length of a 53-byte external input cell is converted to 54, 56, or 64 bytes, and the converted cell (hereinafter referred to as a conversion cell) is used. ) In parallel. As described above, by converting the cell length, the amount of hardware can be reduced.

Here, as described above, when the cell length is converted, an empty field occurs in the converted cell. Usually, it is considered that an internal output port number, an external output port number, and the like are arranged as routing information in this empty field. However, as the size of the switch circuit increases, the amount of routing information also increases, so that there is a drawback that the length of the conversion cell is determined depending on the amount of routing information. Therefore,
This configuration has a drawback in that it cannot cope with an increase or change in the scale of the switch network.

As described above, in the conventional routing system, it cannot be said that each external input cell is effectively processed in order to analyze a discarded cell or transmit a routing information signal.

[0015]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a routing system capable of effectively processing each cell.

Another object of the present invention is to provide a routing system capable of accurately analyzing a discarded cell when an overflow occurs in each buffer.

Still another object of the present invention is to provide a routing system capable of easily coping with an increase in the scale of a switch network without increasing hardware.

The routing system to which the present invention is applied is used to connect a plurality of external input ports to a plurality of external output ports, and includes a plurality of internal input ports, a plurality of internal output ports, and an internal input port. A switch circuit provided between the internal output port, an input unit provided between the external input port and the internal input port, an output unit provided between the internal output port and the external output port,
A control unit coupled to the input unit and the switch circuit, the control unit controlling the switch circuit to form an internal path between the internal input port and the internal output port; An external input cell including a header is sequentially provided to the port, and an external input port number and an external output port number are assigned to the external input port and the external output port. Each port has a configuration in which an internal input port number and an internal output port number are assigned.

Here, the input unit according to the present invention is provided between each of the external input ports and each of the external output ports, and in response to the external input cell, the external input port and the internal input port. A port number generation unit that generates an output port number signal representing one of the internal output port numbers while generating an input port number signal related to any of the above, each of the external input cells, the input port number signal, And a signal supply unit for sending the external input cells to the switch circuit in response to the output port number signal, and supplying the input port number and the output port number of the header to the control unit. ing. On the other hand, the control unit receives the header and the output port number signal, controls the switch circuit based on the header and the output port number signal, and controls the switch to form the internal path. Receiving at least one of a port number signal and the input port number signal and the header, processing the header using at least one of the output port number signal and the input port number signal; Is provided.

An input unit of a routing system according to another aspect of the present invention is coupled to the external input port, and converts a cell format of the external input cell into a routing information field for a routing information signal, the payload field, and First format conversion means for converting to an internal format having the header field and generating a converted cell having the routing information field, and coupled to the first format conversion means for relating to the external input port number Port number assigning means for assigning the first port number to the routing information field of the converted cell as the routing information, and generating an internal cell having the first input port number in the routing information field;
Coupled to the port number assigning means, the internal cell,
A cell multiplexing unit for multiplexing into an internal multiplexed cell sequence having a multiplexed input cell including a first input port number, the cell multiplexing unit being coupled to one of the cell multiplexing unit and the internal input port; And generating a second port number associated with the internal output port number and the external output port number based on the input port number and the multiplexed input cell, and setting the first port number to a second port number. Number generating means for sequentially replacing the multiplexed cells by the port numbers of the switch network and the switch network and the control unit, wherein the replaced multiplexed cells and the internal output port numbers are replaced by the switch network. And transmission means for transmitting the signals to the control unit. In this case, the control unit is coupled to the transmission unit and the switch circuit, and includes a unit that controls the switch circuit based on the internal output port number. A separating unit coupled to the indicated internal output port and separating the replaced multiplexed cell into an external output cell based on the selected second port number; and Output means for sequentially outputting to the external output port.

[0021]

Referring to FIG. 2, a routing system according to a first embodiment of the present invention is different from the system shown in FIG. 1 in that an input unit, a control unit, and a microprocessor operate differently from the system shown in FIG. 1 is similar to the system shown in FIG. In this regard, the input, control, and microprocessor of FIG. 2 are designated by reference numerals 25a, 27a, and 33a, respectively. An external input cell is supplied to the illustrated input unit 25a through the external input port 15. Each external input cell is composed of 53 bytes and transmits a 5-byte header and a 48-byte payload arranged in a header field and a payload field, respectively. VPI or VCI as header
Is used.

The routing system has an external input port 1
5 has a format converter 36 connected thereto.
Each format converter 36 serves to convert a 53 byte external input cell into, for example, a 56 byte internal input cell. This inner input cell has the same header and payload as the outer input cell. As is apparent from this, the internal input cell has a 2-byte empty field as a result of the format conversion, and each internal input cell is transmitted from the format converter 36 to the input port number setting device 37.
Has been given to.

Referring also to FIG. 3, the input port number setting unit 37 has a field extraction circuit 371 and an input port number generator 372. The input port number generator 372 generates an external input port number assigned to each external input port 15. Since the illustrated external input cells are not multiplexed, the external input port number matches the switch input port of the switch network 21, that is, the internal input port. On the other hand, format converter 3
6. Field extraction circuit 3 to which internal input cells are given from
Reference numeral 71 detects an empty field of the internal input cell. When an empty field is detected, an external input port number is sent from the input port number generator 372, and is arranged as routing information in an empty field of each internal input cell. In this connection, the empty field is called a routing information field. In this way, the external input port number is sent to the header separation circuit 28a together with the header.

Referring to FIG. 2, the header separation circuit 28a separates the header field and the routing information field from the internal input cell while passing the internal input cell as the first output signal O1. As a result, the header and the external input port number are separated by the header separation circuit 28a and sent to the routing table 29a as the second output signal O2. Routing table 2
9a stores an output port number corresponding to each header (VPI or VCI), that is, a switch output port number (internal output port number). For this reason, the switch output port number (internal output port number) is read from the routing table 29a based on each header, and transferred to the control unit 27a together with the header and the external input port number.

The control unit 27a includes the switch controller 3
1a and a waste cell memory 40. The switch controller 31a is provided with a switch output port number, a header, and an external input port number. The switch controller 31a is a switch network 2
1 controls the buffer 23 and performs routing control based on the switch output port number. Switch control
The roller 31a is provided with a battery for each output port in a known manner.
Of the number of cells written to the file 23 and the number of cells read
The difference, that is, the number of cells staying in the buffer 23 is counted.
Is managed by counting the data. Specifically
For example, if the counter value of the counter is
The capacity (upper limit) allocated to the output port has been reached
State, cells routed to that output port arrive.
When wearing, the switch controller 31a
3 is recognized as an overflow, and that cell is written.
Absent. That is, the switch controller 31a
No write control signal is sent to the CPU 23. This and
Switch controller 31a
Rooty with header and external input port number entered
And write it to discard cell memory 40
No. In this case, the written header and external input port number correspond to the discarded cell, and these are stored in the discard memory 40 as a history information signal. The monitoring microprocessor 33a reads the history information signal, that is, the header and the external input port number from the discarded cell memory 40 via the bus 34, and analyzes the discarded cell history.

As described above, the header and the external input port number are transferred to the discard cell memory 40 as a history information signal. Therefore, the microprocessor 33a can easily analyze the cause of the discard regarding the discarded cell.
In particular, when a bit slice type ATM switch circuit is used, the cause of discard can be analyzed without reconfiguring the bit sliced cell.

The routing system according to the second embodiment of the present invention shown in FIG. 4 multiplexes a plurality of external input cells. In FIG. 4, the routing system has an external input port 15 and an external output port 16 connected to an input line and an output line, respectively. The external input port 15 is divided into a plurality of input port groups indicated by 15a and 15b in FIG. 4, and the external output port is also divided into a plurality of output port groups indicated by 16a and 16b. ing. Hereinafter, an external input cell having a bit rate of 15.52 Mbps is supplied to an input port group 15a called a first input port group, while 622 is input to an input port group 15b called a second input port group. .08Mb
External input cells at a bit rate of ps are provided. Similarly, a 15.52 Mbps external output cell is supplied to the external output port group 16a called the first output port group, and 622.08 Mbps is supplied to the external output port group 16b called the second output port group. External output cells are provided. In the example shown, each external input cell of the first and second external input port groups is multiplexed to an internal multiplexed input cell, and each internal multiplexed input cell has a bit rate of 2488.32 Mbps. ing.

In this relation, the first external input port group 15a has 16 ports as indicated by # 1 to # 16.
The second external input port group is formed by four external input ports as indicated by # 1 to # 4. Similarly, the first external output port group 16a includes 16 external output ports as indicated by # 1 to # 16,
The second external output port group 16b is formed by four external output port groups as indicated by # 1 to # 4.

Here, it is assumed that the external input cell is sequentially supplied to each external input port 15 as a transmission line signal. 4, each transmission path signal is supplied to a format converter 36 (herein, referred to as a first format converter) having a configuration similar to that of FIG.

In FIG. 5, each transmission path signal is shown in FIG.
As shown in (1), it includes an overhead area such as an SOH (section overhead) area, valid cells, and empty cells. Each valid and empty cell has a header,
The external input cells are formed as described with reference to FIG. Therefore, as shown in FIG. 5B, a 53-byte external input cell is composed of a 5-byte header field and 4 bytes.
And a payload field of 8 bytes.

The first format converter 36 shown in FIG. 4 receives the transmission path signal and converts this transmission path signal to the signal shown in FIG.
Is converted into an internal signal as shown in FIG. Each internal signal has a valid cell and an empty cell, like the transmission line signal. Further, a routing information field and a header field are added to valid cells and empty cells to form internal input cells. The routing information field will be described later in detail. The routing information field has, for example, a 2-byte length. As a result, the first format converter 36 sequentially outputs internal signals as shown in FIG.

Referring to FIGS. 6 and 4, the format converter 36 includes a FIFO memory 361, a valid cell detector 3,
62, a write control unit 363, and a read control unit 364. The transmission path signal is given to both the FIFO memory 361 and the valid cell detector 362. The valid cell detector 362 sequentially detects only valid cells in response to a cell head signal CH indicating the head of each cell. Specifically, when the cell head signal CH and the transmission path signal are supplied, the valid cell detector 362 detects valid cells one by one with reference to the cell head signal CH. As a result, the valid cell detector 362 synchronizes with each valid cell and sends out a valid cell detection signal indicating detection of a valid cell to the write control unit 363.

The illustrated write control unit 363 is supplied with a frame signal FM of a transmission path signal and a lock WC to be written, together with a valid cell detection signal. The write control unit 363 outputs a write timing signal to the FIFO memory 361 with reference to the valid cell detection signal, the frame signal FM, and the write clock WC. In this way, the write timing signal is synchronized with each valid cell,
O memory 361. As a result, the FIFO memory 361 stores only valid cells among the cells from the external input ports 15 as storage cells under the control of the write control unit 363. The storage cells are sequentially stored in the FIFO memory 36.
1 is output as an internal signal as shown in FIG. 5D under the control of the read control unit 364. In this case, the read control unit 364 controls the FIFO memory so that the routing information field is added to the head of each valid cell, and each storage cell is read from the FIFO memory 361 at the phase assigned to that cell. . When no valid cell exists in the FIFO memory 361,
Empty cells are generated from FIFO memory 361.

As described above, the internal signal is supplied from each first format conversion unit 36 to the corresponding input port number setting unit 37 described with reference to FIGS. It is located in the routing information field of the input cell.

Referring back to FIG. 4, the internal signals from the first and second external input groups are multiplexed by the cell multiplexing unit 41 to form an internal multiplexed input cell sequence. The internal multiplexed input cell row is an internal input port of the switch network 21,
That is, it is transmitted to the switch input port through the header converter 43. The switch network 21 has a configuration similar to that shown in FIG. 2, and the internal input port may be called a high-speed input port.

Referring to FIG. 7 together with FIG. 4, each header converter 43 includes a header conversion table 431, an input port number detector 432, a header detector 433, and a rearrangement circuit 434. As described in connection with FIGS. 3, 4, and 5, each of the inner multiplexed input cells has a header information field and a payload field, as well as a routing information field for an external input port number. I have.

In FIG. 7, the internal multiplexed input cells are provided to an input port number detector 432, a header detector 433, and a rearrangement circuit 434. The input port number detector 432 detects an external input port from each internal multiplexed input cell and generates a port number detection signal representing the detected external input port number. On the other hand, the header detector 433
Detects a header such as VPI or VCI, and outputs a header detection signal indicating the detected header. The header detection signal and the port number detection signal are supplied to the header conversion table 431 as address signals.

The switch network 21 shown in FIG.
Has a plurality of switch output ports, that is, internal output ports, each port is assigned an internal output port number IOP, and a cell separation unit 45 is connected to each port. Each cell separation unit 45 has a plurality of intermediate output ports, and these intermediate output ports are divided into first and second external output port groups 16a and 16b.
Each intermediate output port has an intermediate output port number I
M has been assigned and is connected to the second format converter 37.

In FIG. 7, the header conversion table 43
1 is the internal output port number I of the switch network 21
It has a first area A1 for storing an OP, a second area A2 for storing an intermediate output port number, and a third area A3 for storing a header such as VPI or VCI. ing. When the header detection signal and the port number detection signal are given to the header conversion table 431 as address signals, a set of the internal output port number, the intermediate output port number IM, and the address of the header conversion table 431 in which the header is indicated by the address signal Are read out simultaneously.

The internal output port number IOP is sent to the control section 27b as a read output port number, while the intermediate output port number IM and header are sent to the rearrangement circuit 434 as a read intermediate output port number and read header. The rearrangement circuit 434 replaces the external input port number and header of each internal multiplexed input cell with the read intermediate output port number and read header. The read intermediate output port number and the read header are arranged in the routing information field and the header field, respectively, and supplied to the switch network 21.

As described above, by replacing the external input port number with the read intermediate output port number,
The expansion of the routing information field can be prevented, and the amount of routing information signals can be minimized. Further, the read output port number is sent to the control unit 27b via a signal line.

Referring to FIG. 8 together with FIG.
b has a plurality of output port extraction circuits 271 connected to the header converter 43 and a plurality of comparators 272 connected to each output port extraction circuit 271. Here, the control unit 27b includes first to N-th output port extraction circuits 271.
-1 to 271-N are converted to first to N-th comparators 272-1.
Generality is not lost even if it is assumed to have it together with .about.272-N. The first to Nth output port extraction circuits 271-1 to 271-N extract the read output port numbers, and the extracted output port numbers are sequentially sent to the first to Nth comparators 272-1 to 272-N. Supplied. Since the first to N-th comparators 272-1 to 272-N are given first to N-th physical port numbers corresponding to the switch output ports of the switch network 21, the extracted output port numbers Are comparators 272-1 to 272
At -N, each is compared with the physical port number. As a result of the comparison, when a match is detected, the first to Nth switch control signals SW1 to SWN are sent from each of the comparators 272-1 to 272-N to the switch network 21.

The replaced, that is, the internal multiplexed input cell having the read output port number is sent out to the switch output port IOP as an internal multiplexed output cell in accordance with the switch control signals SW1 to SWN, and the cell separation unit shown in FIG. 45. The cell separator 45 separates the internal multiplexed output cells into internal output cells based on the intermediate output port number IM. The internal output cell is the second format converter 4
7 are supplied to external output ports 16a and 16b, respectively.

Referring to FIG. 9 in conjunction with FIG. 4, a second format converter 47 is used to convert internal output cells to transmission line output cells. It is assumed that the illustrated transmission line output cell has the same bit rate as the transmission line input cell input through the external input ports 15a and 15b. In this case, the second format converter 47
6 includes a FIFO memory 471, a valid cell detector 472, a write control unit 473, and a read control unit 474, as in FIG.

In FIG. 9, the intermediate output cells are
The O memory 471 and the valid cell detector 472 are provided. The valid cell detector 472 receives a cell head signal indicating the head of each cell, checks each header field of the intermediate output cell, and detects a valid cell. When a valid cell is detected, the valid cell detector 472 generates a valid cell detection signal indicating the detection of a valid cell. This valid cell detection signal is applied to write control unit 4 operating in response to a write clock train.
It is sent to 73. The write control unit 473 supplies a write timing signal to the FIFO 471 in synchronization with a valid cell. As a result, valid cells are sequentially stored in the FIFO 471.
In this case, the write control unit 473 controls so that the routing information field preceding the valid cell is not written into the FIFO 471.

When a valid cell is written into the FIFO 471, the read control unit 474 performs read control according to the read clock RC and the frame signal of the transmission line. More specifically, valid cells are sequentially read from the FIFO 471 in accordance with the phase of the transmission line frame signal FM. Such a read operation is performed outside the overhead area. If no valid cell is stored in the FIFO 471, an empty cell is transmitted.

Also in the embodiment shown in FIG. 4, the external input port number is arranged in the routing information field and replaced with the intermediate output port number. For this reason, even if the amount of routing information increases, there is no need to expand the routing information field, and therefore the amount of hardware can be reduced. In addition, when the intermediate output port number is the same as the external output port number, it may be positioned in the external output port number or the routing information field.

[0048]

As described above, according to the present invention, by placing the input port number in the routing information field of the input cell, if an overflow occurs in the buffer of the switch network, the input port number is changed. It is possible to easily analyze a discarded cell by using the input port number and replace the input port number with the output port number, thereby easily coping with expansion and change of the routing system without expanding the routing information field. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a conventional routing system.

FIG. 2 is a block diagram illustrating a routing system according to a first embodiment of the present invention.

FIG. 3 is a block diagram showing an example of an input port number setting device used in the routing system shown in FIG. 2;

FIG. 4 is a block diagram illustrating a routing system according to a second embodiment of the present invention.

FIG. 5 is a diagram for explaining a format used in the routing system of FIG. 4;

FIG. 6 is a block diagram illustrating a format converter used in the routing system of FIG. 4;

FIG. 7 is a block diagram illustrating a header conversion unit used in a second embodiment of the present invention.

FIG. 8 is a block diagram for explaining a control unit according to a second embodiment of the present invention.

FIG. 9 is a block diagram illustrating a format converter according to a second embodiment of the present invention.

[Explanation of symbols]

 15, external input port 16, external output port 21, switch network 22, switch circuit 23, buffer 25a, input unit 26, output unit 28a, header separation circuit 29a, routing table 27a, control unit 31a, switch controller 36, format conversion Device 37, input port number setting device 40, discarded cell memory 33a, microprocessor

Claims (8)

(57) [Claims] 1. A routing system used to connect a plurality of external input ports to a plurality of external output ports, the routing system comprising: a plurality of internal input ports;
A plurality of internal output ports, a switch circuit provided between the internal input port and the internal output port, an input unit provided between the external input port and the internal input port, and an internal output port and an external output port. And an output unit provided between the control unit and the control unit, which is coupled to the input unit and the switch circuit, and controls the switch circuit to form an internal path between the internal input port and the internal output port. And each of the external input ports is sequentially provided with an external input cell including a header, and the external input port and the external output port are assigned an external input port number and an external output port number. On the other hand, the internal input port and the internal output port have a configuration in which an internal input port number and an internal output port number are assigned, The external input port is provided between each external input port and each external output port, and in response to the external input cell, generates an input port number signal associated with any of the external input port and the internal input port. A port number generating unit that generates an output port number signal representing one of the internal output port numbers; and the external input cells, the input port number signal, and the external input signals in response to the output port number signal. A signal supply unit that sends a cell to the switch circuit and supplies the header with the input port number and the output port number, respectively, to the control unit.The control unit sends the header and the output port number signal to the control unit. A switch for controlling the switch circuit based on the header and the output port number signal to form the internal path. Switch control means, receives at least one of an output port number signal and the input port number signal, and the header, and processes the header using at least one of the output port number signal and the input port number signal. And a processing means for analyzing each of the external input ports. 2. The routing system according to claim 1, wherein said header is formed by at least one of VPI and VCI. 3. The routing system according to claim 1, wherein said processing means is coupled to said signal supply means and stores said input port number signal and header, and stores said stored input number signal and header. A routing system, comprising: a storage unit for generating; and a unit coupled to the storage unit, for analyzing a history of each external input cell based on a stored input number signal and a header. 4. A routing system used to connect a plurality of external input ports and a plurality of external output ports, the routing system comprising: a plurality of internal input ports;
A plurality of internal output ports, a switch circuit provided between the internal input port and the internal output port, an input unit provided between the external input port and the internal input port, and an internal output port and an external output port. And an output unit provided between the control unit and the control unit, which is coupled to the input unit and the switch circuit, and controls the switch circuit to form an internal path between the internal input port and the internal output port. And each of the external input ports is sequentially provided with an external input cell having a cell format having a payload field and a header field for a header, and the external input port and the external output port are provided with an external input cell. A port number and an external output port number are assigned, while the internal input port and the internal output port are assigned an internal input port. A number and an internal output port number are assigned, the input unit is coupled to the external input port, the cell format of the external input cell is a routing information field for a routing information signal, And a first format converting means for converting the data into an internal format having the header field and generating a converted cell having the routing information field, and being coupled to the first format converting means, Port number assigning means for assigning an associated first port number to the routing information field of the converted cell as the routing information, and generating an internal cell having the first input port number in the routing information field; Port number assignment Coupled to the means, the internal cells,
A cell multiplexing unit for multiplexing into an internal multiplexed cell sequence having multiplexed input cells including a first input port number, the cell multiplexing unit being coupled to one of the cell multiplexing unit and the internal input port; 1 based on the input port number and the multiplexed input cells, the internal output port number;
Number generating means for generating a second port number associated with the external output port number and sequentially replacing the first port number with a second port number to form a replaced multiplexed cell; Coupled to a switch network and the control unit;
Transmission means for transmitting the replaced multiplexed cell and the internal output port number to the switch network and the control unit, respectively, while the control unit is coupled to the transmission means and the switch circuit. Means for controlling the switch circuit based on the internal output port number, and wherein the output section is coupled to an internal output port indicated by the internal output port number, and A separation unit that separates the replaced multiplexed cell based on a second port number and converts the multiplexed cell into an external output cell; and an output unit that sequentially outputs the external output cell to the external output port. A routing system, characterized in that: 5. The routing system according to claim 4, wherein said cell multiplexing unit is connected to said external input port via said port number allocating means, and is provided with an intermediate input port number. A routing system having a port, wherein the port number assigning means assigns the intermediate input port number to the internal cell as the first port number. 6. A routing system according to claim 5, wherein the separating means is connected to said external output ports through said output means, and, an intermediate output port intermediate output port number is assigned And the number generation means gives the intermediate output port number as the second port number. 7. The routing system according to claim 4, wherein said port number assigning means assigns said external input port number to said internal cell as said first port number. 8. The routing system according to claim 7, wherein said number generating means gives said external output port number as said second port number.