JP2735173B2 - One-chip memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage element, and more particularly to a storage circuit suitable as a frame buffer for a high-speed graphic display. BACKGROUND OF THE INVENTION Graphic display devices have begun to require large-capacity display information storage memories, that is, frame buffers, with the improvement in display resolution. However, an increase in the capacity of the frame buffer leads to an increase in the number of memory accesses when displaying graphic data. Therefore, it is necessary to reduce the number of memory accesses in order to speed up the display. As means for reducing the number of memory accesses,
There is a method of executing arithmetic processing inside a frame buffer for a graphic display. FIG. 2 shows an example of a frame buffer using this method. In FIG. 2, 1
Is a 16-bit arithmetic unit, 2 is a memory for storing graphic data, 3 is an arithmetic function designating register of an arithmetic unit, 4 is a write mask circuit, and D _{15 to} D ₀ are 1 from the data processing device.
6-bit data, DO _{15 to} DO ₀ are read data of memory,
FC ₃ ~FC ₀ computation function specifying data for calculator, M ₁₅ ~M
₀ is a write control signal for the memory, A _{23 to} A ₁ are 23-bit address signals from the data processing device, WE is a write control signal from the data processing device, FS is a latch control signal for the arithmetic function designation register, and MS is a write mask. This is a latch control signal for the circuit. The reason why the number of times of memory access is reduced in the configuration of FIG. 2 will be described. When drawing a graphic on a bitmap type graphic display, the graphic is represented by a set of points, and the graphic is drawn by repeating point drawing. For this reason, access to the frame buffer is performed not in units of 16 bits but in units smaller than the data width constituting the memory, such as 1 bit or 4 bits. In general, when writing a point, an operation with write data is required, and therefore an operation with memory data and a write in bit units are required. Normal memory does not have these functions.
The calculation is performed inside the data processing device that performs the graphic drawing process, and the data is written in the same address after reading the data of the memory address to be written and executing the bit calculation. Therefore, even when writing 1-bit data, two memory accesses are required. In the frame buffer shown in FIG. 2, the arithmetic unit 1 realizes the operation of the memory data and the operation of the data processing unit, and the mask circuit 4 realizes the data writing in bit units. The memory access required for writing 1-bit data is as follows. The data processor only needs to do it once. Access to the memory 2 is required twice: read and write. However, a normal memory has an access mode called read-modify-write that realizes read and write in one time, so that it can be realized in one time. As described above, the frame buffer shown in FIG. 2 is effective for speeding up the graphic display, but requires a large number of circuits to be added around the memory element, so that the reliability is reduced and the cost is high. There is a problem that becomes. The frame buffer shown in FIG. 2 is shown in, for example, Nikkei Electronics 1984.8.27, “Designing a 1280 × 1024 Pixel Graphic Display Frame Buffer with 64KRAM with Nipple Mode” (P.227 to 245). . [Object of the Invention] An object of the present invention is to solve the above-mentioned problems and to provide a one-chip multi-function memory device capable of setting a predetermined operation mode from among a plurality of operation modes without increasing the number of pins of the device. To provide a device. Another object of the present invention is to provide a one-chip memory device that minimizes overwork for setting an operation mode. It is another object of the present invention to provide a one-chip memory device that realizes a compact high-speed graphic display frame buffer. [Summary of the Invention] In order to achieve the above object, a feature of the present invention is that a terminal to which an address signal is supplied from the outside and a plurality of storage locations are allocated and respond to the address signal from the outside. In a storage element from which reading or writing of the plurality of storage locations is performed, and in a read-modify-write cycle in which data is read or written from or to a storage location specified by the address signal of the storage element, a plurality of different A computing unit for performing an operation in any one of the operation modes, the operation mode being prior to a read-modify-write cycle for reading or writing data to or from the storage element. The terminal is externally connected via a predetermined part of the terminals to which the address signal is supplied in a set period. Holding means for holding an instruction signal for instructing the operation in the one operation mode according to the operation mode signal supplied from the control unit, and whether or not to permit the operation unit to write to the storage element during the operation mode setting period. Further comprising a write selection unit that holds the signal, wherein the arithmetic unit is prohibited from performing any of data reading or writing of the storage location by designating the address signal during the arithmetic mode setting period, In the read-modify-write cycle, data is written to the storage element in bit units by the write selection unit holding a signal that permits writing, thereby providing a one-chip memory device. . Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. First, the concept of the present invention will be described. In order to reduce the peripheral circuits of the frame buffer memory shown in FIG. 2, an integrated circuit (IC) integrating a memory, a computing unit, a computing function designation register, and a write mask circuit is required.
rcuit). In a current graphic display, a logical operation is mainly required as an arithmetic function, so that an arithmetic unit can be divided into bit units of arithmetic data. Even in the case of using arithmetic operation, division by a bit unit is possible in principle by adding a circuit for handling a carry signal. Write mask circuit 4
Is a circuit that performs write control on a bit basis, so that it can be clearly divided on a bit basis. However, since the arithmetic function designation register 3 has a bit length determined by the number of arithmetic functions of the arithmetic unit 1 and has no relation to the bit length of the arithmetic data (here, 16), it is not possible to divide the arithmetic data into bit units. Can not. Therefore, the operation function specification register 3 must be provided for each divided unit. Although it is useless to have the same function for each divided unit in this way, the degree of integration of ICs increases every year, and the number of elements used as peripheral circuits for the number of memory elements when integrated is increased. This is not a problem because the ratio of numbers is so small that it does not reach 1%. In the case of integration, it is not so problematic to have the arithmetic function designation register 3 for each division unit as described above, but it is necessary to divide the frame buffer shown in FIG. 2 into data bit units. Has a problem. In order to use the frame buffer shown in FIG. 2, it is necessary to write arithmetic function data in the arithmetic function designation register 3 and write mask data in the mask circuit 4 before actually performing memory access. The frame buffer of FIG. 2, since both data are the input signals a data signal D ₁₅ to D ₀ from the data processing device,
Since division into bits results in a one-bit signal, there is no problem in the write mask circuit 4, but only two types of computations can be designated in the computation function designation register 3. As described above, it is a problem that the number of arithmetic functions varies depending on the bit configuration of the memory. The present invention focuses on the fact that it is performed on the data bus for specifying the operation function and therefore depends on the bit division of data, and designates using an address signal that does not depend on the bit division unlike the data bus. . Next, an embodiment of the present invention will be described. FIG. 1 shows the configuration of a frame buffer memory circuit according to an embodiment. 1 computing unit, 2 a memory device, 3 arithmetic function specifying register, the write mask circuit 4, Dj is 1-bit signals in the data signal 16 bits Gurafiku drawing data processor, A ₂₃ to A ₁ data Address signal of the processing device, WE is a write control signal of the data processing device, FS is a data set control signal for the arithmetic function designation register 3 and the write mask circuit 4, DOj is read data of the memory element 2, and DIj is an arithmetic operation of the arithmetic unit 1. The result data, Wj, is a write control signal for the memory element 2. FIG. 3 shows the configuration of the write mask circuit. 41 is a write mask data storage register, 42 is a write control signal WE
This is a gate for suppressing the above. FIG. 4 is an example of the configuration of a frame buffer using the memory circuit of FIG. FIG. 4 shows a 4-bit configuration to clarify the connection relationship. FIG. 5 shows an example in which the memory circuit of the embodiment is applied to a graphic display system. Reference numeral 6 denotes a data processing device, and reference numeral 7 denotes a decoding circuit for generating a set signal FS. Hereinafter, the operation of the memory circuit of the embodiment will be described. In the embodiment, the memory circuit 5 is assigned to addresses from 800000H to 8FFFFFH. Here, H is an address indicating a hexadecimal number and having a byte unit. Decoding circuit 7 is 900000H ~ 900
The set signal FS is output at the address 01FH. The arithmetic functions of the arithmetic unit 1 are 16 types shown in FIG. When the data processing apparatus 6 writes F0FFH for example 900014H address, the decode circuit 7 outputs a set signal FS, to the arithmetic function specified register 3 address signal A ₄ to A ₁ i.e. 1010B (B 2 multiples) sets. As a result, the arithmetic unit 1 selects the logical sum as the arithmetic function as shown in the arithmetic function table of FIG. In the write mask circuit 4, one bit of the 16-bit data F0FFH from the data processor 6 is set in the write mask data storage register 41. 1 to be set
The bit is the same position as the bit position of the memory element. As a result, F0FFH is set as the write mask data. Next, the case where the data processing device 6 writes F3FFH at the address of 800000H will be described. It is assumed that 0512H is stored at the address 800000H. FIG. 7 shows the memory access timing of the data processing device 6. Write access to the memory circuit 5 of the data processing device 6 is a read-modify-write operation as shown in FIG. 0512 on the DO bus at the timing of read-modify-write
H is read, and F3FFH is input to the D bus. At the next modify timing, arithmetic unit 1 connects to D bus and DO
Calculates bus data and outputs the result to the DI bus.
In this case, since the value of the D bus is F3FFH and the value of the DO bus is 0512H, the data of the DI bus is F7FFH. This is because the arithmetic unit 1 has selected the logical sum as the arithmetic function in the operation described above. Finally, the data F7FFH on the DI bus is written at the timing of read-modify-write, but the write mask data is
F0FFH is set, and as shown in FIG. 3, since the gate 42 is turned on when the mask data is 0 and the gate 42 is turned off when the bit is 1, only the four bits D _{11 to} D ₈ are actually set. , And no write operation occurs in the remaining 12 bits. As a result, the data at address 800000H is 0
712H. As described above, in this embodiment, since a part of the address signal is used as the control signal, it is possible to realize a read-modify-write memory circuit capable of specifying an arithmetic function regardless of the data division method. it can. The difference between the memory circuit of the embodiment and a normal memory IC is that a set signal for setting an arithmetic function and write mask data.
Since only FS and IC pins increase by one pin,
This difference does not pose a problem when the circuit of FIG. For example, in a dynamic RAM of 64K × 1 bit configuration, 1
Since some pins are not used, FS
It is possible to use It is also apparent that this set signal may be realized in a timing sequence different from a normal memory access. For example, as shown in FIG. 8, the falling edge of RAS signal and WE
It is possible to make a set signal with the signal. In this embodiment, the data width is 16 bits and the unit of division is 1 bit. However, it is obvious that both values may be values other than the values described in this embodiment. In the embodiment, the designation of the arithmetic function and the designation of the write mask are performed at the same time. However, it is apparent that the designation may be performed separately. Further, it is apparent that the data width for designating the function of the arithmetic unit may be other than 4 bits. It is also apparent that the present embodiment may be applied to a memory having a configuration in which a shift register is built in and has a serial output. [Effects of the Invention] As is clear from the above description, according to the present invention, the setting of the operation mode of the multifunctional one-chip memory device can be realized without increasing the number of pins. Further, since the operation mode of the one-chip memory device is held and access can be executed one after another according to the operation mode, overwork for setting the operation mode can be minimized. In addition, since the specification of the read-modify-write write operation does not depend on the data width of the write data, a one-chip memory device with a built-in circuit for executing the read-modify-write operation with an arbitrary data width can be realized. For example, there is an effect that the frame buffer for a high-speed graphic display can be made compact.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a memory circuit of an embodiment, FIG. 2 is a block diagram showing a conventional frame buffer memory, FIG. 3 is a diagram showing a write mask circuit, FIG. FIG. 5 is a diagram for explaining the frame buffer configuration of the embodiment, and FIG.
FIG. 6 is a block diagram showing a configuration example of the graphic display system, FIG. 6 is a diagram for explaining an arithmetic function, FIG. 7 is a timing chart showing memory access timing, and FIG. 8 is a timing chart showing set signal creation timing. It is. 1 ...... calculator, 2 ...... memory device, 3 ...... calculation function specified register, 4 ...... write mask circuit, D ₁₅ to D ₀ ...... input data, A ₂₃ to A ₁ ...... address signal, WE ...... Write control signal, FS …… Set signal.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Koichi Kimura               292 Yoshida-cho, Totsuka-ku, Yokohama-shi Co., Ltd.               Hitachi, Ltd. microelectronics machine               Instrument development laboratory (72) Inventor Hiromichi Enomoto               1 Horiyamashita, Hadano City Hitachi, Ltd.               Tokoro Kanagawa Factory                (56) References JP-A-55-124187 (JP, A)                 JP-A-55-121574 (JP, A)                 JP-A-53-32634 (JP, A)                 JP-A-53-113437 (JP, A)                 JP-A-59-56284 (JP, A)                 JP-A-60-83296 (JP, A)

Claims (1)

(57) [Claims] A terminal to which an address signal is supplied from the outside, a plurality of storage locations assigned, and a storage element for reading or writing the plurality of storage locations in response to the address signal from the outside; A read-modify-write cycle for reading or writing data from or to a storage location specified by the address signal, the read-modify-write cycle comprising: an operation unit that performs an operation in any one of a plurality of different operation modes. A memory device, which passes through a predetermined part of the terminals to which the address signal is supplied in an operation mode setting period before a read-modify-write cycle for reading or writing data to or from the storage element. Operation in the one operation mode according to the operation mode signal supplied from outside. Holding means for holding an instruction signal to perform, and write selection means for holding a signal as to whether or not to allow the arithmetic unit to write to the storage element during the arithmetic mode setting period. In the operation mode setting period, the execution of any of data reading or writing at the storage location by the designation of the address signal is prohibited during the operation mode setting period, and in the read-modify-write cycle, the write selection unit outputs a signal that permits writing. A one-chip memory device characterized in that, by holding the data, data is written to the storage element in bit units.