JP2734587B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial Field of Use B Outline of the Invention C Prior Art D Problems to be Solved by the Invention E Means for Solving the Problems F Function G Example H Effects of the Invention A. Field of Industrial Use The present invention relates to a thin film transistor. , That is, a method of manufacturing a thin film transistor in which an insulated gate field effect transistor is formed in a thin film semiconductor layer.

B. Summary of the Invention The present invention relates to a method for manufacturing a thin film transistor, particularly a method for manufacturing a thin film transistor having a light beam annealing step of performing at least one of crystallization on an amorphous semiconductor layer or recrystallization on a microcrystalline semiconductor layer. Impurity atoms are implanted into the source and drain regions of the amorphous semiconductor layer or the micro-polycrystalline semiconductor layer before light beam annealing or the impurity atom-containing layer is formed, and then the light beam annealing step is performed. And / or recrystallization of a crystalline semiconductor or a recrystallization of a fine polycrystalline semiconductor layer, that is, growth of crystal grains, and at the same time, reliably form source and drain regions. Crystallization for crystalline or fine polycrystalline semiconductor layers Stone is intended to achieve simplification of manufacturing and to be able to perform the annealing of the diffusion or activation treatment of the impurity of the work and the source and drain formation recrystallization simultaneously.

C. Conventional technology Carrier mobility by crystallizing a hydrogenated amorphous silicon (hereinafter a-Si: H) film formed by plasma CVD (Chemical Vapor Deposition) at room temperature by pulsed laser irradiation It has become possible to produce a high-quality polycrystalline silicon film having a large temperature at a low temperature.
By applying such technology, a thin film transistor (TFT) using a polycrystalline silicon thin film can be realized in a low-temperature process of 300 ° C. or less (T, Sameshima and S, Usui; Materia
ls Research Society Symposium Proceedings vol.71
(1986) pp. 435-440).

In the above-described TFT manufacturing process of polycrystalline silicon using the laser annealing method by pulsed laser irradiation, laser treatment for activating the dopant, i.e., impurity atoms, is usually performed by ion implantation for crystallization and source and drain formation. In a separate process. Ninth
An example of a conventional TFT manufacturing method will be described in the order of steps with reference to the drawings. As shown in FIG. 9A, for example, an a-Si: H amorphous semiconductor layer (2) is entirely deposited on a glass substrate (1) by a plasma CVD method, and then selectively etched or the like. An island of the amorphous semiconductor layer (2) is formed by patterning. Then, the amorphous semiconductor layer (2) is irradiated with, for example, a pulse laser using excimer laser light L.

Thus, a polycrystalline semiconductor layer (3) in which the amorphous semiconductor layer (2) is polycrystallized is formed as shown in FIG. 9B. Then, a gate insulating layer (4) made of, for example, an SiO ₂ or SiN insulating layer and a gate electrode (5) are formed on the island-shaped polycrystalline semiconductor layer (3) at portions where a gate portion of a TFT is finally formed. To form a coating. Thereafter, impurities forming the source and the drain entirely, for example, n
Gas containing the type of impurity, by plasma CVD using, for example, phosphine PH ₃ and source gas monosilane SiH ₄ containing silicon, to form the impurity-containing layer (6).

After that, irradiation with the excimer laser light L is performed again to
As shown in FIG. C, impurities in the impurity-containing layer (6), for example, phosphorus P, are diffused into a portion of the polycrystalline semiconductor layer (3) that is not covered by the gate insulating layer (4) and the gate electrode (5). A high impurity concentration, for example, n-type source and drain regions (7) and (8) are formed.

Next, as shown in FIG. 9D, a target TFT (11) is formed by ohmic deposition of a source electrode (9) and a drain electrode (10) on the source region (7) and the drain region (8), respectively. Is what you get.

D. Problems to be Solved by the Invention However, according to such a method, a laser irradiation operation for crystallization of the amorphous semiconductor layer (2) described with reference to FIGS. ) Requires two steps of laser irradiation for introducing (diffusing) impurities into the polycrystalline semiconductor layer (3), which complicates the operation.

Furthermore, in particular, when irradiating a laser beam for impurity doping in the step of FIG. 9B, the gate portion formed by the gate insulating layer (4) and the gate electrode (5) already protrudes above the polycrystalline semiconductor layer (3). The laser light irradiation is insufficient in the vicinity of the gate portion due to the interference action due to the interference, and the impurity doping amount from the impurity-containing layer (6) becomes insufficient particularly in the vicinity of the gate portion, which greatly affects the characteristics. There is a problem that the characteristics may be unstable and the reliability may be reduced.

In the example described with reference to FIG. 9, the case where the impurity-containing layer (6) is provided so that impurities are diffused into the polycrystalline semiconductor layer (3) is used. In the case where the impurity is doped by ion implantation and the activation of the impurity is performed by laser irradiation, annealing is insufficient due to the interference effect due to the projection of the gate portion of the laser irradiation. There is a problem to be invited.

An object of the present invention is to solve the above-described problems, that is, to avoid repetitive work of annealing treatment of laser light irradiation, and to avoid instability of impurity introduction or activation of source and drain, and a TFT having good characteristics. Thin film transistor (TF
T) The manufacturing method is provided.

D. Means for Solving the Problems In the present invention, a method of manufacturing a semiconductor transistor having a light beam annealing step of performing at least one of crystallization for an amorphous semiconductor or recrystallization for a fine polycrystalline semiconductor layer, For example, as shown in FIG. 1E, the implantation of impurity atoms or the formation of an impurity-containing layer (22) containing impurity atoms is performed on the regions of the amorphous semiconductor layer (21) where the source and drain are to be formed, followed by light beam annealing. The process is performed by irradiating a light beam from the side where the gate portion is formed or from the side opposite to the side where the gate portion is formed to crystallize the amorphous semiconductor layer (21) or to grow crystal grains by recrystallization of the fine polycrystalline semiconductor. By performing at least one of the enlargement and forming the polycrystalline semiconductor layer (23) as shown in FIG. 1F, the source and the drain are formed. Down each region (24) and performing the formation of (25).

F. Function According to the above-described manufacturing method of the present invention, annealing for crystallization or recrystallization and annealing for diffusion or implantation of impurity atoms by one light beam annealing, for example, pulsed excimer laser irradiation can be performed. As a result, manufacturing can be simplified. In this case, the light beam irradiation is performed on the side where the gate section is formed, or the irradiation of the laser beam is not performed due to the presence of the gate section because the irradiation from the gate section is not performed. It is possible to avoid a disadvantage that a portion is generated in the source and drain regions near the gate portion and causes instability in characteristics.

G. Embodiment An example of a method of manufacturing a TFT according to the present invention will be described in detail with reference to FIG.

In this case, first, as shown in FIG. 1A, a substrate (31) made of a glass plate or the like that is transparent to light used for light beam annealing described later is provided. Then, a gate electrode (32) is formed on one main surface thereof. The gate electrode (32) can be formed by depositing, for example, Al, Mo, Cr, or the like on the entire surface to a thickness of, for example, about 500 °, and patterning as required by selective etching.

Next, as shown in FIG. 1B, a gate insulating layer (33) is formed on the entire surface including the gate electrode (32). This gate insulating layer (33) is made of, for example, SiO ₂ or SiN of 1000Å.
For example, by CVD. Further, an amorphous semiconductor layer (21), for example, a-Si: H containing 10 atomic% of hydrogen is formed thereon by, for example, plasma CVD.

As shown in FIG. 1C, a photoresist layer, that is, a photosensitive resin layer (34) was formed on the entire surface, and the back surface of the substrate (31), that is, the gate electrode (32) of the substrate (31) was formed thereon. The entire surface is irradiated with light Ls for exposure to the photoresist layer (34) from the opposite side, and the photoresist layer (34) other than immediately above the photoresist layer (34) using the gate electrode (32) as an optical mask.
To make it soluble.

Next, a development process is performed on the photoresist layer (34), and as shown in FIG.
Is patterned just above the gate electrode (32) into a pattern corresponding to the pattern of the gate electrode (32). Subsequently, a dopant such as n
Gas containing P next to the impurity of the type, for example, phosphine PH
₃ and an impurity-containing layer (22) at a temperature such as 100 ° C. that does not alter the photoresist layer (34) by using a silicon source gas such as monosilane SiH ₄ gas.
To form

Next, as shown in FIG. 1E, a photoresist layer (34)
And the impurity-containing layer (22) thereon is selectively removed. Next, a light beam L, for example, a XeCl excimer laser beam is irradiated from the entire surface of the impurity-containing layer (22) with a pulse to perform annealing.

As shown in FIG. 1F, when an amorphous semiconductor layer (21) is crystallized to form a polycrystalline semiconductor layer (23) as shown in FIG. 1F, the impurity atoms in the impurity-containing layer (22) are added to this. The portion where the impurity-containing layer (22) in FIG. 1E has been removed, that is, the portion directly above the gate electrode (32) where the impurity has not been introduced in FIG. 1E is used as a high resistivity channel forming region (26). Then, low-resistivity n-type source and drain regions (24) and (25) are formed on both sides thereof, respectively.

As shown in FIG. 1G, patterning for removing the polycrystalline semiconductor layer (23) by well-known selective etching is performed, and other portions are finally removed except for a portion where a TFT is to be formed.

As shown in FIG. 1H, for example, Al is entirely deposited on the source and drain regions (24) and (25), and this is selectively removed by etching or the like to remove the source and drain electrodes (27) and ( 28). In this way, a so-called inverted staggered TFT (35) is formed on the substrate (31) by the polycrystalline semiconductor layer (23) in which the gate portion is formed by the gate electrode (32) and the gate insulating layer (34). Is done.

According to this method, diffusion of impurities and crystallization of the amorphous semiconductor layer (21) are simultaneously performed by one light beam annealing, that is, irradiation of the laser beam L.
In this case, since the gate portion does not exist on the irradiation side of the laser light L, the laser light can be sufficiently irradiated even in the vicinity of the gate portion, and the impurity doping from the impurity-containing layer (22) can be sufficiently performed. As a result, the specific resistance in each of the source and drain regions (24) and (25) was sufficiently reduced.

FIG. 2 shows a measurement curve diagram of the relationship between the laser irradiation energy and the specific resistance in the source and drain silicon layers, and it can be seen from this that the specific resistance is sufficiently reduced.

The drain region I _D to a drain voltage V ₀ which TFT obtained in this way as a parameter - characteristic diagram of a gate voltage V _G is as shown in FIG. 3, showed excellent transistor characteristics.

FIG. 4 shows a process chart of another example of the manufacturing method of the present invention. In this example, a planar type TFT in which the source, drain and gate electrodes are led out from the same side is obtained. . In this case, as shown in FIGS. 4A to G, the same steps as in FIGS. 1A to G are performed. The gate electrode (32) in FIG. 1 is used as a second gate electrode or only as an exposure mask for the photoresist layer (34) in FIG. 4C. Then, as shown in FIG. 4H, the gate insulating layer (43) covers the entire surface of the polycrystalline semiconductor layer (23) on which the impurity-doped source and drain regions (24) and (25) are formed. ), For example
It is formed by a CVD method or the like of a SiO ₂ layer having a thickness of about 1000 mm.

Next, as shown in FIG. 4I, the source and drain regions (2) are selectively etched with respect to the insulating layer (43).
Drill electrode windows (24W) and (25W) on 4) and (25).

Next, a metal layer such as Al is formed on the entire surface including the windows (24W) and (25W) by, for example, vapor deposition, and is patterned by selective etching. As shown in FIG. Source and drain electrodes (27) and (28) are formed in the regions (24) and (25), and at the same time, a gate insulating layer on a channel forming region (26) therebetween, that is, a second gate insulating layer ( 43) An upper gate electrode, that is, a second gate electrode (44) is formed thereon. Thus, a planar TFT (45) is formed.

Incidentally, the TFT (45) thus obtained can also be used as a bipolar gate type TFT structure by using the lower gate electrode (32) in combination.

In the method described with reference to FIG. 4, the gate electrode (the side where the amorphous silicon semiconductor layer (21) has been irradiated with the laser beam L of the light beam annealing, that is, the side where the polycrystallization has been performed well, is performed. Since the upper gate according to 44) is formed, a TFT having better characteristics can be obtained.

Thus the measurement results of a similar I _D -V _G characteristic curve obtained was the TFT is shown in FIG. 5. As is clear from the above, the TFT (45) obtained by the method of the present invention also exhibited excellent transistor characteristics.

According to the method of FIG. 4 described above, it is possible to obtain a TFT (45) having a planar structure in which the gate, source and drain electrodes can be led out from the same side of the semiconductor layer. However, an example of obtaining a planar TFT having a self-aligned gate structure similarly to the inverted staggered TFT of FIG. 1 will be described with reference to FIG. In this case, as shown in FIGS. 6A to 6G, FIG.
After the same steps as those described with reference to G, a gate insulating film (43) such as SiO ₂ is formed to a thickness of about 1000 ° by a CVD method as shown in FIG. And so on.

Next, as shown in FIG. 6I, a light-transmitting conductive film (46), for example, an indium-tin composite oxide film is deposited on the gate insulating film (43), and a lower layer is formed on the light-transmitting conductive film (46). A photoresist layer (47) is deposited directly on the gate electrode (32). The photoresist layer (47) is formed by applying a photoresist on the entire surface of the light-transmitting conductive film (46), and thereafter, from the back surface side of the base (31), forming a gate electrode (32) of this lower layer.
Is used as an exposure mask to irradiate the photoresist layer (47) with light Ls for exposure over the entire surface, and then perform a development process to leave a pattern on the resist layer (47) immediately above the underlying gate electrode (32). I do.

Thereafter, the light-transmitting conductive film (46) is etched using the resist layer (47) as an etching resist to form a sixth layer.
This is used as an upper gate electrode (44) as shown in FIG.

Thereafter, as shown in FIG. 6K, an electrode window is formed on the source and drain regions (24) and (25) with respect to the gate insulating layer (43), or the entire thickness is not shown but required. An insulating layer, for example, SiO ₂ is formed by a CVD method or the like, and the source and drain regions (24) are formed over the entire thickness of the insulating layer and the gate insulating layer (43)
On (25), the source and drain electrodes are opened.

Then, the source and drain electrodes (27) and (28) of, for example, an Al conductive film are formed on the source and drain regions (24) and (25) through the source and drain electrode windows, respectively.

In this manner, the upper gate electrode (44), the source and drain electrodes (2
7) and (28) are derived, and a planar TFT (48) having a self-aligned gate structure can be obtained.

FIG. 7 shows an example in which laser light irradiation is performed from the substrate side. In this example, as shown in FIG. 7A, a substrate (31) such as a glass plate is prepared, and an amorphous semiconductor layer (21) made of, for example, a-Si: H is entirely formed on the substrate (31). thickness
200-500CVD formed by plasma CVD method etc., T
The amorphous semiconductor layer (21) is formed into an island shape by performing patterning for selectively etching other portions except for portions where FTs are to be formed.

Next, as shown in FIG. 7B, 10
A gate insulating layer (33) made of, for example, SiO ₂ having a thickness of about 00 ° is formed by a CVD method or the like.
l Deposit the constituent layer of the gate electrode (44) over the entire surface.

As shown in FIG. 7C, a photoresist layer (34) is formed on the entire surface of the amorphous semiconductor layer (21) by applying, patterning, and developing a photoresist layer (34) on the final gate portion.

As shown in FIG. 7D, the constituent layer of the gate electrode (44) and the gate insulating film (33) are sequentially etched using the photoresist layer (34) as a mask to form a gate portion.

Next, for example, by plasma CVD to a thickness of about 50 °, using a gas pH ₃ containing impurity phosphorus P and a source gas SiH ₄ containing silicon in the same manner as described above at 100 ° C. so as not to attack the resist layer (34). An impurity-containing layer (22) is deposited at about the temperature.

Next, as shown in FIG. 7E, the resist layer (34) is removed, and then a photoresist layer (74) is further applied over the entire surface, and an island-shaped amorphous semiconductor is formed from the back surface of the substrate (31). The entire surface is exposed to exposure light L with an exposure intensity such that the layer (21) is used as an exposure mask.
Exposure processing is applied to 4), and development processing is performed, and the photoresist layer (74) in the other portion is removed except for the portion immediately above the island-shaped amorphous semiconductor layer (21).

Next, using the photoresist layer (74) as an etching mask, the impurity-containing layer (22) on the amorphous semiconductor layer (21) is used.
The other portion of the impurity-containing layer (22) is removed by etching while leaving.

Next, an annealing light beam L such as a pulse excimer laser beam is applied with a required power from the back side of the substrate (31) to polycrystallize the amorphous semiconductor layer (21), thereby forming a polycrystalline semiconductor layer (23). And at the same time, diffusion of impurities from the impurity-containing layer (22) into the polycrystalline semiconductor layer (23) is performed to form the source and drain regions (25) and (26).

Next, for example, an insulating layer (73) of SiO ₂ or the like is entirely formed by a CVD method or the like, and an electrode window is formed on the source and drain regions (24) and (25) with respect to the insulating layer (73). The source and drain electrodes (27) and (28) are formed by performing the entire vapor deposition and selective removal of a metal layer such as Al to form the source and drain regions (24) of the polycrystalline semiconductor layer (23). A planar type TFT (7) having a self-aligned gate structure intended to be used as a channel forming region (26) with a high-resistance region where no impurity is introduced between (25) and (25).
5) get

However, in the example of FIG. 7, since the laser beam is irradiated through the substrate 31, it is necessary to select a substrate material so as not to affect a sufficient annealing process or the like due to a problem of absorption of the laser beam by the substrate. Will be needed.

FIG. 8 shows the measurement results of the I _D -I _G characteristics of the TFT (75) thus obtained, which showed excellent transistor characteristics.

In the above-described example, the formation of the source and drain regions (24) and (25) is performed by using the impurity-containing layer (22).
In some cases, the source and drain regions were formed by ion implantation, followed by annealing for polycrystallization of the amorphous semiconductor layer (21) and ion implantation. The activation treatment of the impurity ions may be performed at the same time.

Further, in the above-described example, the amorphous semiconductor layer (21) is crystallized by annealing by light beam irradiation to form the polycrystalline semiconductor layer (23). The present invention can also be applied to the case where the polycrystalline semiconductor layer (23) is formed by recrystallization by beam annealing and crystal growth.

H. Effects of the Invention As described above, according to the method of the present invention, the crystallization of the amorphous semiconductor layer (21) or the recrystallization of the fine polycrystalline layer and the impurity Diffusion or activation of implanted impurity ions can be performed at the same time, so that the number of manufacturing steps can be simplified, and the laser light (annealing light) irradiation can be performed before forming the gate portion or with the gate layer. Since the laser irradiation is performed from the opposite side, that is, the side where the protrusion is hardly shown, the diffusion effect of impurities due to lack of laser irradiation on the source and drain sides near the gate due to the interference effect due to the protrusion of the gate, that is, In addition, it is possible to avoid deterioration of characteristics, instability and reliability due to insufficient introduction of impurities or insufficient activation thereof.

[Brief description of the drawings]

FIG. 1 is a process diagram of an example of the manufacturing method of the present invention, FIG. 2 is a measurement curve diagram showing the relationship between the laser irradiation energy of the silicon layer and the specific resistance, and FIG. 3 is the _ID- V of the transistor obtained in FIG. _G
Characteristic curves, Figure 4 is a process diagram of another embodiment of the present invention production process, Fig. 5 I _D -V _G characteristic diagram of a transistor obtained by the method described in FIG. 4, FIG. 6 is present further process diagram of another embodiment of the invention the manufacturing method, FIG. 7 is a process view of the manufacturing method to be compared with the present invention, I _D -V _G characteristic diagram of the transistor 8 Figure obtained in FIG. 7, the FIG. 9 is a process chart of the conventional method. (31) is a substrate, (23) is a polycrystalline semiconductor layer, (22) is an impurity-containing layer, (23) is a gate insulating film, (32) and (44) are gate electrodes, (24) and (25) are sources. And drain regions, (27) and (28) are source and drain electrodes.

 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Setsuo Usui 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (56) References JP-A-61-295625 (JP, A) JP-A Sho 62-32653 (JP, A) JP-A-62-2531 (JP, A)

Claims (5)

(57) [Claims] A method of manufacturing a thin film transistor having a light beam annealing step of performing at least one of crystallization of an amorphous semiconductor layer and recrystallization of a polycrystalline semiconductor layer, comprising the steps of: forming a gate electrode having a required pattern on a substrate; Forming a gate insulating layer and a semiconductor layer of at least one of an amorphous semiconductor layer and a polycrystalline semiconductor layer on the gate insulating layer, and corresponding to the gate electrode on the semiconductor layer. Forming an impurity-containing layer over the semiconductor layer and the mask; removing the impurity-containing layer on the mask together with the mask; By irradiating a light beam from above the side having the semiconductor layer, the semiconductor layer and the impurity-containing layer are crystallized or Crystallization The method of manufacturing a thin film transistor which is characterized in that a step of forming a source region, a drain region and a channel region. 2. The method according to claim 1, further comprising, after the step of irradiating the light beam, a step of forming a second gate insulating layer and a second gate electrode covering the source region, the drain region and the channel region. The method for manufacturing a thin film transistor according to claim 1. 3. The thin film transistor according to claim 1, wherein the mask is formed by forming a resist layer on the semiconductor layer, and then exposing and developing the back surface of the substrate using the gate electrode as a mask. Manufacturing method. 4. The method according to claim 1, wherein the light beam is a pulsed excimer laser. 5. The method according to claim 1, wherein the semiconductor layer is made of silicon.