JP2732326B2 - Method and apparatus for calculating path delay of logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for calculating a path delay of a logic circuit, and more particularly, to a path calculation between any two points in a logic circuit in which individual gate delays and net delays are calculated. The present invention relates to a calculation method and a calculation device for performing the calculation.

[0002]

2. Description of the Related Art In general, when a signal of "up" or "down" is inputted to an input terminal of a gate, a gate delay is generated until a waveform of "up" or "down" is observed at an output terminal of the gate. With delay, up → up, up →
down, down → down and down → up 4
There are different types of delays.

A net delay is generated when a signal "up" or "down" is input to the input terminal of the net.
The delay until the waveform of “up” or “down” is observed at the output end of the net. Up → up and down
→ There are two types of delay, down. The path delay is obtained by integrating these delays between any two points in the logic circuit so that no inconsistency occurs in the propagation of the waveform.

[0004] For example, as shown in FIG.
Conventionally, in the circuit in which the gate 1 and the other gate 12 are connected by the net 13, the input terminal of the NOT gate 11 is A, the output terminal of the NOT gate 11 is B, and the input terminal of the other gate 12 is C.
At each point, storage areas 14, 15, and 16 for up and down delay values are provided at each point, and tables 16 and 17 for storing delay values of gates 11 and nets 13 known in advance are provided. The path delay is calculated by integrating the delay values. Here, the path delay at each point is, for example, the path delay at B is the path delay at A, that is, the value obtained by adding the gate delay value to the respective delay values U of UP and DN in the storage area 14. At this time, whether the signal at A is up or down, and the gate delay is whether the state of the signal is up → down or down
By adding the values stored in the table depending on whether the signal is up or not, a path delay value corresponding to the state in B, that is, whether the signal is up or down can be obtained in the storage area 15. . Similarly, the path delay value in C is obtained by adding a net delay value according to the state of the signal stored in the table 18 to the path delay value in B stored in the storage area 15 described above. Can be obtained. By continuing such an operation from the start point to the end point, a path delay between any pins can be obtained.

Here, depending on the state of the circuit, as shown in FIG. 6, even if the start point 21 and the end point 22 are the same, a plurality of paths may exist depending on the signal propagation path.
In the example shown in FIG. 6, the value of the integrated delay at the end point is u
For each of p and down, there are two types: in such a case, depending on the purpose of calculating the path delay, whether the maximum value of the path delay is adopted (max mode), Either the minimum value is adopted or (min mode) is selected.

[0006]

By the way, in the above-described conventional path delay calculation method, the initial value of the path delay in the state (up or down) at the final destination, that is, the state of the signal is changed. whether it was up or down
Sometimes you need to know what was. Conventionally, in such a case, the path is traced back and the initial value is u
There is a problem in that it must be tracked whether it is p or down, which is complicated.

In addition, when a path is used as a library, for example, there is a problem that it is impossible to cope with a case where four types of delays must be defined for the gate delay based on the theory inside the bus. Therefore, the present invention provides a path delay calculation method and calculation method that can easily obtain an initial value when calculating a path delay, can use a path as a library, and can reduce the calculation time. It is intended to provide a device.

[0008]

According to the present invention, a first means for solving the above-mentioned problems relates to a calculation method,
As shown in FIG. 1, when calculating a path delay from a start point to an end point between two predetermined points of a logic circuit, a point of interest determined in advance as a preceding stage delay value which is a delay value before the point of interest. In the method of calculating the path delay of a logic circuit that performs the operation from the start point to the end point by calculating the integrated delay value that is the delay value from the start point to the target point by adding the target point delay value that is the delay value of When an up is input to the input of the I path, u is output to the output of the path.
The delay value (UU) when p is observed, the delay value (UD) when down is observed at the output of the path when up is input to the input of the II path, and the do value at the input of the III path
The delay value (DU) when up is observed in the path output when wn is input, and the delay value (UU) when down is observed in the path output when down is input to the input of the IV path. It is to calculate with four kinds of values.

Further, in the present invention, a second means for solving the above-mentioned problem relates to a computing device, and as shown in FIG. A calculation device for calculating a path delay, comprising: a pre-stage table 1 for storing a pre-stage delay value which is a delay value up to a stage prior to a point of interest; and a point-of-interest delay value which is a delay value of a point of interest obtained in advance. A point-of-interest table 2, an addition means 3 for adding the value stored in the preceding table and the value of the point-of-interest table, and an accumulation table 4 for storing the added delay value. In an apparatus for calculating a path delay of a logic circuit that calculates an integrated delay value which is a delay value to a point of interest and performs this operation from a start point to an end point, a pre-stage table 1, a point-of-interest table 2, and a product In Table 4, a delay value (UU) when an up is observed in the output of the path when up is input to the input of the I path, and a down is observed in the output of the path when up is input to the input of the II path, respectively. Value when the down is input to the input of the III path, the delay value when the up is observed in the output of the path (DU), and the output of the path when the input is down to the input of the IV path The delay value when the down is observed (U
U), an area for storing the four types of delay values is provided.

[0010]

According to the first and second means of the present invention, as shown in FIG. 1, all the signals input to UU and UD of the above-mentioned integration table are output from UU and UD of the preceding table. ing. All signals input to DU and DD in the integration table are output from DU and DD in the preceding table.

Therefore, no matter how many times such a method is applied, UU, UU
Since the path delay stored in D uses the path delay stored in UU and UD of the first-stage preceding table as the initial value, the initial value of the delay can be known without particularly tracing back. In addition, since the state of the delay of all paths can be stored, even if it is necessary to define four types of delays according to the logic inside the path, such as a gate delay, the path can be stored as a library. It can be used.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a method and apparatus for calculating a path delay of a logic circuit according to the present invention.
In this embodiment, the path delay calculation device is realized by executing a path delay calculation method on a computer. In such a case, each table implements the apparatus by executing a program stored in advance using a storage device of the computer and a calculation function of the computer as an adding unit.

FIGS. 2 to 4 show an embodiment of a path delay calculating method according to the present invention. FIG. 2 shows a calculation example of the path delay according to the embodiment of the path delay calculation method of the logic circuit according to the present invention. This table shows delay data from an input pin to an output pin of each gate, delay data of a net connecting them, and a logic circuit having link data indicating the connection relationship between them.

In this example, the logic circuit is an OR gate 31, E
An OR gate 32 and a NAND gate 33 are provided, and nets 34, 35, 36, and 37 connecting between these gates 31, 32, 33 and the pin A and the output pin are provided.
It has. Then, delay tables 41, 42, 43, 44, 45, and 4 as point of interest tables storing net and gate delay values corresponding to these circuits.
6, 47 are provided. Here, in the present embodiment, these delay tables 41, 42, 43, 44, 4
5, 46 and 47 are four delay storage areas (1), (2), (3),
(4), each of which is directed downward from above in FIG.
up → up, (2) up → down, (3) down → do
wn and (4) the delay time from down to up.

In this example, pins A and Z are
An integrated path delay table 51 in which an integrated path delay to the corresponding pin is stored at an input terminal and an output terminal of each gate.
To 58 are provided. These accumulated path delay tables also have four storage areas I, II, II, respectively.
A delay value (UU) having I, IV, and from the top to the bottom in the figure like the path delay table described above, when up is input to the input of the I path and up is observed in the output of the path, A delay value (UD) when a down is observed in the output of the path when up is input to the input of the II path,
Delay value (DU) when up is observed in the output of the path when down is input to the input of the III path, and delay value when down is observed in the output of the path when down is input to the input of the IV path (UU) is integrated.

At this time, each accumulation path delay table is used as a preceding table or as an accumulation table in each stage. In this example, the value in the maximum time (max) mode is shown.
Next, a procedure for tracing a path when A is given as a start pin and obtaining a path delay from A to Z to the pin Z in FIG. 2 will be described.

FIG. 3 is a flowchart showing the method of calculating the path delay of the logic circuit and the operation of the apparatus according to the present embodiment. In this embodiment, the following abbreviations are used. TB1: Stack table of processing target pins N1: Counter of TB1 TBA: Storage table of arrival pin (end pin) NB: Counter of TBA CRX: Pin of interest TB2: Table for stacking the next pin connected to the pin of interest N2 : Counter of TB2 OLD: Delay to target pin BTD: Section delay of net or gate TMD: Delay at next-stage pin First, an initial value is set (ST1). In this case, since the start pin is A, 1 is set to the counter N1 of TB1. Also, 0 is set to N2 and NA.

Next, it is determined whether N1 is larger than 0, and if N1 is smaller than 0, the process is terminated (ST2). In this step, when the integration of the path delay is completed, N1
Is set to 0 and the calculation is terminated. .
Since N1 is now set to 1 as an initial value, the process proceeds to the next step. Hereinafter, steps 3 to 9 are repeated from X to 1 specified by X (ST3).

TB1 [X] is substituted for the pin of interest CRX (ST4). If there is a next-stage pin for CRX, the process proceeds to step 6 (ST5). The NB value is updated in order to calculate the path delay of the system, and the current CRX value is stored in the TBA as the path delay (ST11). Further, it is assumed that steps 7 to 9 are repeated for the number of pins in the next stage with respect to the target pin (ST6), the delay value at the target pin is substituted for OLD, and the section delay to the next stage is set to BTD. (ST7). Then, a calculation to which the present invention is applied is performed (ST8).

FIG. 4 shows a detailed flowchart of step 8. To select the specified calculation mode, that is, the path delay that requires the longest time,
X, when selecting a path delay requiring the shortest time, the process proceeds to MIN (ST81). To find the longest time, OLD [1] + BTD [1] and TMD [1]
The larger of LD [2] + BTD [3] is substituted.
Here, TMD [1] corresponds to I (UU) of the integration delay shown in FIG. 1, and similarly, OLD [1] corresponds to I (UU) of the preceding stage, and BTD [1] corresponds to the delay of the point of interest. (1) corresponds to u → u. Similarly, [2],
[3] and [4] are II or (2), III or (3), IV
Or, it corresponds to (4).

Then, similarly, OLD is added to TMD [2].
The larger of [1] + BTD [2] and OLD [2] + BTD [4] is set to OLD [3] + BTD in TMD [3].
The larger of [1] and OLD [4] + BTD [3] is assigned to TMD [4] as OLD [3] + BTD [2] and OLD
[4] + BTD [4], whichever is larger, is substituted. Thereby, the integrated delay value that is the maximum value can be obtained (ST82).

On the other hand, when obtaining the minimum time, the smaller one of the above values can be obtained as the integrated delay value (ST83). Referring back to FIG. 3, N2 is updated and T
B2 is the next stage pin (ST9), the value of N2 is N1,
Substitute the value of TB2 for TB1 and set the value of N2 to 0.
(ST10), and returns to step 2.

As a result, the path delay values are successively stored in the four areas (1) to (4) of the integrated path delay tables 52 to 58 shown in FIG. Therefore, according to the present embodiment, the value of the path delay can be calculated quickly, and the values of the storage areas (1) and (2) of the integrated path delay table 58 storing the delay value of the pin Z are The occurrence of the signal due to the input of the up signal to the pin A, and the occurrence of the value of the storage areas (3) and (4) due to the input of the down signal to the pin A can be performed without performing path tracing or the like. Recognize.

[0024]

As described above, according to the present invention,
The calculation method and apparatus of the path delay of the logic circuit are as follows. The calculation of the integrated path delay in each path is performed as up → up, up →
down, down → down and down → up 4
Therefore, the path delays stored in UU and UD of the last-stage integration table are equal to those of the first-stage preceding table.
Since the path delays stored in U and UD are used as the initial values, the initial values of the delays can be known without traceback, and the delay states of all paths can be stored. Therefore, even in the case where four kinds of delays need to be defined by the logic inside the path, such as a gate delay, the path can be used as a library, and the calculation for designing the logic circuit can be performed. This has the effect that it can be performed quickly.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a diagram illustrating a calculation example of a path delay according to a path delay calculation method according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating an operation of a path delay calculation method according to the embodiment.

FIG. 4 is a flowchart showing call CA in the flowchart shown in FIG. 3;
It is a partial flowchart of LX.

FIG. 5 is a diagram showing a conventional path delay calculation method.

FIG. 6 is a diagram showing a conventional path delay calculation method.

[Description of Signs] 1 Previous stage table 2 Point of interest table 3 Addition means 4 Integration table

Claims (2)

(57) [Claims] When calculating a path delay from a start point to an end point between two predetermined points of a logic circuit, a delay of a target point which is obtained in advance as a preceding stage delay value which is a delay value before a target point is calculated. In the calculation method of the path delay of the logic circuit that performs the operation from the start point to the end point by calculating the integrated delay value that is the delay value from the start point to the target point by adding the target point delay value that is The delay value (UU) when the up is observed in the output of the path when up is input to the input of the I path and the dow is output in the output of the path when up is input to the input of the II path, respectively.
Delay value when n is observed (UD), when down is input to the input of the III path Delay value when the up is observed at the output of the path (DU), When down is input to the input of the IV path D for path output
A path delay calculation method for a logic circuit, wherein a delay value (OU) when own is observed is obtained and calculated using the following four values. 2. A calculation device for calculating a path delay from a start point to an end point between two predetermined points of a logic circuit,
A pre-stage table (1) for storing a pre-stage delay value which is a delay value up to the pre-stage of the point of interest, and a point-of-interest table (2) for storing a point of interest delay value which is a delay value of the point of interest obtained in advance. An addition means (3) for adding the value stored in the preceding table and the value in the point-of-interest table, and an integration table (4) for storing the added delay value, from the starting point to the point of interest. In the apparatus for calculating a path delay of a logic circuit that calculates the integrated delay value, which is the delay value of the above, and performs this operation from the start point to the end point, the preceding table (1), the point-of-interest table (2), and the integration table (4) A delay value (UU) when an up is observed in the output of the path when an up is input to the input of the I path, and a dow is output in the output of the path when an up is input to the input of the II path
Delay value when n is observed (UD), when down is input to the input of the III path Delay value when the up is observed at the output of the path (DU), When down is input to the input of the IV path D for path output
An apparatus for calculating a path delay of a logic circuit, wherein an area for storing four kinds of delay values, ie, a delay value (UU) when an own is observed, is provided.