JP2732070B2 - Writing method for nonvolatile semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a writing method for an electrically writable nonvolatile semiconductor memory device.

[Conventional technology]

Figure 3 shows the 1987 IEEE International Solid State Circuits Conference (International So
lid State Circuits Conference) Digest (pages 76 to 77) is an operation explanatory diagram showing an equivalent circuit of a memory cell in a conventional nonvolatile semiconductor device and a voltage value to be applied to each terminal when erasing and writing. 4 Figure shows a memory transistor having a third is a sectional view of a memory transistor used in a nonvolatile semiconductor device shown in FIG, any figure Q ₅ to Q ₈ are floating (floating) gate. Each memory transistor Q ₅ to Q ₈ are substantially the same, the fourth drain (diffusion) at a predetermined interval on the surface as shown in FIG region 21, the source (diffusion) on the semiconductor substrate 23 formed with region 22 A control gate 25 and a floating gate 26 are formed with an oxide film 24 interposed therebetween, and a control gate electrode 27 is formed on the control gate 25, and a drain electrode 28 is formed on the drain region 21.
And a source electrode 29 is connected to the source region 22.

The control gate 25 is disposed between the drain region 21 and the source region 22 with one end facing the drain region 22 and the other end positioned near the source region 22. Is disposed near the drain region 21 between the drain region 21 and the source region 22 with one end facing the drain region 21, and applies a predetermined high voltage between the control gate 25 and the drain region 21. When applied, the floating gate 26
On the other hand, charges (electrons) can be injected and accumulated by hot electron injection from the drain region 21, or charges (electrons) can be drawn out of the drain region 21 by a tunnel phenomenon.

Thus the transistors Q ₅ to Q ₈ constructed are arranged in a matrix as shown in FIG. 1, the row direction is arranged transistors Q _5, Q ₇ gate electrode of the transistor
The gate electrodes of Q ₆ and Q ₈ are connected to word lines 18 and 19, respectively.
The source electrode of the transistor Q _5, Q _7, transistor
The source electrodes of Q ₆ and Q ₈ are connected to the source line 17 respectively, and the transistors Q ₅ and Q ₆ ,
The drain electrodes of Q ₇ and Q ₈ are connected to bit lines 15 and 16, respectively.

Such a conventional writing method for a non-volatile semiconductor device firstly starts with all memory cells, that is, memory transistors.
Q _{5 to} Q _{8 are} erased, in other words, a state of logic “1” is obtained by extracting electrons from each floating gate, and then the selected memory cell is programmed, in other words, electrons are applied to the floating gate of the memory transistor. Is made into a state of logic "0" by injection and accumulation.

Specifically described the case where the memory transistor Q ₇ next selected perform writing.

(Erase operation) First, as shown in FIG. 3, a high voltage V is applied to all the bit lines 15 and 16.
_This is _performed by applying _pp2 and applying 0V to all the word lines 18 and 19.

As a result, a high electric field is generated between the floating gate 26 and the drain region 21 shown in FIG. 4, and the charges, ie, electrons, stored in the floating gate 26 are drawn out to the drain region 21 by the tunnel phenomenon through the thin oxide film 24a. .

The floating gate 26 of each memory transistor Q ₅ to Q ₈ becomes a depletion state of the electronic, the threshold voltage of the memory transistor Q ₅ to Q ₈ as viewed from the control gate 25 side becomes lower than before the erase operation, the erase this state It is called state and logic "1".

(Program operation) bit line connected to the drain region of the memory transistor Q ₇ to be subjected to writing, that is, the selected high voltage V _pp2 to the bit line 16 are also 0V to the bit line 15 of the non-selected, further memory transistor Q ₇ A high voltage V _pp2 is applied to a word line connected to the control gates, i.e., a selected word line 18, 0 V to an unselected word line 19, and 0 V to a common source line 17.

This becomes the control gate and the drain region and the respective bit lines 16 of the memory transistor Q _7, the high voltage V _pp2 together through word line 18 is applied, in contact in the memory transistor Q _7, the drain shown in Figure 4 High energy electrons (hot electrons) are generated near the region 21, accelerated by the high voltage V _pp2 applied to the control gate 25, and injected into the floating gate 26.

Surrounding the floating gate 26 is surrounded by the oxide film, the electron becomes accumulation state, the threshold voltage of the memory transistor Q ₇ Looking at this state from the control gate 25 side becomes higher than that before the program operation. This state is called a program state and has a logic “0”.

Such an electrically erasable and programmable nonvolatile semiconductor memory device (EEPROM) does not require the use of ultraviolet light or the like for erasing unlike an EPROM, and can be electrically erased while mounted on a board. Since the cell can be composed of one transistor, there is an advantage that the chip area can be reduced.

[Problems to be solved by the invention]

By the way, in the conventional method as described above, since the erasing operation is performed collectively for all the memory cells, there has been a problem that page-based rewriting cannot be performed.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a writing method of a nonvolatile semiconductor memory device capable of performing page-mode rewriting, that is, so-called page mode writing.

[Means for solving the problem]

A writing method for a nonvolatile semiconductor memory device according to the present invention is a writing method for a nonvolatile semiconductor memory device in which a plurality of memory transistors each having a floating gate capable of electrically injecting and releasing electric charges are arranged in a matrix. At the time of writing, a predetermined voltage is applied to the bit line connecting the drain region of the column including the selected memory transistor, and the column of the non-selected memory transistor is connected to the bit line connecting the drain region of the column of the unselected memory transistor. A voltage intermediate between the voltage of the word line connecting the control gates and the zero voltage is applied, and the word line connecting the control gates of the column including the selected memory transistor is applied with the zero voltage, and the column of the non-selected memory transistors is applied. The word line connecting the control gates of the memory transistors has the voltage of the bit line connecting the drain regions of the columns of the non-selected memory transistors and the predetermined voltage. And applying an intermediate voltage between the voltage.

[Action]

According to the present invention, by applying an appropriate voltage to the non-selected memory transistors, it is possible to enhance the write blocking effect and obtain a stable operation.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings showing the embodiments.

FIG. 1 is an explanatory diagram showing an equivalent circuit of a memory cell in a nonvolatile semiconductor memory device using the method of the present invention and a voltage value for each terminal at the time of an erase and program operation, and FIG. 2 is a sectional structural view of a memory transistor. , Q _{1 to} Q ₄ denote memory transistors, 1 and 2 denote bit lines, 3 and 4 denote word lines, and 5 and 6 denote source lines.

All of the memory transistors Q _{1 to} Q ₄ are substantially the same, and as shown in FIG. 2, the surface of the semiconductor substrate 12 on which the drain (diffusion) region 10 and the source (diffusion) region 11 are formed at required intervals. A control gate 14 and a floating gate 15 are provided via an oxide film 13, and the control gate 14 is provided with the control gate electrode 7,
The drain electrode 8 is connected to the drain region 10, and the source electrode 9 is connected to the source region 11.

The control gate 14 is provided between the drain region 10 and the source region 11, with one end facing the drain region 10 and the other end facing the vicinity of the source region 11. The floating gate 15 is disposed between the drain region 10 and the source region 11 near the drain region 10 and has one end facing the drain region 10. The floating gate 15 has a protruding portion protruding toward the drain region 10 at a part of the portion facing the drain region 10 and facing the drain region 10 with a thin oxide film 13a interposed therebetween.

Such memory transistors Q ₁ to Q ₄ are disposed in a matrix as shown in FIG. 1 (in FIG. 1 shows the case of providing the two rows, the column direction), the memory transistor Q _1,
Q ₃ and the memory transistors Q ₂ and Q ₄ are arranged in the row direction, and the memory transistors Q ₁ and Q ₂ and the memory transistors Q ₃ and Q ₄ are arranged in the column direction.

The gate electrodes of the memory transistors Q ₁ and Q ₃ arranged in the row direction and the gate electrodes of the memory transistors Q ₂ and Q ₄ are connected to the word lines 3 and 4, respectively, and the memory transistors Q ₁ and Q ₁ arranged in the column direction. Q _2, connected to the memory transistor Q _3, the drain electrode are each bit lines 1 and 2 of Q _4, further memory transistor Q _1, Q _2, in the memory transistor Q _3, a source electrode are each source lines 5 and 6 of the Q ₄ Have been.

Thus, writing to such a nonvolatile semiconductor memory device involves an external write cycle of writing one page of data to an internal latch and an internal write cycle of actually writing data to a memory cell in accordance with the data written to the latch. The internal write cycle is further divided into an erase cycle and a program cycle. In the erase cycle, first, all the memory cells for one page to be programmed are erased, that is, logic "1" is written. Then, in the program cycle, a program, that is, logic "0" is written in accordance with the latch data.

Hereinafter, the internal cycle of the page mode write will be specifically described.

(Erase Operation) The high voltage _Vpp is applied to the selected word line 3 corresponding to the page to be written in the page mode, 0 V is applied to the unselected word line 4, and 0 V is applied to all the bit lines 1 and 2, respectively. Source line
Steps 5 and 6 are performed by floating.

As a result, a high voltage is applied between the control gate and the drain region of each of the memory transistors Q ₁ and Q ₃ in which the control gate is connected to the word line 3, and a high electric field is generated between the floating gate and the drain region. Electrons are injected toward the floating gate through a thin oxide film 13a shown in FIG. 2 by a tunnel phenomenon, and the floating gate is in a state where electrons are accumulated.

In this state, the memory transistor is viewed from the control gate.
The threshold voltages of Q ₁ and Q ₃ are higher than before the erase operation,
In other words, a state where logic "1" is written is obtained.

In the memory transistors Q ₂ and Q ₄ in which the control gate is connected to the word line 4, 0 V is applied to both the word line 4 and the bit lines 1 and 2. There is no potential difference, there is no change in each threshold voltage, and no erasing is performed.

(Program operation) Memory transistor with control gate connected to word line 3
Q _1, if shown for the case of writing a logic "0" only to the transistor Q ₃ of the Q _3, first selected 0V to the word line 3, the word line 4 of the unselected _{V WI (= 2 / 3V pp} ) Is applied to the selected bit line 2 and the high voltage V _pp is applied to the selected bit line 1 and V _BI is applied to the unselected bit line 1
(= 1/3 V _pp ) by further floating the source lines 5 and 6.

This allows the control gate of the memory transistor Q ₃ is
At 0 V, a high voltage V _pp is applied to the drain region, a high electric field is generated between the floating gate and the drain region, and electrons are extracted from the floating gate through the thin oxide film 13a to the drain region by a tunnel phenomenon. Is depleted.

The threshold voltage of the memory transistor Q ₃ When in this state seen from the control gate is lower than the pre-program operation, a program state, i.e. a state in which a logic "0" is written.

Word lines in the other memory transistors Q _2, Q _{4 4}
Since the voltage V _WI to the gate electrode, and the voltage V _BI both the drain region through the bit lines 1 and 2, the voltage of V _pp is applied through, whereas in the memory transistors Q ₁ to the gate electrode through the word line 3 0V and bit line 1
Since _VBI is applied, a voltage difference of 1/3 _Vpp is applied between the control gate and the drain region.

Normally, the tunnel current between the control gate and the drain region in a memory transistor strongly depends on the strength of the electric field. When the electric field decreases by 1 MV / cm, the tunnel current density decreases by about one digit. In the memory transistors Q ₁ , Q ₂ , and Q _{4 of 1/3} V _pp , almost no tunnel current flows, and the change in the threshold voltage can be ignored. As a result, only the memory transistor Q ₃ is programmed.

〔The invention's effect〕

As described above, in the method of the present invention, at the time of writing, the bit line connecting the drain region of the column of the non-selected memory transistor is connected to the word line voltage and the zero voltage connecting the control gate of the column of the non-selected memory transistor. Between the voltage of the bit line connecting the drain region of the column of the non-selected memory transistors and the 0 voltage is applied to the word line connecting the control gates of the column of the non-selected memory transistors. Even if the source is common, the current flowing through the path of the selected bit line, the selected memory transistor, the source, and the unselected bit line is extremely large due to the relative relationship with the voltage value. It is small or does not flow at all, and the effect of preventing writing to non-selected memory cells is large, and stable operation can be expected.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an equivalent circuit of a memory cell in a semiconductor memory device used in the method of the present invention, and voltage values to respective terminals during erase and program operations. FIG. 2 is a sectional structural view of a memory transistor used in the method of the present invention. FIG. 3 is an explanatory view showing an equivalent circuit of a memory cell in a semiconductor memory device used in a conventional method and a voltage value to each terminal at the time of erase and program operations, and FIG. 4 is a memory also used in a conventional nonvolatile semiconductor memory device. FIG. 3 is a sectional structural view of a transistor. Q ₁ to Q ₄ ... memory transistors 1 ... bit lines, 3,4 ... word lines 5 and 6 ... source line In the drawings, the same reference numerals denote the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A method of writing data in a nonvolatile semiconductor memory device in which a plurality of memory transistors each having a floating gate capable of electrically injecting and discharging electric charges are arranged in a matrix. A predetermined voltage is applied to the bit line connecting the drain region of the column including the column, and the voltage of the word line connecting the control gate of the column of the non-selected memory transistor is applied to the bit line connecting the drain region of the column of the non-selected memory transistor. A voltage between 0 and 0 is applied. A voltage of 0 is applied to the word line connecting the control gates of the column including the selected memory transistor, and a voltage of 0 is applied to the word line connecting the control gates of the column of the unselected memory transistors. Applying an intermediate voltage between the voltage of the bit line connecting the drain regions of the columns of the unselected memory transistors and the predetermined voltage. Writing method for a nonvolatile semiconductor memory device according to symptoms.