JP2730051B2 - Data communication device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication device for performing data communication between first and second units which are close to each other in a non-contact manner by using an induction electromagnetic field.

(Prior art)

Conventionally, as shown in, for example, JP-A-62-63050, a data storage device for holding respective tool data is provided in a tool shank of a machine tool or the like, and data is serially transferred from the data input / output device to the data storage device. 2. Description of the Related Art There has been proposed a data transmission device that transmits and writes data or reads written content. In such a data transmission device, communication between the data input / output device and the data storage device is performed by using a fixed high-frequency signal and performing frequency shift keying (FSK) modulation on the signal.

[Problems to be solved by the invention]

However, according to such a conventional data transmission device, a PLL circuit and the like for demodulating an FSK signal are required in the data storage device and the data input / output device, so that much power consumption is required. In some cases, a data storage device rectifies an AC voltage induced from a data input / output device and uses it as a power source. At this time, if the power consumption is large, data communication cannot be performed unless the induced voltage is high. It has the disadvantage of being shorter. Further, when a battery is provided on the data storage device side, there is a disadvantage that the battery life is shortened. On the other hand, the applicant transmits a binary logical level signal from the input / output device by matching the resonance frequency of the data storage device and the input / output device, intermittently intermittently transmitting a signal of a fixed frequency at a fixed period, and changing the duty ratio. A data communication device that transmits a signal having an intermediate duty ratio during reception and transmits a signal from a data storage device to a data input / output device has been proposed (not disclosed). In this case, the logic signal is transmitted by changing the duty ratio of the intermittent transmission pulse from the data input / output device. However, even when the data input / output device is in the reception state, the logic signal is erroneously regarded as a signal of any logic level. There is a disadvantage in that if the data storage device receives the data and therefore matches the specific command, a malfunction may occur.

The present invention has been made in view of such a problem of the data communication device, and transmits a transmission signal to each other by changing the duty ratio using a carrier of a constant frequency, and also realizes a data input / output device. It is a technical object to enable data transmission without causing the above malfunction even during reception.

[Structure and effect of the invention]

(Means for Solving the Problems) The present invention is a data communication device for performing half-duplex data transmission of serial data between a first unit and a second unit, wherein the first unit is a second unit. An oscillator that oscillates a signal of a constant frequency, having a first coil provided on a surface facing the data, and has first and second duty ratios corresponding to a transmission data signal during data transmission, Occasionally, a transmission pulse signal of a constant cycle having a third duty ratio between the first and second duty ratios is generated, and the oscillation is intermittently generated by applying the transmission pulse signal of the constant cycle to an oscillator. A first coil having a resonance frequency substantially equal to the oscillation frequency of the oscillator and having a second coil provided on a surface facing the second unit;
A receiving gate signal generating means for receiving a signal corresponding to the transmission pulse of the transmission pulse generating means and generating a reception gate signal having a timing when the oscillation of the oscillator is stopped, and a reception gate signal of the reception gate signal generating means , A detection circuit for detecting an electromagnetic induction signal obtained in the first resonance circuit while the signal is given, a sample and hold circuit for sampling the output of the detection circuit at a predetermined timing of the reception gate signal, and discriminating the hold signal of the sample and hold circuit The second unit is provided on a surface facing the first unit and having a resonance frequency substantially equal to the oscillation frequency of the oscillator of the first unit. A second resonance circuit including a third coil, a detection circuit for detecting a signal obtained by the second resonance circuit, and a detection output that is a predetermined threshold level. A second comparator that obtains a transmission pulse signal by discriminating a clock signal obtained by the second resonance circuit when receiving data from the first unit, counts the number of clocks, and counts the first and second clocks. When counting the first clock number between the clock numbers obtained at the time of transmission at the duty ratio of 3, and the second clock number between the clock numbers obtained at the time of transmission at the second and third duty ratios, Data demodulating means including counters each providing an output, and using one of the count outputs of the counter selected based on the demodulated signal to discriminate the output of the second comparator into a demodulated signal; and a second resonance circuit. And a switching element connected between the first unit and the ground.
Controlling the reverberation generated in the second resonance circuit by intermittently switching the switching element corresponding to the transmission data at the oscillation stop timing of the oscillator based on the transmission pulse signal of the third duty ratio obtained from the comparator And reverberation control means.

(Operation) According to the present invention having such characteristics, the first unit intermittently oscillates the oscillation of the oscillator of a constant frequency at a constant period, and changes the duty ratio at the time of transmission to convert the binary signal into the second signal. To the unit side. The second unit detects this signal, discriminates the clock obtained in the second resonance circuit by the data demodulation means, counts the number of clocks, and corresponds to the first and third duty ratios and the second and third duty ratios. A demodulated signal is obtained by counting the number of clocks in the middle of the number of clocks. Then, based on the demodulated signal, the threshold is switched to the first or second clock number, and demodulation is performed with hysteresis. And the first
When the unit is in the receiving state, the oscillation of the oscillator is interrupted by the first unit at the third duty ratio between the first and second duty ratios. When data is transmitted from the second unit to the first unit, the switching provided in the resonance circuit of the second unit when the oscillation of the oscillator is stopped at a constant third duty ratio from the first unit. The reverberation obtained in the resonance circuit of the first unit is controlled by intermittently switching the elements according to the transmission data signal. The first unit generates a reception gate signal within the oscillation stop period based on the transmission pulse signal supplied to the oscillator, and extracts only the reverberation by the reception gate signal to detect the reverberation. Then, the transmission signal obtained from the second unit is demodulated by sampling the reception gate signal at a predetermined timing, applying the signal to a first comparator, and discriminating the signal by comparison with a predetermined threshold level or a previous signal level. I have to.

(Effects of the Invention) As described above, according to the present invention, the first and second electromagnetic couplings are utilized.
Half-duplex data transmission of serial data is performed between the second units. The data demodulation means of the second unit demodulates the pulse width by a digital comparator having hysteresis based on the clock signal discriminated from the output of the comparator. Therefore, when transmitting data from the first unit to the second unit,
Since the thresholds of the first and second clock numbers are exceeded, the signal can be demodulated. When the first unit changes to the receiving state and changes from the first or second duty ratio signal to the third duty ratio signal, the count value of the number of clocks generated by the third duty ratio signal Are the first and second
, The demodulated signal of the pulse width demodulation circuit does not fluctuate and is not erroneously interpreted as a command. Furthermore, when the power of the second unit is obtained from the first unit, the power consumption is small, so that the transmission distance can be lengthened. When data is transmitted from the second unit to the first unit, reverberation of a signal obtained from the first unit is controlled based on transmission data.
If the oscillation output given from the unit to the second unit is increased, the reverberation level can be increased accordingly. Therefore, the reverberation resonance signal obtained in the first unit also increases, so that the data transmission distance can be increased. Also, since the resonance circuits provided in the first and second units are made to substantially match the oscillation frequency of the oscillator, data transmission can be performed with high efficiency, and the SN ratio can be improved. The effect is also obtained.

[Explanation of Example]

(Configuration of Embodiment) FIG. 2 is a block diagram showing an overall configuration in which a data communication device according to an embodiment of the present invention is applied to an article identification system. In this figure, the data communication device has a write / read control unit 1 as a first unit and an ID unit 3 as a second unit attached to an article 2 or the like.
The write / read control unit 1 has first and second coils L1 and L2 at positions facing the ID unit 3, and the ID unit 3 also has third coils L3 at positions facing these coils. Have. The write / read control unit 1 is connected to, for example, a higher-order control device 4. The upper control device 4 performs writing /
After transmitting the transmission control signal (CT) to the read control unit 1, the transmission data SD is transmitted, and the reception data RD obtained from the write / read control unit 1 is read.

As shown in a detailed block diagram in FIG. 1, the write / read control unit 1 includes a clock generator 11 for generating a fixed clock signal, a time controller 12 for generating a timing signal based on the clock signal, and a transmission unit. A pulse generation circuit 13 is provided. The time controller 12 is a transmission control signal (CT) obtained from the upper control device 4
Is transmitted to the transmission pulse generation circuit 13 and the reception gate signal generation circuit 14, the host control device 4 sends the transmission data SD to the transmission pulse generation circuit 13 after giving the transmission control signal. send. The transmission pulse generation circuit 13 counts the clock of the clock generator 11 at a predetermined cycle at the timing when the reception switching signal is in the transmission state from the time controller 12, and performs the first and second duty ratios according to the transmission data SD at a fixed cycle. The output is given to the oscillator 15. The oscillator 15 oscillates at a constant frequency only when a transmission pulse signal is given from the transmission pulse generation circuit 13, and its oscillation output is supplied to a first coil L1 for transmission via an amplifier 16. Things. In this embodiment, the first duty ratio is 15 when the number of clocks of the clock generator 11 is 15.
As described above, the second duty ratio is 11 or less.

The write / read control unit 1 is provided with a second coil L2 for reception. A capacitor C1 is connected in parallel to the coil L2 to form a first resonance circuit 17 that resonates with the oscillation frequency of the oscillator 15, and an induced voltage obtained at both ends thereof is supplied to the amplifier 18. The amplifier 18 amplifies the induced voltage, and supplies its output to the detection circuit 20 via the analog switch 19. The reception gate signal generation circuit 14 generates a reception gate signal delayed by a predetermined time, for example, one clock from the fall of the transmission pulse when the transmission / reception switching signal provided by the time controller 12 is in the reception state. The reception gate signal is provided to the analog switch 19 as a gate signal. Clock generator 11
The reception gate signal of the reception gate signal generation circuit 14 is also given to the sampling signal generation circuit 21. The sampling signal generation circuit 21 supplies a predetermined timing of the reception gate signal, for example, a signal for one clock immediately before the end to the sample and hold circuit 22 as a sampling signal. The detection circuit 20 detects a signal obtained through the analog switch 19 to obtain an integrated signal or its envelope signal. The detection signal is supplied to the sample-and-hold circuit 22. The sample and hold circuit 22 holds an input signal based on a sampling signal, and its output is provided to a first comparator 23. The comparator 23 obtains a binary signal by discriminating a signal held by comparison with a predetermined threshold level or a previous signal, and an output thereof is given to the upper control device 4 as a reception signal RD.

As shown in FIG. 3, the ID unit 3 has a second resonance circuit 30 including a coil L3 and a capacitor C2 provided on a surface facing the write / read control unit 1, and induced voltages at both ends thereof. Is supplied to the detection circuit 31 and the diode bridge 32. The detection circuit 31 detects this signal, and its output is given to the second comparator 33. Further, the diode bridge 32 performs full-wave rectification of the induced voltage obtained in the resonance circuit 30 and supplies the voltage to the constant voltage circuit 34. The constant voltage circuit 34 smoothes the rectified voltage and supplies it to each block of the ID unit 3 as a constant voltage. A predetermined threshold level is set in the comparator 33, and the detection output is discriminated by the threshold. The output of the comparator 33 is supplied to a clock discrimination circuit 35, a pulse width demodulation circuit 36, and a memory control unit 37. The clock discrimination circuit 35 is connected to one end of the resonance circuit 30 and detects a clock having an oscillation frequency obtained by the resonance circuit 30 when a transmission pulse is given, and converts the clock signal into a pulse width demodulation circuit. Give to 36. The pulse width demodulation circuit 36 is a digital comparator that discriminates the count value of the clock signal obtained from the clock discrimination circuit 35 by a threshold having a hysteresis that changes based on the demodulated signal to be output. Given to 37. The memory controller 37 is connected to a memory 38 as a storage unit of the ID unit 3.

Since the signals obtained from the write / read control unit 1 are data and commands, the memory controller 37 writes the given data to the memory 38 based on this command and reads the data in the memory 38. Is controlled. The memory controller 37 has a comparator as a reference clock.
The output of 33 is given, and the read data is given to a reverberation control pulse generator 39. Reverberation control pulse generator
The reference numeral 39 designates the transmission data of the "L" level based on the transmission data which is read from the memory control unit 37 and transmitted to the write / read control unit 1 at a predetermined timing when the output of the comparator 33 becomes the "L" level. Sometimes, a reverberation control pulse having a predetermined width is generated. By the way, at both ends of the resonance circuit 30, the FET 40, which is a switching element,
41 is connected. The FETs 40 and 41 control both ends of the resonance circuit 30 to be grounded based on the reverberation control pulse of the reverberation control pulse generator 39. Here, the reverberation control pulse generator 39 and the FETs 40 and 41 which are switching elements for grounding both ends of the resonance circuit 30 constitute reverberation control means 42 for controlling the reverberation vibration of the resonance circuit 30.

Next, a detailed configuration of the pulse width demodulation circuit 36 of the present embodiment will be described with reference to FIG. Pulse width demodulation circuit 36
Is a counter 51 for counting the clock signal based on the output of the comparator 33, and T for detecting the rise and fall of the comparator 33.
Type flip-flops 52 and 53. Counter 51
Is reset when the comparator 33 rises, and counts the clock signal. A constant count value, for example, "12" or "14", which becomes the second or first clock number, is output by the gate circuit 54. , 55. The outputs of the gate circuits 54 and 55 are supplied to a set input terminal of an RS flip-flop 57 via an OR circuit 56. The Q output of flip-flop 57 is applied to D-type flip-flop 58, and the Q output is applied to D-type flip-flop 59. The Q output of the flip-flop 52 that detects the rise is supplied to the reset input terminal of the flip-flop 57 and the T input terminal of the flip-flop 59. Q of flip-flop 53 for detecting falling
The output is applied to the T input of flip-flop 58. The flip-flop 59 outputs a demodulated signal, and its Q output and output are supplied to the gate circuits 54 and 55, respectively, and the Q output is supplied to the memory controller 37 as a demodulated signal.

(Operation of Embodiment) Next, the operation of the embodiment will be described with reference to a time chart. First, when a signal is transmitted from the writing / reading control unit 1 to the ID unit 3, a transmission control signal CT is transmitted from the host control device 4 to the time controller 12. Then, the time controller 12 supplies a transmission switching signal to the transmission pulse generation circuit 13. After that, as shown in FIG.
(For example, “HLLH” as shown) is applied to the transmission pulse generation circuit 13. Then the transmission pulse generation circuit
13 The corresponding to the logical level of the transmitted data at a predetermined period T from the time t _1, t _3, t ₅ and t _6, as shown in FIG. 5 (b)
1. Generate a transmission pulse signal having a second duty ratio. In the present embodiment, the first duty ratio is set to 70%, and the second duty ratio is set to 30%. FIG. 5 (c)
The oscillation of the oscillator 15 is interrupted as shown in FIG. Therefore, when the ID unit 3 is close, the driving time of the oscillator 15, that is, times t _{1 to} t ₂ , t _{3 to} t ₄ , at both ends of the resonance circuit 30 as shown in FIG. , A signal having a constant amplitude is obtained, and then a signal attenuating is obtained. Since this signal is detected by the detection circuit 31 and compared at a predetermined threshold level, the same signal as the transmission pulse signal as shown in FIG. The signal is provided to the demodulation circuit 36. The clock signal is discriminated by the clock discriminating circuit 35 as shown in FIG.

FIG. 6 is a time chart showing the operation of the pulse width demodulation circuit 36. As shown in FIGS. 6 (a) to 6 (d), the flip-flop 57 is reset by the Starts counting at times t ₁ , t _3, .... Assuming that the demodulated output at this time is at the “H” level as shown in FIG.
As shown in FIGS. 11E and 11H, the flip-flop 57 is set via the gate circuit 54 and the OR circuit 56 at the count point "12". Further, the time when the comparison output of the comparator 33 is stopped.
The T input is applied to the flip-flop 58 at t ₂ and t _4, and the state of the flip-flop 57 at that time is read into the flip-flop 58. Then, the output of the flip-flop 58 is read into the flip-flop 59 and output by the next rising output of the comparator 33, so that the memory control is performed at a timing delayed by one cycle from the transmission data SD as shown in FIG. Part 37
Output the signal. Accordingly, when the output of the pulse width demodulation circuit 36 is at the "H" level, the output is switched to the "L" level when the count value of the counter 51 becomes "12" as a threshold as shown in FIG. That when the clock signal at time t ₃ ~t ₄ is, for example, "11" is a pulse, the comparator 33
Resets the flip-flop 57,
Flip-flop as shown in Figure 6 for down comparison output at time t ₄ until the count output of "12" is obtained stand (i)
58 is reset. Therefore it is possible to output at time t ₅ in the next cycle for outputting "L" level and the signal delayed one cycle in the same manner. When the output of the flip-flop 59 becomes "L" level, the gate circuit 54 is closed and the gate circuit 55 is opened, so that the threshold value is switched to the count value "14" as shown in FIG. And then as shown at time t ₁ ~t ₂ For example, the count value is output if exceeds "14" is never switched to "H". In this way, the pulse width demodulation circuit 36 can be realized using a digital comparator having hysteresis. Write /
Data is transmitted from the read control unit 1 to the ID unit 3. Unlike the FSK signal, since a signal of a constant frequency is only intermittent, the data transmission can be performed with high efficiency by keeping the resonance frequency of the resonance circuit 30 equal to the oscillation frequency of the oscillator 15. Also, if the output of the oscillator 15 of the write / read control unit 1 is increased,
Since the voltage level induced in the ID unit 3 increases,
The communication distance can be increased by the oscillation output.

Next, when data is transmitted from the ID unit 3 to the write / read control unit 1, first, the write / read control unit 1
The transmission / reception switching signal of the time controller 12 is switched to the reception state, and the transmission pulse generation circuit 13 outputs a third duty ratio between the first and second duty ratios as shown in FIG. A transmission pulse signal having a constant period T with a duty ratio of% is generated. In this case, the oscillator 15 is periodically interrupted, so that an oscillation signal as shown in FIG. 8B is transmitted to the ID unit 3 from the coil L1. Accordingly, the comparator 33 outputs a comparison signal having a duty of 50% as shown in FIGS. 6 (a) and 8 (c). At this time, if the number of clocks is within the range of 12 to 14,
When counting 12 after the rising of the comparison output of the comparator 33, the sixth
As shown in FIG. 9E, the counter 51 gives a count output of "12". At this time, if the output of the pulse width demodulation circuit 36 is "H" level, the threshold is "12".
The flip-flop 57 is set as shown in FIGS. 6 (e), (g) and (h). Then, the signal is transmitted to the flip-flop 58 at the falling times t ₉ , t _11, ... Of the comparison output. Then, times t ₁₀ and t _{12 at which the} comparison output rises again ...
Is transmitted to the flip-flop 59 to output a demodulated signal. Therefore, in this case, the "H" level is continued until the threshold value becomes less than "12", and 12 is the threshold value for digital comparison. Therefore, if the number of clocks in each cycle does not become 11 or less, the demodulated signal does not change, and there is no danger that the output will change despite the signal of 50% duty from the pulse width demodulation circuit 36. If the output of the pulse width demodulation circuit 36 is at the "L" level, the output will not be inverted unless the count value exceeds "14", so that the output will not change with respect to the comparison signal having a duty of 50%. Accordingly, the pulse width demodulation circuit 36 has a hysteresis characteristic as shown in FIG.
During the period of 14, the signal in the original state is maintained as it is. Therefore, the demodulation output does not fluctuate with a signal having a duty of 50%, and there is no fear that a meaningless signal is erroneously recognized as a received signal such as a command. And write again /
If the read control unit 1 enters the data transmission state to the ID unit 3 and receives an output with a duty of 30%, a clock signal with a threshold of 12 or less can be obtained.
Becomes the "L" level. Next, in order for the output to change to "H" level, a clock signal exceeding 14 pulses needs to be given.

FIG. 8 (d) shows an example of a signal in which the signal read from the memory control unit 37 is "HLHL", and this signal is given to the reverberation control pulse generator 39. The reverberation control pulse generator 39 outputs a reverberation control pulse having a predetermined width as shown in FIG. 8 (e) when the comparator 33 falls based on the logical level of this signal. This signal is applied to the FETs 40 and 41 and is interrupted. Thus, in FET40,41 off state, the attenuation signal to the resonant circuit 30 as shown at time t ₉ subsequent etc. Figure 8 (f) has occurred, at time t ₁₁ after turning on the FET40,41 Since both ends of the resonance circuit 30 are grounded, the ID unit 3
Resonance hardly occurs in the resonance circuit 30 of FIG. Meanwhile signal obtained in the resonant circuit 17 of the write / read control unit 1 is between the oscillator 15 time t ₈ ~t ₉ which is driven, t ₁₀ ~t ₁₁ ...... having constant high amplitude level, it Later time
At t _{9 to} t ₁₀ , t _{11 to} t ₁₂ , low-level reverberation remains according to the reverberation of the resonance circuit 30 of the ID unit 3. Then, as shown in FIG. 8 (h), a reception gate signal is generated by the reception gate signal generation circuit 14 at a fixed period shorter than the period in which the transmission pulse is turned off, and detection is performed via the analog switch 19 which is closed only during that period. The signal is transmitted to the circuit 20. Immediately before the fall, a sampling signal is applied to the sample and hold circuit 22 as shown in FIG. 8 (k). Therefore, since the output of the sample hold circuit 22 is discriminated from the threshold value by the comparator 23, a signal as shown in FIG. 8 (l), that is, a memory read signal similar to that of FIG. This is transmitted to the read / write control unit 1 with a delay of the transmission period T.

In the present embodiment, a rectifier circuit and a constant voltage circuit are provided in the ID unit 3 to serve as a power supply for the ID unit 3.
The transmission data SD supplied from the control device 4 is further subjected to Manchester encoding so that the average period of the transmission pulse becomes constant, and the signal subjected to Manchester encoding, that is, logic "H"
"HL" for level, "LH" for logical "L"
It is preferable to transmit the transmission data by giving the signal of (1) to the transmission pulse generation circuit 13 as transmission data.
In this case, the data transmission rate is halved compared to the case without Manchester encoding.However, the average value of the driving time of the oscillator 15 does not fluctuate with time, and an oscillation signal having a constant average value is given. 3 can perform data transmission without changing the DC voltage.

Further, in this embodiment, the oscillation signal of the resonance circuit is rectified and smoothed and supplied as power to each block. However, a battery may be provided in the ID unit to supply power to each block from this battery. Needless to say.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a write / read control unit of an article identification system according to an embodiment of the data communication device of the present invention, FIG. 2 is a block diagram showing the overall configuration thereof, and FIG. FIG. 4 is a circuit diagram showing a configuration of a pulse width demodulation circuit, FIG. 5 is a time chart showing waveforms of respective parts when data is transmitted from a write / read control unit to an ID unit, FIG. 6 is a time chart showing the operation of the reception inhibition circuit, FIG. 7 is a diagram showing the hysteresis characteristic of the pulse width demodulation circuit of the present embodiment, and FIG.
5 is a time chart showing waveforms of respective units when transmitting a signal from an ID unit to a write / read control unit. 1 ... Write / read control unit, 3 ... ID unit, 4
…… Control equipment, L1, L2, L3 …… Coil, 11 …… Clock generator, 12 …… Time controller, 13 …… Transmit pulse generation circuit, 14 …… Reception gate signal generation circuit, 15 …… Oscillator, 17 , 30 …… Resonant circuit, 19 …… Analog switch, 20,
31 ... Detector circuit, 22 ... Sample hold circuit, 23,33
…… Comparator, 35 …… Clock discrimination circuit, 36 …… Pulse width demodulation circuit, 37 …… Memory control unit, 38 …… Memory, 39 ……
Residual control pulse generator, 42 ... Reverberation control means, 51 ... Counter, 57-59 ... Flip-flop

Claims (1)

(57) [Claims] 1. A data communication apparatus for transmitting half-duplex data of serial data between a first unit and a second unit, wherein the first unit is provided on a surface facing the second unit. An oscillator having a first coil provided and oscillating a signal of a constant frequency; and a first and a second corresponding to a transmission data signal during data transmission.
And at the time of data reception, the first and second
Transmission pulse generating means for generating a fixed-period transmission pulse signal having a third duty ratio between the above-mentioned duty ratios, and applying the fixed-period transmission pulse signal to the oscillator to interrupt the oscillation, and the oscillator A first resonance circuit having a resonance frequency substantially equal to the oscillation frequency of the first unit and including a second coil provided on a surface facing the second unit; Receiving gate signal generating means for receiving a received signal and generating a receiving gate signal having a timing when the oscillation of the oscillator is stopped; and providing the first resonance circuit while the receiving gate signal of the receiving gate signal generating means is supplied. A detection circuit for detecting the obtained electromagnetic induction signal; and a sampler for sampling the output of the detection circuit at a predetermined timing of the reception gate signal. And a first comparator for discriminating a hold signal of the sample and hold circuit, wherein the second unit has a resonance substantially equal to an oscillation frequency of an oscillator of the first unit. A second resonance circuit having a frequency and including a third coil provided on a surface facing the first unit, a detection circuit for detecting a signal obtained by the second resonance circuit, and a detection output A second comparator that obtains a transmission pulse signal by discriminating a clock at a predetermined threshold level, and discriminates a clock obtained in the second resonance circuit when receiving data from the first unit and counts the number of clocks Between the number of clocks obtained at the time of transmission at the first and third duty ratios and the number of clocks obtained at the time of transmission at the second and third duty ratios. Data demodulation including a counter for providing an output when counting the number of clocks of 2, and using one of the count outputs of the counter selected based on the demodulated signal to discriminate the output of the second comparator as a demodulated signal. Means, and a switching element connected between the second resonance circuit and ground, and a transmission pulse signal having a third duty ratio obtained from the second comparator when data is transmitted to the first unit. Reverberation control means for controlling reverberation vibration generated in the second resonance circuit by intermittently switching the switching element in accordance with transmission data at the timing of stopping oscillation of the oscillator based on Communication device.