JP2728028B2 - Simultaneous bidirectional input / output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simultaneous bidirectional input / output circuit, and more particularly to a simultaneous bidirectional input / output circuit using MOS transistors.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram of a conventional simultaneous bidirectional input / output circuit. The conventional simultaneous bidirectional input / output circuit has a first structure including a P-type MOS transistor 51 and an N-type MOS transistor 52 provided between a power supply voltage E and a ground voltage G.
CMOS inverter and power supply voltage E and 1 of power supply voltage E
A voltage at an intermediate level (first reference voltage) with respect to the reference voltage VRFH is used as a reference voltage VRFH.
The reference voltage VRFL is a voltage at an intermediate level (second reference voltage) between the voltage 2 and the ground voltage G, and a comparison circuit 54 that compares the reference voltage VRFL with the output voltage level, and a comparison result of the comparison circuits 53 and 54 Circuit 55 for determining the output voltage level from the other party based on the input voltage level
A first bidirectional input / output circuit 50 composed of
A second C transistor comprising a P-type MOS transistor 61 and an N-type MOS transistor 62 provided between
A MOS inverter, a comparison circuit 63 for comparing the reference voltage VRFLH with the output voltage level, a comparison circuit 64 for comparing the reference voltage VRFL with the output voltage level, and a comparison result of these comparison circuits 63 and 64 with the input voltage level. And a common input / output signal line 70 of the first and second bidirectional input / output circuits 50 and 60.
(Hereinafter, referred to as a signal line 70).

The input side of the first bidirectional input / output circuit 50 has an input terminal 57, a bidirectional input / output terminal 58, and an output terminal 59, and the input side of the second bidirectional input / output circuit 60 has an input terminal. A terminal 67, a bidirectional input / output terminal 68, and an output terminal 69 are provided.

In this simultaneous bidirectional input / output circuit, when the input terminal 57 of the first bidirectional input / output circuit 50 and the input terminal 67 of the second bidirectional input / output circuit 60 are both at a high level, an N-type MOS Since the transistors 52 and 62 are turned on and the P-type MOS transistors 51 and 61 are turned off, the signal line 70 goes low.

The input terminal 57 of the first bidirectional input / output circuit 50 and the input terminal 67 of the second bidirectional input / output circuit 60
Are low level, the P-type MOS transistor 5
1, 61 are turned on, and the N-type MOS transistors 52,
Since 62 is turned off, the signal line 70 goes high.

When the input terminal 57 of the first bidirectional input / output circuit 50 is at a high level and the input terminal 67 of the second bidirectional input / output circuit 60 is at a low level, the N-type MOS transistor 52 and the P-type MOS The transistor 61 is turned on, and the P-type MOS transistor 51 and the N-type MOS transistor 62
Is turned off, the input / output terminal 58 is at a low level, the input / output terminal 68 is at a high level, and a bus fight state is established between the input / output terminals 58 and 68. Therefore, the signal line 70 to which the input / output terminals 58 and 68 are connected is at an intermediate level which is intermediate between the high level and the low level. At this time, P-type CM
OS transistor 61 to N-type MOS transistor 52
, A through current flows.

On the other hand, when the input terminal 57 of the first bidirectional input / output circuit 50 is at a low level and the input terminal 67 of the second bidirectional input / output circuit 60 is at a high level, the P-type MOS transistor 51 and the N-type MOS transistor The transistor 62 is turned on, and the N-type MOS transistor 52 and the P-type MOS transistor 61
Is turned off, the input / output terminal 58 is at a high level, the input / output terminal 68 is at a low level, and a bus fight state is established between the input / output terminals 58 and 68. Therefore, the signal line 70 to which the input / output terminals 58 and 68 are connected is at an intermediate level which is intermediate between the high level and the low level. At this time, the P-type MO
A through current flows from the S transistor 51 to the N-type MOS transistor 62.

That is, when the output levels of the first and second bidirectional input / output circuits 50 and 60 are different from each other, a through current flows, and a through current flows with a probability of 1/2.

The first bidirectional input / output circuit 50 has a second
To determine the output level of the bidirectional input / output circuit 60,
This can be achieved by determining whether the potential of the signal line 70 connecting the two is at a high level, a low level, or an intermediate level.

FIG. 3 is a contrast diagram of the level of the input terminal and the level of the signal line. In this figure, H indicates a high level, L indicates a low level, and M indicates an intermediate level. From this table, when the level of the input terminal 57 is H, when the level of the signal line 70 is L, the level of the input terminal 67 is H, and when the level of the signal line 70 is M, the level of the input terminal 67 is L. When the level of the input terminal 57 is L, when the level of the signal line 70 is M, the level of the input terminal 67 is H. When the level of the signal line 70 is H, the level of the input terminal 67 is L. . That is,
The level of the signal output by the other party can be determined from the own input level and the level of the signal line 70.

When the level of the input terminal 57 is H and the level of the signal line 70 is L, the comparison circuit 53 outputs L and the comparison circuit 54 outputs L. In this case, the judgment circuit 55
Outputs a level H to the output terminal 59 based on the level H of the input terminal 57 and the level L of the comparison circuits 53 and 54.

Next, when the level of the input terminal 57 is H and the level of the signal line 70 is M, the comparison circuit 53 outputs L and the comparison circuit 54 outputs H. In this case, the judgment circuit 55
Are the level H of the input terminal 57, the level L of the comparison circuit 53,
The level L is output to the output terminal 59 based on the level H of the comparison circuit 54.

Next, when the level of the input terminal 57 is L and the level of the signal line 70 is M, the comparison circuit 53 outputs L and the comparison circuit 54 outputs H. In this case, the judgment circuit 55
Are the level L of the input terminal 57, the level L of the comparison circuit 53,
The level H is output to the output terminal 59 based on the level H of the comparison circuit 54.

Next, when the level of the input terminal 57 is L and the level of the signal line 70 is H, the comparator 53 outputs H and the comparator 54 outputs H. In this case, the judgment circuit 55
Outputs the level L to the output terminal 59 based on the level L of the input terminal 57 and the level H of the comparison circuits 53 and 54.

The first bidirectional input / output circuit 60 has the first
The output level of the bidirectional input / output circuit 50 is also determined by the first bidirectional input / output circuit 50 side.
Since the output level can be determined in the same manner as described above, the description is omitted.

[0016]

However, in the conventional simultaneous bidirectional input / output circuit, there is a drawback that current consumption increases because a through current flows with a probability of 1/2.

It is an object of the present invention to provide a simultaneous bidirectional input / output circuit capable of reducing the probability that a through current flows.

[0018]

In order to solve the above-mentioned problems, the present invention provides a first CMOS inverter provided between a first power supply voltage and a reference voltage, and a first CMOS inverter provided between the first power supply voltage and the first power supply voltage. A second CMOS inverter provided between a double power supply voltage and the first power supply voltage and having an output commonly connected to an output of the first CMOS inverter ;
In one CMOS inverter, its output and the first
MOS transistor closer to the power supply that supplies the power supply voltage
A first unidirectional element provided between the first unidirectional element and the second
In the CMOS inverter, the output thereof and the first
MOS transistor closer to the power supply that supplies the power supply voltage
And a second unidirectional element provided between the two .

[0019]

When the MOS transistor on the first power supply voltage side of the first CMOS inverter and the MOS transistor on the first power supply voltage side of the second CMOS inverter are turned on, that is, the low level is applied to the first CMOS inverter. When a signal is input and a high level is input to the second CMOS inverter, the same power supply voltage (first power supply voltage) is applied to both MOS transistors.
The level of the output terminal of the inverter and the level of the output terminal of the second CMOS inverter are equal, so that no through current flows between the two transistors.

[0020]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a circuit diagram of an embodiment of a simultaneous bidirectional input / output circuit according to the present invention. In the drawing, the same components as those of the conventional simultaneous bidirectional input / output circuit are denoted by the same reference numerals, and description thereof will be omitted.

The simultaneous bidirectional input / output circuit comprises a first input / output circuit 1, a second input / output circuit 2, and a signal line 70 to which the outputs of both input / output circuits 1 and 2 are commonly connected.

The first input / output circuit 1 is provided with a first CMO
The second input / output circuit 2 includes a second CMOS inverter 7 and a signal determination unit 8.

Further, the first CMOS inverter 5
A P-type MOS transistor 51 having a source to which the first power supply voltage E1 is applied, and a P-type MOS transistor 11 having a drain connected to the source of the P-type MOS transistor 51 and having a drain and a gate commonly connected.
And an N-type MOS transistor 52 whose drain is connected to the drain of the P-type MOS transistor 11, whose source is grounded, and whose gate is connected to the gate of the P-type MOS transistor 51.
The gates of the transistor 51 and the N-type MOS transistor 52 are connected to an input terminal 57, and the drain of the P-type MOS transistor 11 is connected to an input / output terminal 58.

The signal judging section 6 has one input side connected to the input / output terminal 58 and the other terminal connected to the intermediate point between the first power supply voltage E1 and the voltage E2 which is twice the first power supply voltage E1. A comparison circuit 53 to which a voltage VRFH2 (first reference voltage) is applied; one input side is connected to an input / output terminal 58;
Comparison circuit 5 in which intermediate voltage VRFL2 (second reference voltage) between first power supply voltage E1 and ground voltage is applied to the other terminal.
4 and a judgment circuit 55 for judging the level of the signal output from the second input / output circuit 2 based on the levels of the comparison circuits 53 and 54 and the input terminal 57. Is output to

On the other hand, the second CMOS inverter 7 includes a P-type MOS transistor 61 having a source to which a power supply voltage E2 twice the first power supply voltage E1 is applied, and a P-type MOS transistor 61.
An N-type MOS transistor 15 having a drain connected to the drain and the gate of the transistor 61;
The source and the drain of the OS transistor 15 are connected, a first power supply voltage E1 is applied to the source, and an N-type MOS transistor 62 whose gate is connected to the gate of the P-type MOS transistor 61 is provided. MO
S transistor 61 and N-type MOS transistor 62
Is connected to the input terminal 67, and the drain of the N-type MOS transistor 15 is connected to the input / output terminal 68.

The signal judging section 8 has one input side connected to the input / output terminal 68 and the other terminal connected to the intermediate between the first power supply voltage E1 and a voltage E2 twice as large as the first power supply voltage E1. A comparison circuit 63 to which a voltage VRFH2 (first reference voltage) is applied, and one input side connected to an input / output terminal 68;
Comparison circuit 6 in which intermediate voltage VRFL2 (second reference voltage) between first power supply voltage E1 and ground voltage is applied to the other terminal.
4 and a judgment circuit 65 for judging the level of the signal output from the first input / output circuit 1 based on the levels of the comparison circuits 63 and 64 and the input terminal 67. The judgment result of the judgment circuit 65 is an output terminal 69 Is output to

Further, the N-type MOS transistor 52 and P
The impedance (that is, the ON resistance) of each of the MOS transistors 61 in the ON state is (voltage E2−voltage E1) :( voltage E1−ground voltage G) =
It is assumed that the relationship between the ON resistance of the N-type MOS transistor 52 and the ON resistance of the P-type MOS transistor 61 is satisfied.

Next, the operation of this simultaneous bidirectional input / output circuit will be described. First, when the input terminal 57 of the first input / output circuit 1 and the input terminal 67 of the second input / output circuit 2 are both at a high level, the N-type MOS transistors 52, 62
Is turned on, and the P-type MOS transistors 51 and 61 are turned off. Further, since the N-type MOS transistor 52 is on, the gate of the P-type MOS transistor 11, N
The gates of the p-type MOS transistors 15 are both low, the p-type MOS transistor 11 is on,
The transistor 15 turns off. As a result, the input / output terminals 58 and 68 are both at a low level, and no bus fight occurs. Further, the signal line 70 is at a low level.

The input terminal 57 of the first input / output circuit 1
When the input terminal 67 of the second input / output circuit 2 is at a low level, the N-type MOS transistors 51 and 61 are turned on, and the P-type MOS transistors 52 and 62 are turned off. Further, since the N-type MOS transistor 61 is turned on, the gate of the N-type MOS transistor 15 and the
The gate of the type MOS transistor 11 becomes high level,
The N-type MOS transistor 15 is turned on, and the P-type MOS transistor 11 is turned off. As a result, the input / output terminals 5
Both 8 and 68 are at a high level and no bus fight occurs. Also, the signal line 70 is at a high level.

The input terminal 57 of the first input / output circuit 1
Is high and the input terminal 67 of the second input / output circuit 2 is low, the N-type MOS transistor 52 and the P-type MOS transistor 61 are turned on, and the P-type MOS transistor 51 and the N-type MOS transistor 62 are turned off. Becomes Further, since the P-type MOS transistor 61 is turned on, the gates of the N-type MOS transistor 15 and the P-type MOS transistor 11 become high level, the N-type MOS transistor 15 is turned on and the P-type MOS transistor 11 is turned off. . As a result, the input / output terminal 58 is at a low level and the input / output terminal 68 is at a high level, causing a bus fight.
A through current flows through the type MOS transistor 52. Also,
P-type MOS transistor 61 and N-type MOS in ON state
Since the impedance of the transistor 52 is matched, the level of the signal line 70 becomes an intermediate level, that is, the voltage E1.

Now, the input terminal 57 of the first input / output circuit 1
Is low and the input terminal 67 of the second input / output circuit 2 is high, the P-type CMOS transistor 51 and N
The type MOS transistor 62 is turned on, and the N-type MOS transistor 52 and the P-type MOS transistor 61 are turned off. At this time, since the voltage E1 is applied to the sources of the P-type MOS transistor 51 and the N-type MOS transistor 62 which are turned on, the input / output terminals 58,
68 are both at the voltage E1, and the signal line 70 is also at the voltage E1, that is, at the intermediate level. Also, P-type CMOS
No through current flows between the transistor 51 and the N-type CMOS transistor 62.

Next, the operation of the determination units 6 and 8 will be described. Since the determination units 6 and 8 operate in the same manner, the determination unit 6 will be described, and the description of the determination unit 8 will be omitted.
The operations of the determination units 6 and 8 are the same as in the conventional example.

In order for the first bidirectional input / output circuit 1 to determine the output level of the second bidirectional input / output circuit 2, the potential of the signal line 70 connecting the two bidirectional input / output circuits 2 is set to a high level, a low level or an intermediate level. It becomes possible by determining which one.
Note that FIG. 3 is referred to in the following description.

In FIG. 3, H is a high level, L is a low level, M
Indicates an intermediate level. From this table, when the level of the input terminal 57 is H, and when the level of the signal line 70 is L,
7 is H and the level of the signal line 70 is M, the level of the input terminal 67 is L, and the level of the input terminal 57 is L.
, When the level of the signal line 70 is M, the level of the input terminal 67 is H, and when the level of the signal line 70 is H,
It can be seen that the level of 7 becomes L. That is, the level of the signal output by the other party can be determined from the own input level and the level of the signal line 70.

When the level of the input terminal 57 is H and the level of the signal line 70 is L, the comparison circuit 53 outputs L and the comparison circuit 54 outputs L. In this case, the judgment circuit 55
Outputs a level H to the output terminal 59 based on the level H of the input terminal 57 and the level L of the comparison circuits 53 and 54.

Next, when the level of the input terminal 57 is H and the level of the signal line 70 is M, the comparison circuit 53 outputs L and the comparison circuit 54 outputs H. In this case, the judgment circuit 55
Are the level H of the input terminal 57, the level L of the comparison circuit 53,
The level L is output to the output terminal 59 based on the level H of the comparison circuit 54.

Next, when the level of the input terminal 57 is L and the level of the signal line 70 is M, the comparison circuit 53 outputs L and the comparison circuit 54 outputs H. In this case, the judgment circuit 55
Are the level L of the input terminal 57, the level L of the comparison circuit 53,
The level H is output to the output terminal 59 based on the level H of the comparison circuit 54.

Next, when the level of the input terminal 57 is L and the level of the signal line 70 is H, the comparator 53 outputs H and the comparator 54 outputs H. In this case, the judgment circuit 55
Outputs the level L to the output terminal 59 based on the level L of the input terminal 57 and the level H of the comparison circuits 53 and 54.

In this embodiment, the circuit is constituted by MOS transistors, but a bipolar transistor may be used instead of the MOS transistor. That is,
It is possible to use a PNP-type bipolar transistor instead of the P-type MOS transistor and use an NPN-type bipolar transistor instead of the N-type MOS transistor.

[0040]

According to the present invention, a first CMOS inverter provided between a first power supply voltage and a reference voltage;
Simultaneous bidirectional input is provided between a power supply voltage twice as high as the first power supply voltage and a second CMOS inverter having an output commonly connected to the output of the first CMOS inverter. Since the output circuit is configured, the first CMOS
When both the MOS transistor on the first power supply side of the inverter and the MOS transistor on the first power supply side of the second CMOS inverter are turned on, the output of both inverters is at an intermediate level, so that bus fight occurs. No through current flows between the two transistors.

Therefore, the probability that a through current flows can be reduced to half of the conventional case, that is, 1/4, so that the current consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of a simultaneous bidirectional input / output circuit according to the present invention.

FIG. 2 is a circuit diagram of a conventional simultaneous bidirectional input / output circuit.

FIG. 3 is a contrast diagram of the level of an input terminal and the level of a signal line.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st input / output circuit 2 2nd input / output circuit 5 1st CMOS inverter 6,8 signal determination part 7 2nd CMOS inverter 7 11,61,51 P type MOS transistor, 15,52,62 N type MOS transistors 53, 54 Comparison circuits 63, 64 Comparison circuits 55, 65 Judgment circuits 70 Signal lines

Claims (6)

(57) [Claims] A first CMOS inverter provided between a first power supply voltage and a reference voltage; and a power supply voltage twice as large as the first power supply voltage and the first power supply voltage. provided, a second CMOS inverter having a common output coupled to the output of the first CMOS inverter, in the first CMOS inverter, before its output
The MOS transistor closer to the power supply that supplies the first power supply voltage
A first unidirectional element provided between the first CMOS transistor and the second CMOS inverter;
The MOS transistor closer to the power supply that supplies the first power supply voltage
A second unidirectional element provided between the transistor and the transistor . 2. The device according to claim 1, wherein said first and second unidirectional elements are:
Diode connection structure with drain and gate connected in common
A MOS transistor comprising:
2. The simultaneous bidirectional input / output circuit according to 1. 3. The first and second CMOS inverters.
A determination means for determining the voltage level of the output of the
3. The simultaneous bidirectional input / output according to claim 1, wherein
circuit. 4. The method according to claim 1 , wherein the determining means is configured to control the first and second states.
The ternary signal on the output signal line of the CMOS inverter and the
A reference voltage not less than 1 power supply voltage and not more than 2 times that power supply voltage
A first comparison circuit for comparing the first and second
Ternary signal on the output signal line of the two CMOS inverters and
Note that the ratio is lower than the first power supply voltage and higher than the ground voltage.
A second comparison circuit for comparing the first and second comparison circuits;
From the comparison result on the road and the level of the binary signal
A judgment circuit that judges the level of the signal output by the other party
4. The simultaneous two-way input / output according to claim 3, wherein
Power circuit. 5. In the first CMOS inverter,
ON resistance of the CMOS transistor on the reference voltage side;
The first power supply in the second CMOS inverter
The on-resistance of the MOS transistor on the power supply voltage side twice the voltage
The ratio to the resistance is (voltage twice as high as the first voltage−the first voltage).
Voltage) and (the first voltage−the reference voltage)
5. A method according to claim 1, wherein the two are equal.
Simultaneous bidirectional input / output circuit. 6. A bipolar transistor in place of said MOS transistor.
3. A transistor according to claim 1, wherein
6. The simultaneous bidirectional input / output circuit according to any one of 5.