JP2723776B2 - Automatic gain control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control circuit for transmitting a signal or the like for waveform transmission.

[0002]

2. Description of the Related Art Conventionally, a communication signal is attenuated in a communication path in a data communication device, and the attenuation rate of the communication signal differs depending on a distance between communication devices and a signal cable. When amplifying the attenuated signal to a level at which data can be identified, the error occurrence rate at the time of data identification can be reduced by selecting an optimal amplification rate at the time of data reproduction. In order to automatically control the optimum amplification factor, some data communication devices have an automatic gain control circuit.

The above-described automatic gain control circuit detects a peak voltage of a signal to be reproduced within a certain period, changes the amplification factor of the amplifier by comparing the peak value with a reference value, and always amplifies the signal to a level at which data can be identified. Is a circuit for controlling the amplifier. The gain of this automatic gain control circuit changes according to the peak voltage of the signal, but the change in the gain is digital. The gain decreases when the peak voltage exceeds a certain value, and increases when the peak voltage falls below a certain value. In addition, the amplification factor exists in steps at certain intervals (see FIG. 5).

[0004] However, when noise on a signal is detected as a peak voltage, the step of the amplification factor is determined by the peak voltage determined by the noise level. For example, when the true peak value of the signal shown in FIG. 5 is at the level of A, it is appropriate that the amplification factor is B. However, if the peak value is A 'due to the influence of noise, the amplification factor drops to B', and the automatic gain control circuit takes an inappropriate amplification factor for the signal.

Referring to FIG. 3, a conventional automatic gain control circuit includes an amplifier 31 for amplifying an input signal 41 and a peak value detection circuit 32 for detecting a peak value of an output signal 42.
A sample and hold circuit (S / H) 33 for holding a peak value 42, a frame generation circuit 34 for generating a frame signal 43, a comparator (CMP) 40 for comparing a peak value with a reference value 45, and an amplifier 31 And an AGC control counter 39 for instructing an amplification factor.

Here, the frame generation circuit 34 outputs a frame signal 43 at regular intervals, and the peak value detection circuit 3
Synchronization 2 and sample and hold circuit (S / H) 33 and AGC control counter 39 preparative Ru. In addition, one frame is defined between frame signals.

Next, a reproduced signal for explaining the operation of the conventional automatic gain control circuit is input to an amplifier 31. The signal 41 is amplified by the amplifier 31 at the amplification factor given to the amplifier 31 at that time, and output to a data identification circuit (not shown). The amplified signal 42 is also input to the peak value detection circuit 32. Peak value detection circuit 3
In 2, the peak value of the signal 42 is detected, and the sample and hold circuit 33 holds the peak value of the signal for one frame. At this time, the peak value detection circuit 32 is reset by the frame signal 43 and searches for the peak value of the next frame. The held peak voltage 44 is compared with a reference voltage value 45 by the comparator 40. Reference value 45 and peak value PP
An example of the relationship is shown in FIG.

The result of comparison with the reference voltage value 45 is based on the relationship between the peak voltage and the reference voltage, where peak voltage> reference voltage → decrease the amplification factor (step down) Peak voltage <reference voltage → increase the amplification factor (step up) Is input to the AGC control counter 39 as an up / down signal 46 for performing the control of. The amplification factor of the step determined by the counter value of the AGC control counter 39 is instructed to the amplifier 31, and the amplifier 31 amplifies the signal at the amplification factor.

[0009]

However, referring to FIG. 6 showing a timing chart of a frame signal and a step change control system signal, the conventional automatic gain control circuit has a large difference in signal amplitude level as a whole. However, since the peak value detection is always performed, the noise on the signal is also detected as the peak value, and the step is changed. That is, in the conventional automatic gain control circuit,
Always performs peak value detection, and based on this, constantly
Since noise has been changed,
The step change is frequently performed due to the influence. As a result, the AGC control counter 39 responds to the signal by the actual signal.
Since an amplification factor step that does not match the signal data is taken and optimal amplification factor control is not performed, there is a high possibility that a data error occurs because the data identification level does not match the signal. That is, in the conventional peak value detection type automatic gain control circuit, when noise enters the signal and the peak value becomes larger than the actual signal, an improper step change is performed to match the actual signal at the time of data identification. Error occurs. Therefore, the present invention is not affected by noise.
The irrationalities of frequently changing steps
Signal level, such as immediately after starting communication.
If the gain is greatly shifted, the amplification step
It is an object to provide an automatic gain control circuit for bundling.

[0010]

An automatic gain control circuit according to the present invention includes an amplifier for variably amplifying an input signal according to a first control signal, and a frame for outputting a frame signal at predetermined intervals.
A frame generation circuit and the amplification in synchronization with the frame signal.
Value detection circuit that detects the peak voltage of the output signal of the heater
And the peak voltage is kept constant in synchronization with the frame signal.
A sample-and-hold circuit for holding for a period, and the sample
.Peak voltage held by the hold circuit and first base
The first core for comparing with a reference voltage and outputting the comparison result
And a ratio between the peak voltage and the second reference voltage.
And outputs a result of the comparison.
And the output of the first comparator and the second
When the outputs of the parators are at the same logic level,
Counts in synchronization with the
A counter that resets when the level is high and the counter
The second control signal when the count value of
A control circuit for outputting, and an operation in response to the second control signal
An AGC control counter, wherein the first comparator
Change the number of steps according to the output of the
AGC control for outputting the first control signal corresponding to a number
Automatic gain control with a basic basic configuration consisting of a counter
In the control circuit, the counter operates when the A
Initial value of the count value according to the number of steps of the GC control counter
It is characterized in that the period value is increased or decreased.

As described above, the present invention provides the above-described basic structure.
An automatic gain control circuit having a counter
Is the number of steps of the AGC control counter at the time of reset.
The initial value of the count value is increased or decreased according to
ing.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the basic principle of the automatic gain control circuit of the present invention will be described.
Referring to FIG. 1 showing the present configuration , this basic basic configuration is described.
The automatic gain control circuit includes an amplifier 1 for amplifying an input signal 11, a peak value detection circuit 2 for detecting a peak value of an output signal 12, a sample / hold circuit (S / H) 3 for holding the peak value 12, and A frame generating circuit 4 for generating a frame signal 13, a first comparator (CMP) 5 for comparing a peak value with a reference value a15, a second comparator 6 for comparing a peak value with a reference value b16, A counter 7 that counts in accordance with the outputs of the second comparators 5 and 6, and a run / stop that outputs a run instruction 19 when the counter value 20 exceeds a predetermined value.
When the run instruction 19 is issued, the first
Count value is increased according to the output of the comparator 5 of
And an AGC control counter 9 which goes down. It is assumed that the counter 7 holds the maximum value at the time of overflow.

Next, the operation of the automatic gain control circuit according to the basic configuration of the present invention will be described.

The peak value 14 held by the sample and hold circuit 3 is input to the first comparator 5 and the second comparator 6. In the first comparator 5,
The peak value 14 is compared with a reference value a15. At the same time, the second comparator 6 compares the peak value 14 with the reference value b16. The reference values a and b (15 to 16) are within the data recognizable range according to the input signal and are ±± of the desired peak voltage.
It is set to several% (see FIG. 4B).

The comparison result between the peak voltage of the signal and the reference voltage is input to the counter 7 as data for each frame. The counter 7 receives the step-down signals 18 from the step-up signal 17 or the second comparator 6 from the first comparator 5, output action of the first and second comparators 5 and 6 as an up cans counter
When receiving another combination of force signals, the reset (counter value = 0) operation is performed.

FIG. 9 shows the truth values of the outputs (17, 18) of the first and second comparators 5, 6 and the counter input.

Referring to FIG. 9, the run / stop control circuit 8 outputs the following instruction to the AGC control counter 9 according to the value of the counter 7.

When the counter 7 is equal to or greater than 4, a run instruction is output. …
(1) When the value of the counter 7 is less than 4, a stop instruction is output. …
(2) The run instruction / stop of the run / stop control circuit 8
In response to the p instruction 19, the AGC control counter 9 performs a step change operation on the amplification factor for the amplifier 1 when the run instruction is performed, and stops the step change operation when the stop instruction is performed.
FIG. 8 shows an operation example of the counter 7 and the run / stop control circuit.
Shown in

Basic principle of the present principle for the same signal as the conventional example
Referring to Figure 7 showing the operation of the arrangement, although the automatic gain control circuit in the conventional example is performed constantly step changes, Motohara
In the automatic gain control circuit having the logical basic configuration , since the step change is not performed due to the influence of noise, an amplification factor step that does not match the actual signal data is not taken.

In the automatic gain control circuit according to this basic configuration, the run / stop determination value of the counter is set to 4, but other values according to the input signal can be taken.

Next, an automatic gain control circuit according to an embodiment of the present invention will be described.

Referring to FIG. 2, the automatic gain control circuit according to an embodiment of the present invention, instead of the automatic gain control circuit 9 according to principle basic construction of the present invention, first when the run command 19 is issued Except for the configuration having an AGC control counter 29 for increasing / decreasing the count value in accordance with the output of the comparator 5 and specifying the initial value 21 of the counter 7 by the number of amplification steps, the same as the automatic gain control circuit according to the basic basic configuration In the configuration, the same components are denoted by the same reference numerals. That is, in this embodiment, the amplifier 1 for amplifying the input signal 11, the peak value detection circuit 2 for detecting the peak value of the output signal 12, the sample / hold circuit (S / H) 3 for holding the peak value 12, A frame generating circuit 4 for generating a frame signal 13, a peak value and a reference value a15
A first comparator (CMP) 5 for comparing the peak value with a reference value b16,
A counter 7 that counts in response to the outputs of the first and second comparators 5 and 6 and a ru that outputs a run instruction 19 when the counter value 20 exceeds a predetermined value
and an n / stop control circuit 8.

Next, the operation of the automatic gain control circuit according to the embodiment of the present invention will be described.

The operation of this embodiment and the basic basic configuration
The difference of the operation of the automatic gain control circuit is that the initial value of the counter 7 is initialized as follows at the time of reset by the amplification step number of the AGC control counter 29.

When the amplification step is large → large initial value → small judgment count (3) During the amplification step → small initial value → large judgment count (4) When the amplification step is small → initial value Large → small judgment count ... (5) That is, it is necessary to greatly change the amplification factor step of the amplifier 1 immediately after the start of communication or the like by the initialization operation of (3), (4) and (5) described above. In this case, the convergence of the amplification factor step can be accelerated.

[0026]

As described above, the automatic gain control circuit of the present invention provides a run /
By controlling the operation of the AGC control counter by the stop instruction, it is possible to eliminate a change in the amplification factor due to noise.

Therefore, there is an effect that the signal is stabilized at an appropriate amplification factor step and a data error can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an automatic gain control circuit according to a basic configuration of the present invention.

FIG. 2 is a block diagram illustrating an automatic gain control circuit according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional automatic gain control circuit.

4A and 4B are diagrams illustrating a relationship between a reference value and a peak value, wherein FIG. 4A illustrates a case of a conventional example, and FIG.
It is a figure explaining the case of a fundamental basic composition, and the case of an example.

FIG. 5 is a diagram illustrating an amplification factor step.

FIG. 6 is a timing chart of a step control system signal of the conventional automatic gain control circuit.

FIG. 7 is a timing chart of a step control system signal of the automatic gain control circuit according to the basic basic configuration of the present invention.

FIG. 8 is a diagram illustrating operations of a counter 7 and a run / stop control circuit.

FIG. 9 is a diagram showing a truth value of an input signal of the counter 7;

[Explanation of symbols]

 1, 31 amplifier 2, 32 peak value detection circuit 3, 33 sample and hold circuit (S / H) 4, 34 frame generation circuit 5, 6, 40 comparator (CMP) 7 counter 8 run / stop control circuit 9, 29, 39 AGC control counter 11, 41 Input signal 12, 42 Amplifier output 13, 43 Frame signal 14, 44 Input peak value signal 15, 16 Reference voltage value 17 Step-up signal 18 Step-down signal 19 Run / stop instruction 20 Counter value 21 Initial value of counter

Claims (1)

(57) [Claims] An input signal is varied according to a first control signal.
An amplifier that amplifies and outputs a frame signal at predetermined intervals
And a frame generating circuit for synchronizing with the frame signal.
Peak value detection to detect the peak voltage of the amplifier output signal
Output circuit and the peak voltage in synchronization with the frame signal.
A sample and hold circuit for holding the
The peak voltage held by the sample hold circuit
No. 1 that compares the reference voltage with the first reference voltage and outputs the comparison result.
1 comparator, said peak voltage and a second reference voltage
And outputs a result of the comparison.
The output of the first comparator and the second
When the outputs of the comparators are at the same logic level,
Counts in synchronization with the frame signal and differs from each other
A counter for resetting at the time of a logic level;
The second control signal when the count value of the
And a control circuit for outputting the second control signal.
An AGC control counter that operates, wherein the first controller
Change the number of steps according to the output of the
AGC for outputting the first control signal corresponding to the number of taps
A control counter, wherein the counter is
Counts according to the number of steps of the AGC control counter
Automatic gain control circuit characterized by increasing or decreasing the initial value of the value
Road.