JP2722463B2 - Address control device - Google Patents

Description

The present invention relates to an address control device. [Prior art] Conventionally, address control devices used for electronic musical instruments and the like are:
A read address of the memory storing the amplitude data of the waveform is output, and it is determined whether or not the read address has reached a predetermined final address. When the read address has reached the final address, a predetermined start address is determined as the next read address. By repeatedly outputting the address or the read address at that time, loop reproduction or reading of a normal tone is performed. FIG. 2 is a circuit block diagram showing a circuit configuration of such a conventional address control device. In FIG. 1, a loop end address register 1 is composed of eight stages of shift registers for storing data of eight channels corresponding to, for example, eight tone polyphonics, and is composed of each shift register. Stores a loop end address consisting of bits. Then, address data supplied from a CPU (not shown) or the like is written into the shift register of each channel, and the written data is output in synchronization with the timing of the corresponding channel. The loop end address of the loop end address register 1 is output to the A input terminal of the selector 3. Hereinafter, other registers to be described later are similarly constituted by eight stages of shift registers. Each shift register has a storage capacity corresponding to the bit line of data to be written, and the written data is stored at the timing of the corresponding channel. Output synchronously. The end address register 2 is a register for storing a normal read end address of a musical tone, and the written end address is output to the B input terminal of the selector 3.
The selector 3 selects one of the A input and the B input according to the content of the end flag output from the end flag register 4 and outputs the selected input to the B input terminal of the comparator 5. The comparator 5 compares the current read address from the current address register 16 supplied to the A input terminal with the output of the selector 3 supplied to the B input terminal, and outputs the comparison result to AND gates 6 and 7. . The data of the end flag register 4 is supplied to the other input terminals of the AND gates 6 and 7. The selector 8 selects one of the output of the current address register 16 supplied to the A input terminal and the output of the loop start address register 9 supplied to the B input terminal in accordance with the control signal output from the AND gate 6, and Output to the A input terminal of the adder 15. The output of the AND gate 7 is input to the reproduction flag register 12 via the inverter 10 and the AND gate 11. Also, the address pitch data of the read address written in the pitch data register 13 and the reproduction flag register
The contents of 12 are supplied to the B input terminal of the full adder 15 via the group of AND gates 14. The full adder 15 adds the inputs of A and B, and outputs the addition result to the current address register 16. The current address register 16 stores the result of the addition and outputs the result to the half adder 17 and the selector 18. The selector 18 outputs the current address supplied to the B input terminal and the output of the half adder 17 obtained by adding the current address to +1 to a waveform memory, an interpolation circuit, etc. (not shown) at the timing synchronized with the selection signal CH. Next, the operation of the address control circuit having the above configuration will be described. Hereinafter, the operation will be described using one channel as an example.
When the content of the end flag register 4 of a certain channel is “0”, that is, when loop reproduction is performed, the selector 3 selects the loop end address of the A input and outputs it to the B input terminal of the comparator 5. Further, the current address output from the current address register 16, that is, the current read address is supplied to the A input terminal of the comparator 5, so that the two are compared, and if A <B, "0" is output. . Therefore, the outputs of the AND gates 6 and 7 become "0", and the selector 8 selects the current address of the A input and outputs it to the full adder 15. The current address is added to the pitch data from the pitch data register 13 by the full adder 15, and the addition result is written to the current address register 16 as the next read address. Then, the written address and the address obtained by adding +1 to the written address are selected by the selector 18, the written address is output at the first half timing of the corresponding channel, and the address is added to the +2 timing at the second half timing.
The set address is output to a waveform memory, an interpolation circuit, and the like. Thereafter, the interpolation circuit interpolates the amplitude data between the address and the next address. On the other hand, if the result of the comparison by the comparator 5 is A ≧ B,
That is, when the current read address reaches the loop end address, "1" is output from the comparator 5, and the output of the AND gate 6 becomes "1". Therefore, the selector 8 selects the loop start address of the B input and selects the full adder
Output to 15. Then, pitch data is added to the loop start address in the same manner as described above, and is written to the current register as the next read address. When the content of the end flag register 4 is “1”, that is, when a normal tone is read, the end address of the B input of the selector 3 is selected and output to the comparator 5. The comparator 5 compares the end address with the current address, and outputs “0” if the current address has not reached the end address. And, as in the case of the above-described loop reproduction, the address obtained by adding the pitch data is
Current address register 16 as next read address
Is written to. On the other hand, when the current address reaches the end address, "1" is output from the comparator 5, and since the end flag is "1", the output of the AND gate 6 becomes "0" and the output of the AND gate 7 becomes "0". The output becomes "1". Then, a signal “0” obtained by inverting the output of the AND gate 7 is written in the reproduction flag register 12. As a result, the AND gate group 14 closes, no pitch data is supplied to the full adder 15, and the current address reaching the end address is written into the current address register 16 again. As described above, this address control circuit compares the actually output read address with the loop end address or end address, and when the read address reaches the final address, outputs the loop start address and the like as the next read address. Was to do. Therefore, when the amplitude data of "0 to 8" as shown in FIG. 3 is stored in the memory and the amplitude data during that period is read, "8" is set in the end address register 2 as the end address. However, when the read address output from the current address register 16 reaches the end address “8”, for example, an address of “9” which is incremented by 1 is output for interpolation of amplitude data between the addresses. As a result, there is a problem that data that does not need to be read is read and the data is output as a musical tone. [Problems to be Solved by the Invention] As described above, when the read address output to the memory coincides with the last address of the waveform memory, the conventional address control device usually performs interpolation to perform interpolation. Although the amplitude data of the address is read, there is a problem that the address cannot be specified because no address exceeding the final address exists. Further, when the read address exceeds the last address of the waveform memory, there is a disadvantage that an address that does not exist is specified. Further, when the read address exceeds the loop end address, there is a problem that unnecessary amplitude data is specified. An object of the present invention is to control an address so as not to exceed a predetermined final address. [Means for Solving the Problems] The present invention provides a storage means for storing a read address for reading amplitude data of a waveform sampled at a predetermined cycle, and a predetermined address based on the read address stored in the storage means. And a predetermined read address output from the calculation means is compared with a predetermined final address, and the predetermined read address calculated by the calculation means is stored in the predetermined final address. If not reached, the calculated predetermined read address is stored in the storage means as the next address, and when the calculated predetermined read address reaches the predetermined final address, a predetermined start address is changed to the next address. Address control means for storing the read address in the storage means. [Operation] The operation of the present invention is as follows. The amplitude data of the waveform sampled at a predetermined cycle is read by the read address stored in the storage means. The calculating means calculates a predetermined read address based on the read address stored in the storage means. The predetermined read address is compared with a predetermined final address. If the calculated predetermined read address does not reach the predetermined final address, the calculated predetermined read address is stored in the storage means as the next address. When the calculated predetermined read address reaches the predetermined final address, the operation of storing the predetermined start address as the next read address in the storage means is repeated. Thus, when determining the next read address by comparing with the predetermined final address, the read address stored in the memory used for reading the amplitude data of the actual waveform is not directly used, but is calculated by the arithmetic means. Since the obtained read address is used, the read address can be controlled so as not to exceed a predetermined final address. Embodiment An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a circuit block diagram of an address control device of an electronic musical instrument. In the figure, components having the same configuration and operation as those of the conventional address control circuit of FIG. 2 are denoted by the same reference numerals, and detailed description is omitted. The pitch data register 21 is a register for storing an address pitch read from a waveform memory or the like (not shown), and is composed of eight stages of shift registers. Each shift register has an integer part data corresponding to an address on the waveform memory and a space between them. And the decimal part data for designating the address of the waveform memory. The decimal part data can specify an address pitch finer than the address pitch of the waveform memory. The full adder 22 is an AND gate group applied to the B input terminal.
The integer part data and the decimal part data of the pitch data output from 14 are added to the current address fed back from the current address register 25 supplied to the A input terminal, and the addition result is input to the selector 23 and the A input of the comparator 5. Output to terminal. The selector 23 selects one of the diffusion result and the output of the current address register 25 given to the B input terminal according to the output from the AND gate 7, and
Output to 24 A input terminals. Then, the selector 24 selects one of the output from the selector 23 and the output of the loop start address register 9 given to the B input terminal according to the output from the AND gate 6, and outputs it to the current address register 25 as the next read address. The current address register 25 is a register that stores integer part data and decimal part data of the current address of each channel,
The current address is output to the B input terminal of the selector 27 and is also output to the half adder 26. Half adder 26
Outputs the current address as +1 to the A input terminal of the selector 27. The selector 27 outputs A,
One of the inputs of B is selected, the current address of B input is output in synchronization with the first half timing of each channel, and the address obtained by adding +1 to the current address of A input in synchronization with the second half timing is stored in the waveform memory and interpolation. Output to circuit etc. Next, the operation of the address control circuit having the above configuration will be described. The operation for one channel will be described for simplicity. When the content of the end flag of a certain channel in the end flag register 2 is "0", that is, when loop reproduction is performed, the result of addition of the pitch data and the current address output from the full adder 22 and the selector 3 Are compared by the comparator 5 with the loop and address output from the. When the addition result has not reached the loop end address, "0" is output from the comparator 5, and the outputs of the AND gates 6 and 7 become "0". Therefore, both the selectors 23 and 24 select the A input, and the addition result of the full adder 22 which added the pitch data to the current current address is used as the next read address in the current address register.
Output to 25 and written. On the other hand, in the comparison by the comparator 5, when the addition result of the full adder 22 reaches the loop end address, the comparator 5 outputs “1”. In this case, the end plug is "0"
Therefore, the output of the AND gate 7 remains “0” and the output of the AND gate 6 becomes “1”. as a result,
The selector 24 selects the B input, outputs the loop end address to the current address 25 as the next read address, and the loop start address is written into the register. Therefore, since the current address register 25 outputs at most only one address before the loop end address, even if the selector 27 outputs an address obtained by adding "1" to the address for interpolation, the loop end address is output. And unnecessary amplitude data is not read out. When the content of the end flag register 2 is "1", that is, when a normal tone is read out, the comparator 5 compares the result of adding the current current address with the pitch data and the end address. When the addition result has not reached the end address, the selectors 23 and 24 select the A input as described above, and the result of adding the pitch data to the current current address is stored in the current address register as the next read address. Written. On the other hand, when the addition result of the full adder 22 reaches the end address, the comparator 5 outputs “1”. In this case, since the end flag is “1”, the output of the AND gate 6 remains “0”, and the output of the AND gate 7 becomes “1”. As a result, the selector 23 selects the B input and the selector 24 selects the A input. Therefore, the current current address, that is, the address one pitch data before the end address is written into the current address register 25 again, and Progress is stopped. Therefore, even if an address obtained by adding "1" to the integer part data of the current address output from the current address register 25 for interpolation is output, an address exceeding the end address is not output as a read address. . By performing the above operation for each channel of the register, the read address can be controlled so as not to exceed the predetermined final address. As described above, it is determined whether or not the operation result of the pitch data for determining the read address pitch of each channel and the current read address has reached a predetermined loop end address or end address. The start address is output as the next read address, or the calculation of the address is stopped, so that the read address actually output to the waveform memory, interpolation circuit, etc. does not exceed the predetermined loop end address or end address. Can be controlled. [Effects of the Invention] As described above, according to the present invention, when comparing with a predetermined final address to obtain the next read address,
Since the read address stored in the storage means used for reading the actual waveform amplitude data is not directly used but the read address obtained by the arithmetic means means is used, the read address output to the memory or the like is used. Address can be controlled so that the actual read address does not exceed a predetermined final address even when interpolation is performed between the address and an address obtained by advancing that address, thereby preventing unnecessary data from being output. be able to.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit block diagram of an address control device according to an embodiment of the present invention, FIG. 2 is a circuit block diagram of a conventional address control device, and FIG. FIG. 1 ... Loop end address register, 3,8,18,23,24,27 ... Selector, 5 ... Comparator, 9 ... Loop start address register, 13,21 ... Pitch data register, 15,22 ... ... full adder, 16, 25 ... current address register, 17, 26 ... half adder.

Claims (1)

(57) [Claims] Storage means for storing a read address for reading amplitude data of a waveform sampled in a predetermined cycle; calculating means for calculating a predetermined read address based on the read address stored in the storage means; A predetermined read address to be output is compared with a predetermined final address, and when the predetermined read address calculated by the calculating means does not reach the predetermined final address, the calculated predetermined read address is compared with the predetermined read address. Address control means for storing in the storage means as a next address, and when the calculated predetermined read address reaches the predetermined final address, storing a predetermined start address in the storage means as a next read address; Address control device having: