JP2719277B2 - Automatic program analyzer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic program analyzer for creating a flowchart based on an assembler language program.

[0002]

2. Description of the Related Art Conventionally, the operation of a computer device is described in a specific program language, and the operation is analyzed by creating a flowchart or the like. Although the operation of the computer device is realized as a stack of executing a plurality of instructions according to a predetermined rule, a relation between a certain range of instructions is represented graphically for understanding the entire program. It is easier to understand. In particular, the machine language of a computer device is almost one-to-one.
A program written in an assembler language that supports the language has a large number of instruction steps, and it is difficult to analyze the program as a whole and understand the contents only by looking at the source program. If it is difficult to analyze a program, it is difficult to determine whether or not an algorithm to be realized by the program is correctly expressed, and it is difficult to quickly and efficiently create a program that operates correctly. In particular, a large-scale program is divided and created by a plurality of program creators and then put together as one program. However, in the verification work of the program created in this way, a flowchart or the like is created and the entire program is created. It is necessary to confirm the general flow of operation. In the preparation stage of such program creation, a so-called top-down method is used.
In many cases, the overall program flow is represented by a flowchart or the like, and a code is created using a programming language based on the flowchart. In such a case, it is easy to verify the program by comparing the flowchart created from the completed program with the original flowchart.

It is desirable that a flowchart for comprehending the contents of a program and for verifying the program be automatically created in order to eliminate the possibility of arbitrary judgment. 2. Description of the Related Art Conventionally, devices and programs for displaying a program described in a high-level language such as FORTRAN, BASIC or C as a flowchart have been put to practical use.
In such a high-level language, one instruction expresses a coherent execution content to such an extent that human understanding is easy. Actually, a translation program such as a compiler or an interpreter translates into a plurality of machine languages in accordance with a predetermined rule, and at execution, the translated machine languages are sequentially executed. As described above, in a high-level language, a single instruction expresses a coherent execution content to some extent, and it is relatively easy to understand what is expressed graphically in units of individual instructions. As a flowchart, an expression style such as a PAD diagram is considered in addition to a so-called flow chart.

On the other hand, in an assembler language program, each instruction substantially corresponds to a machine language, and a plurality of instructions are required to realize one set of operation contents. For this reason, in the flowchart, it is preferable to express a group of a plurality of instructions as one block in the flowchart. Such a block is, for example, a subroutine or
It can be divided as a range from an instruction that is a jump or branch destination of a program to a next jump or branch instruction. In addition, the applicant of the present application discloses Japanese Patent Application Laid-Open No. 3-519.
No. 26 discloses a method of dividing blocks by focusing on changes in flags.

[0005]

In a conventional automatic analyzer of a program in an assembler language, the relation between a group of instruction groups is represented by a flowchart. Since the operation in the block is still described in the original assembler language,
Its understanding is difficult.

SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic program analyzing apparatus capable of collectively expressing instructions in an assembler language so as to be easily understood by humans, for each block of a program representing a united execution operation. It is to provide.

[0007]

According to the present invention, there is provided an automatic program analyzing apparatus for outputting a program in an assembler language as a flowchart representing the operation of the program, in which each instruction in the assembler language is converted into an expression in a preset flowchart. And if the instruction is an instruction for performing a process of storing a predetermined value in a processing object that stores a predetermined value, a conversion unit that converts the processing target name and its storage content into an expression on a flowchart, Determining means for determining whether or not the processing target name of the processing target having the predetermined value stored by the instruction is included in the stored contents of the expression on the flowchart which has already been converted; If it is determined that the name is included, the processing included in the stored contents of the expression on the flowchart that has already been converted A program automatic analysis apparatus which comprises a processing means for replacing the elephant name in the storage contents of the processing object.

[0008]

According to the present invention, the automatic program analysis device comprises:
It includes a conversion unit, a determination unit, and a processing unit. The conversion means converts each instruction of the assembler language into an expression on a flowchart set in advance. If the instruction is an instruction for performing a process of storing a predetermined value in a processing object storing a predetermined value, the processing target name and its storage content are converted into an expression on a flowchart. The determination unit determines whether or not the processing target name for which the predetermined value is stored by the instruction is included in the already converted expression on the flowchart. The processing target is, for example, the storage content of a specific address in a memory or a specific register, and is distinguished by a processing target name. When the processing target name is included in the expression on the converted flowchart, the processing means replaces the processing target name included in the storage content of the expression on the converted flowchart with the storage content of the processing target. Replace with Since instructions for the same processing target are replaced and expressed, it is easy to grasp the execution contents of the program.

[0009]

FIG. 1 shows a schematic electrical configuration of an automatic program analyzer according to one embodiment of the present invention. The automatic program analyzer is realized by a program operation of the workstation 1. An external storage device 2 such as a magnetic disk or a magnetic tape device is connected to the workstation 1. A host computer 3 can also be connected to the workstation 1 via a communication line or the like. The result of the workstation 1 automatically analyzing the program is output to the printer 4. As the printer 4, a page printer such as a laser beam printer (abbreviated as "LBP") is preferably used.

In the workstation 1, a central processing unit (hereinafter abbreviated as "CPU") 5 and a memory 6
And a display device 7 such as a cathode ray tube (abbreviated as “CRT”). A control program for operating as an automatic program analyzer is read from the external storage device 2 into the memory 6. Further, a rule base for associating expressions on the flowchart with each instruction of the assembler language is also read from the external storage device 2 to the memory 6 as data. Thereby, the memory 6 stores each instruction of the assembler language,
It operates as a conversion means for converting into an expression on a flowchart set in advance. The CPU 5 serving as a processing unit divides an assembler language source program supplied from the external storage device 2 or the host computer 3 into predetermined blocks, converts each block into an expression on a flowchart, and indicate. The workstation 1 can print the converted flowchart by the printer 4 or store the flowchart in the external storage device 2.

FIG. 2 shows a workstation 1 shown in FIG.
Shows the automatic program analysis operation by In step a1, conversion from the beginning of the source program to a flowchart is started. At step a2, it is determined whether or not the source program has been completed. If the processing has not been completed, the process proceeds to step a3, in which a block for dividing the source program into one set of instructions is detected. Next, in step a4, the conversion within each block is performed, and in step a5, the result is output as a flowchart. If it is determined in step a2 that the source program ends, the process ends in step a6.

FIG. 3 shows the conversion operation in step a4 shown in FIG. The process starts from step b1, and in step b2, the line pointer p of the source program including the instruction to be converted is initialized to the last line of the block. At step b3, one line of the source program indicated by the pointer p is read. In the next step b4, the instructions contained in the read one line are converted into expressions on the flowchart.

At step b5, it is determined whether or not the converted instruction is a synthesizable instruction. If it is determined that the instruction is a synthesizable instruction, it is determined in step b6 whether a processing target that is a specific address of a register or a memory described as an operand is already used in a converted expression. You. If it has been used, in step b7, the conversion result is combined with the already used expression. If it is determined in step b5 that the combination is not possible, or if it is determined in step b6 that the processing target is not used, the conversion result is output as it is in step b8.

When step b7 or step b8 is completed, the process proceeds to step b9, where the value of the pointer p is decreased by one. At step b10, it is determined whether or not the pointer p has reached the first line of the block. If the first row has not been reached, the process returns to step b3, and thereafter, the conversion for each row up to step b9 is repeated. If it is determined in step b10 that the pointer p has reached the first line, the process ends in step b11.

A program in assembler language is generally executed in the order of lines in which instructions are described.
In the operation shown in FIG. 3, the instructions are converted into the expressions on the flowchart in the reverse order of the execution order of the program. FIGS. 4 and 5 show the process of converting the instructions in the reverse order and the effect thereof.

FIG. 4 shows an example of an assembler language source program and an expression on a flowchart converted by the present embodiment. FIG. 4A shows an example of an assembler language source program for a specific computer. FIG. 4B shows a flowchart obtained by converting the source program shown in FIG. 4A according to the present embodiment. Each line of the source program is described in the form of "label instruction operand" or "instruction operand".

In FIG. 4A, if a blank line is ignored, the program is described on the first to fifteenth lines. Of these, "BNE" on the first line and "BGT" on the thirteenth line are conditional branch instructions. “CALL” on the second and third lines is a subroutine call instruction. The “BRA” instructions on the fourth and fifteenth lines are unconditional branch instructions. The fifth to twelfth lines are grouped as one block 10 sandwiched between branch instructions. The branch destination “IADC30” in the first row is defined as a label in the third row. The branch destination “IADC60” on the thirteenth line is defined as a label on the fifteenth line. The target "ISKSPS" and "SADWAIT" of the subroutine call on the second and third lines
Is not defined on the source program shown in FIG. In the fourth and fifteenth lines, the branch destination "IAD
"CX" is not similarly defined.

In the flowchart of FIG. 4B, a reference symbol 11 is added to the beginning of the program. "P14
"3" indicates, for example, page 143 of the source program. The instruction on the first line is represented by a decision symbol 12. The subroutine calls on the second and third lines are indicated by subroutine call symbols 13 and 14, respectively. Since the branch destination when the condition of the first line is satisfied is the third line, the process branches to the middle of the subroutine call symbols 13 and 14. The fourth line branches out of the source program shown in FIG. “10e” indicates information of a position where a flowchart to be continued next exists.

On the fifth line in FIG. 4A, a label "IADC40" is defined. In the original source program, when a portion corresponding to the program branching to this label is represented in, for example, a portion of a flowchart indicated by “10d”, a reference symbol 16 is added. The block 10 is represented as a block processing symbol 17. The conversion within the block processing symbol 17 will be described later. Since the branch destination is already defined for the 13th line shown in FIG. 4A, the processing is performed as indicated by the judgment symbol 18 in FIG. The 14th line is displayed as a processing symbol 19 with only one instruction. The fifteenth line is displayed using the reference symbol 20 similarly to the fourth line.

FIG. 5 shows a process in which the source program in the block 10 shown in FIG. 4A is converted as in the block processing symbol 17 in FIG. 4B. In FIG. 5A, “CMP” on the twelfth row, which is the last row in the block,
The instruction is converted, as shown by. “CMP” indicates a comparison instruction, and the operand has two processing targets. “CWDT” to be processed first indicates a specific address of the memory. Another processing target "# 10
"0 / 4.096" indicates that the decimal number 100 should be reduced by 4.096 and the result should be expressed as an integer. The result is 24 in decimal, and in FIG.
The reference numeral 8 is used. Next, the eleventh and tenth lines are
And are converted as shown in and. In the assembler language source program, Roman letters are displayed in uppercase, but are converted to lowercase in the flowchart. The instruction on the eleventh line is an instruction for setting bit data represented by “irqll”, and the instruction on the tenth line is an instruction for disabling an interrupt. The content of such an instruction can be easily understood by displaying it as shown in FIG. The ninth and eighth lines in FIG. 4A are converted as shown in FIG. 5A. Since these instructions include the registers A and Y, in FIG. 5A, they are registers such as "Ra" and "Ry".

After the conversion of the "ADD" instruction in the eighth line as shown in the following, referring to the conversion results up to, it is found that the Y register has already been used. For this reason, the expression shown in FIG.
Are synthesized as shown in FIG. This synthesis is performed by replacing “(Ry + Ra)” on the right side of “Ry” on the right side of FIG. Are the same as in FIG. 5 (1).

The instruction on the seventh line in FIG.
It is converted as shown in (3). Are the same as those in FIG. 5 (2). The expression in the sixth row shown in FIG. 4A is converted into an expression as shown in FIG. This instruction is an operation for performing a logical AND operation between the storage content of the A register and the storage content of the memory represented by the SID, and storing the calculation result in the register A. Register A is shown in FIG.
Since it is used in the expression as shown in (2), the expression in FIG. 5 (3) is combined with the expression as shown in FIG. 5 (4). Is as it is. Next, FIG.
As shown in (4), the instruction on the fifth line in FIG. 4 (1) is converted. The instruction on the fifth line is the register B2SSD
Is an instruction to load the contents stored in the memory represented by. In this way, when converted as shown in FIG.
All the instructions in block 10 of (1) will be translated. In the flowchart output of step a5 in FIG. 2, the contents converted as shown in FIG. 5 (4) are output in the reverse order of the conversion as shown in FIG. Is displayed as follows.

In the above embodiment, the source program in the assembler language for a specific computer is converted into a flowchart. However, it is needless to say that the assembler language of another computer can be similarly converted.

[0024]

As described above, according to the present invention, when an instruction described as an assembler language program is converted into an expression on a flowchart, the instruction stores a predetermined value in a processing object storing a predetermined value. In the case of an instruction for performing processing to be stored, the processing target name and its storage content are converted into an expression on a flowchart, and the processing target name of a processing target having a predetermined value stored therein is already converted. If the processing target is included in the storage contents of the expression, the processing target name included in the storage contents of the expression on the flowchart already converted is replaced with the storage contents of the processing target. This is replaced with the form shown, making it easier to understand the operation contents of the block.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic electrical configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation shown in FIG.

FIG. 3 is a flowchart showing the operation of the embodiment shown in FIG. 1;

FIG. 4 is a diagram showing a source program converted by the embodiment shown in FIG. 1 and a flowchart.

FIG. 5 is a diagram illustrating a process of converting an instruction in a block according to the embodiment shown in FIG. 1;

[Explanation of symbols]

 Reference Signs List 1 workstation 2 external storage device 3 host computer 4 printer 5 CPU 6 memory 7 display device 10 block 12, 18 decision symbol 13, 14 subroutine call symbol 17 block processing symbol

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-216129 (JP, A) JP-A-4-199424 (JP, A) JP-A-4-199435 (JP, A) JP-A-4-199435 177427 (JP, A) JP-A-3-51926 (JP, A)

Claims (1)

(57) [Claims] 1. An automatic program analyzer for outputting a program in an assembler language as a flowchart representing the operation of a program. In the case of an instruction for performing processing for storing a predetermined value in a processing object for storing a value, a conversion unit for converting the processing target name and its storage content into an expression on a flowchart; Determining means for determining whether or not the processing target name of the converted processing target is included in the stored contents of the expression on the flowchart already converted; and determining that the processing target name is included by the determining means If the processing target name is included in the stored contents of the expression on the flowchart already converted, An automatic program analyzing apparatus, comprising: processing means for replacing the contents with memory contents.