JP2716055B2 - Vector processor control method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a control method of a vector processing device including a plurality of pipeline processing mechanisms, and more particularly, to a method of reducing wasteful idle time of resource waiting in a pipeline processing mechanism. The present invention relates to a control method of a vector processing apparatus which is preferably used for efficiently processing vector instructions by eliminating the same.

[Conventional technology]

In the case of executing a vector instruction in a vector processing device including a plurality of pipeline processing mechanisms and a plurality of vector registers, the processing device previously includes a pipeline processing mechanism (also referred to as a resource) and a vector used by the instruction. It is necessary to check whether the register is in the "empty" state. If they are not in the "empty" state (this is called a resource conflict or a register conflict), the execution of the instruction is delayed.

When such a conflict occurs, idle time is generated in resources and registers to which subsequent instructions are allocated, which lowers the performance of the system. As a conventional technique for improving the performance degradation, for example, a technique called “chaining” is known as one of the techniques.
In this technique, even if writing of the preceding vector instruction to the vector register is not completed, the written element is processed to be read by the subsequent instruction. That is, connecting two pipelines (chain)
And then process it. By this chaining, generation of useless idle time in the pipeline processing mechanism due to register conflict can be suppressed.

The technology related to such chaining is described in “Nikkei Electronics, November 19, 1984, pp. 262 to 264.
Pages, "Nikkei Electronics, 1983.4.11, pp. 147 to 148" and the like are known.

As a countermeasure for preventing the performance of the processing apparatus from deteriorating at the time of resource conflict, a method has been proposed in which a buffer of an instruction to be executed next is provided in each resource, and the next instruction is executed immediately after completion of the instruction being executed. This technique eliminates a dead time in transmission and reception of a control signal between an instruction activation management circuit and a resource, thereby preventing performance degradation of a processing device.

[Problems to be solved by the invention]

However, the prior art does not consider the chaining of the write operation to the vector register being read. That is, the above-described prior art controls the issue or execution of a subsequent instruction to be written to the vector register until reading of the vector register by the preceding instruction is completed. In addition, the issue or execution of the subsequent instruction is suppressed even when the register is read by the preceding instruction and read by the subsequent instruction or when a conflict occurs due to sharing of registers of the vector register peripheral circuit.

 As an example, consider the following simple program.

When this is executed by the vector processing device, the vector instruction sequence is Becomes Here, VR is a vector register. In this case, a conflict occurs in VR0 between the writing by the Load instruction and the reading by the Store instruction, which can be avoided by the chaining technique. However, the situation changes when considering that the vector instruction is processed by a device having a maximum vector length of 50. That is, since the vector instruction is a vector process with a vector length of 100, the vector length is 50.
In the device described above, it is necessary to execute the vector instruction twice, so that the first Store instruction and the second Load instruction cause VR0
Will hit. In general, conflict avoidance in such a case is not performed because a circuit for implementing a technology equivalent to chaining becomes complicated. As a result, the second Lo
Execution of the ad instruction is delayed until the execution of the first Store instruction is completed.

However, in the pipeline processing mechanism, the processing that needs to be suppressed when the above-described conflict occurs,
In a pipeline stage after the writing operation to the vector register or the reading operation from the vector register and before the operation, it is possible to execute the processing of the instruction regardless of the conflict. In other words, in the pipeline processing mechanism, the conventional technique of inputting the subsequent instruction to the pipeline processing mechanism at the stage when the access to the vector register by the preceding instruction is completely completed is a wasteful idle time for a stage unrelated to the conflict. In addition, even if the instruction following the instruction whose issuance has been suppressed due to the conflict does not cause a conflict, the subsequent instruction is stopped excessively. There is a problem that the performance of the entire processing system is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to prevent useless idle time from being generated in the execution of a subsequent instruction in the process of processing a subsequent instruction that causes a conflict with a preceding instruction, and to excessively execute an instruction unrelated to the conflict. The present invention provides a control method of a vector processing device which can prevent the above-mentioned suppression by a relatively simple control mechanism.

[Means for solving the problem]

According to the present invention, the object is to provide a circuit for detecting that a conflict has occurred, and to add a conflict information indicating that a conflict has occurred to a head element of a vector instruction when a conflict is detected. And a means for notifying the pipeline processing mechanism when the conflict release is detected. In addition, when the pipeline processing mechanism detects the conflict occurrence information, the pipeline processing means Is stopped at a specific stage, and a control means for restarting the pipeline processing upon receiving a conflict release notification is provided. Further, the above object is achieved by providing each pipeline processing mechanism with a conflict information counter that counts up (or down) in response to a conflict resolution notification and counts down (or up) when processing an instruction with conflict information. Is done.

[Action]

When a vector processor attempts to execute a vector instruction, if a conflict state is detected in which a vector register or the like used by the instruction is being used by a preceding instruction, the conflict information is set to the head of the vector instruction. Attached to the element and poured into the desired pipeline processing mechanism. When the pipeline processing mechanism detects the conflict information added to the head element, the pipeline processing mechanism detects the pipeline information upstream of the stage that accesses the vector register or the like.
Stop processing at the stage. As a result, the processing of the instruction assigned to the pipeline is stopped,
Of course, access to the vector register and the like is also suppressed, and collision of access is avoided. However, the pipeline processing of the vector instruction for which a conflict is detected is advanced halfway.

When detecting that the conflict has been resolved, the instruction execution control mechanism notifies the pipeline processing mechanism of the resolved information. Upon receiving the conflict resolution information, the pipeline processing mechanism restarts the processing of the stopped pipeline. This makes it possible to access the vector register and the like while avoiding collision with the access of the preceding instruction, and to minimize wasteful idle time of the pipeline processing mechanism due to a conflict. Become.

Further, the conflict information counter operates to count up by the conflict resolution notification and to count down by the processing of the instruction with the conflict information. When the count value is “0”, the pipeline processing mechanism determines that the conflict resolution notification has not arrived, stops the pipeline processing, and if the counter is not “0”, the conflict resolution information Is determined to have arrived, the counter is counted down, and control is performed so as to proceed without stopping the pipeline.

By providing such a conflict information counter, the loss of the resolution information when the conflict resolution information notification arrives before the head element of the vector instruction to which the conflict information is added arrives at a specific stage of the pipeline. Can be prevented. Further, even when instructions having a short vector length are consecutive and a conflict occurs, the conflict information can be counted, so that the applicable range of the pipeline processing by this method can be expanded.

〔Example〕

Hereinafter, an embodiment of a control method of a vector processing device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a vector instruction execution control device and an access instruction processing device according to the present invention.
3 is a block diagram showing the configuration of a vector instruction execution control device, FIG. 4 is a block diagram showing the configuration of an access instruction control circuit, and FIG. 5 is an access transmission. FIG. 3 is a block diagram illustrating a configuration of a control circuit. 1 to 5, 1 is a scalar processing unit, 2 is a vector instruction execution control device, 3 and 4 are access instruction processing devices, 5 and 6 operation devices, 7 is a vector register, 8 is a main storage control device, 9 is a main memory, 20 is an instruction register, 21 is an instruction activation management circuit, 22 is a state management circuit,
33 is an access instruction control circuit, 34 is an access request transmission control circuit, 210, 212, 219 are decoding circuits, 220 is a pipeline processing mechanism state management circuit, 221 is a vector register state management circuit, 346 is a conflict presence information detection circuit, and 353 is non-zero. It is a detection circuit.

In the overall configuration of the vector processing device according to the present invention shown in FIG. 2, the access instruction processing devices 3, 4 and the arithmetic devices 5, 6
Is constituted by a pipeline processing mechanism.

The vector instruction sent from the scalar processing unit 1 which is a normal central processing unit is sent to the vector instruction execution control unit 2
And activates the corresponding empty pipeline processing mechanism in the access instruction processing units 3 and 4 and the arithmetic units 5 and 6. The access instruction processing devices 3 and 4 control data transfer between the vector register 7 and the main storage device 9, and the vector register 7 stores a plurality of vector data. The main storage control device 8 receives an access request from the access instruction processing devices 3 and 4, and accesses the main storage device 9 according to the access request.

As shown in FIG. 1, the vector instruction execution control device 2 decodes the instruction in the instruction register 20 for receiving the vector instruction from the scalar processing unit 1 and the instruction in the instruction register 20, and starts the corresponding pipeline processing mechanism. And a state management circuit 22 that manages the state of each pipeline processing mechanism and vector register and provides information to the instruction activation management circuit 21. On the other hand, the access instruction processing device 3 includes four stages: an address calculation stage, an address translation stage, an exception detection stage, and a request transmission stage. Register 30
a is a base address register VBR holding the base value of the address of the access instruction sent from the vector instruction execution control device 2, and the register 30b is an increment address holding an increment value for obtaining the address of each vector element.・ Register ViR. The address of the vector element corresponding to the access instruction is obtained by passing the first element through the address adder 32 as the value of the VBR 30a, setting this in the address register 35a, and setting the second and subsequent addresses as
It is sequentially generated by adding the address register 35a and ViR30b. The address translation mechanism 36 is a mechanism that translates a logical address of an address obtained in the register 35a into an execution address, and can be realized by hardware such as a translation table including a translation pair of a logical address and a real address. The register 37a is a register for holding the real address after the address translation, and the exception detection mechanism 38 detects an addressing exception and a memory protection exception of the translated address. The register 39a is a register for holding an address after the exception is detected, and functions as a request buffer for absorbing disturbance of request processing due to contention with a request from another access request control device to the main storage device 9. . The access request transmission control circuit 34 controls the transmission of the request existing in the request buffer 39a to the main storage controller 8, and further detects the conflict occurrence information at the exit of the request buffer 39a. 2 has a function of stopping the transmission of the request to the main storage control device 8 until the notification of conflict resolution from the client 2 is received. The access instruction control circuit 33 holds the instruction sent from the vector instruction execution control device 2, judges the processing status of the access request in the access instruction processing devices 3 and 4, and calculates the access request together with a calculation instruction to the address adder 32. Control the generation of register
35b, 37b, and 39b are access registers corresponding to the address registers of the registers 35a, 37a, and 39a, respectively, and are registers for codes indicating the types thereof.

FIG. 3 shows details of the vector instruction execution control device 2. The state management circuit 22 includes a pipeline processing mechanism state management circuit 220 that holds a busy state corresponding to the pipeline processing mechanism, and a vector register state management circuit 221 that holds a busy state corresponding to the vector register. Each of the state management circuits 220 and 221 is set to a busy state when the instruction activation management circuit 21 activates the pipeline processing mechanism and the vector register 7, and the busy state is reported by the pipeline processing mechanism and the report of the processing end from the vector register 7. Reset. The decoding circuit 210 in the instruction activation management circuit 21 is a circuit for decoding an instruction in the instruction register 20, and determines a pipeline processing mechanism and a vector register used by the instruction. The comparison circuit 211 determines whether or not the pipeline processing mechanism determined by the decryption circuit 210 is in use, based on information from the state management circuit 220. As a result, if the target pipeline processing mechanism is “empty”, the comparison circuit 211 supplies an enable signal to the decoding circuit 215 via the gate 214, and permits transmission of the start signal 215a to the pipeline processing mechanism. If the target pipeline processing mechanism is "in use", the transmission of the activation signal 215a from the decoding circuit 215 is suppressed, and the transmission of the instruction activation report 216b to the scalar processing unit 1 is also suppressed. The comparison circuit 212 also determines whether or not the vector register determined by the decoding circuit 210 is in use based on information from the state management circuit 221. As a result, if the target vector register is “empty”, the comparison circuit 212
To the decryption circuit 215 via the, and permits transmission of the activation signal 215a. Even if the target vector register is "in use", the flip-flop 213 indicating that the conflict generation instruction is already being executed is set to "0".
If so, the conflict presence information 212a is added and the activation signal
Allow transmission of 215a. If the flip flop 21 is already
When 3 is “1” and the output of the comparison circuit 212 also indicates “in use” of the vector register, the activation signal 215a is suppressed. The flip-flop 213 is set to "1" by the activation of the conflict instruction, and is reset when the conflict is resolved. In the embodiment of the present invention, in order to simplify the description, the pipeline processing mechanism is capable of accepting one instruction with conflict information, and controls the suppression of the activation signal 215a by the flip-flop 213.
Going based on the information.

According to the present invention, the pipeline processing mechanism can accept a plurality of instructions having conflict information. In this case, instead of the flip-flop 213, the count-up (or
A counter that counts down (counts down) and counts down (or counts up) by executing an instruction with conflict information is provided, and the suppression of the activation signal 215a can be controlled based on the value of this counter. For example, when the counter is counted up by the conflict resolution notification, the activation signal 215a may be suppressed when the count value is “0”.

The register 218 holds the number of the conflicting vector register. Comparison circuit 240
Indicates the processing end report from the vector register 9 and the register
This is a circuit for comparing the vector register number under conflict occurrence held in 218, and if they match, sends a conflict elimination notification 241a to the pipeline processing mechanism and resets the flip-flop 213 during execution of the conflicted instruction. At this time, since the vector register must be kept busy,
A signal obtained by inverting the output of the decoding circuit 244 using the permission signal 241a is supplied to the AND gate 222. As a result, the reset of the vector register in the busy state is suppressed. The decoding circuit 219 is a circuit for decoding the register number of the instruction decoding circuit 210 and setting a "busy state" in the vector register state management circuit 221. Also, the decryption circuit 215
Is a circuit for decoding the number of the pipeline processing mechanism output from the decoding circuit 210 and transmitting a start signal to a target pipeline processing mechanism. In addition, gates 216, 217, 241,
242 is an AND gate, and gate 214 is a NOR gate and a gate, respectively.
243 is an inversion gate.

FIG. 4 shows details of the access instruction control circuit.

In FIG. 4, an activation signal 215a sent from the instruction activation management circuit 21 of the vector instruction execution control device 2 sets a busy flip-flop 332 indicating that an access instruction is being processed. Along with this, a code (including conflict existence information) indicating the type of access request accompanying the activation signal 215a and a vector length are set in the registers 330 and 331, respectively. The comparison circuit 336 compares the value of the vector length register 331 with the value of the counter composed of the “+1” circuit 335 and the register 334 with the number of the access requests 320a transmitted. When the two values match, that is, when an access request for the designated vector length is sent, an instruction processing end notification signal 336a is sent to the vector instruction execution control device, and the busy flip-flop 332 is sent. The value of the reset and execution vector length register 334 is initialized to "0". On the other hand, the access request 320a must be sent out while judging the processing status of the access request in the access instruction processing device. Therefore, the number of issued requests and the number of access requests sent to the main storage controller 8 are monitored so that the request buffer 39a at the final stage of the access instruction processor 3 does not overflow. I have. The value of the buffer account register 337 is initially reset to "0". When the access request 320a is transmitted, the count value is set to "+1" by the adder 338 and set in the register 377. The comparison circuit 339 compares the value of the register 337 with the number of request buffers 39a (four in this embodiment).
The transmission of the access request 320a in the AND gate 320 is suppressed. When the signal 8a indicating that one access request has been sent to the main memory control device is received from the access request sending control circuit 34, the adder 338 sets the register 3
Reduce the number of access requests in 37 by one.

FIG. 5 shows details of the access request transmission control circuit 34.

In FIG. 5, a code (including conflict information), an address, data, etc. accompanying an access request 34a sent from a stage in the access instruction processing device 3 are set in a request buffer 39a and a register 39b. You. The buffer position set at this time is indicated by a signal obtained by decoding the value of the in-pointer register 340 by the decoding circuit 342, and the value of the in-pointer is determined by the access request.
Each time 34a is sent, "+1" is added in the adder 341. Note that the in-pointer register 340 takes a value from "0" to "3", and after "3", it is wrapped around to "0". The access request set in the buffer 39a and the register 39b is fetched from the buffer position indicated by the signal obtained by decoding the value of the out pointer register 343 by the decoding circuit 345 through the selection circuits 390 and 391. The access request fetched from the buffer 39a and the register 39b is sent as an access request 350a to the main storage controller 8 via the AND gate 350 unless conflict information is provided.
At the same time, a code, an address, data, and the like accompanying the access request are sent from the buffer 390a and the register 391a to the main storage controller 8. Access request sent 35
0a is not always immediately accepted by the main storage control device 8 due to the state of the main storage device or a conflict with another access request. For this purpose, the main memory control device 8 has a priority determining circuit therein, takes priority in the circuit, and returns an accept signal 8a notifying the priority. Upon receiving the accept signal 8a, the access request transmission control circuit 34 sets the value of the out-pointer register 343 to "+1" by the adder 344, and the access command control circuit 33 has processed one access request. This is notified by transmitting the above-mentioned accept signal 8a as it is. On the other hand, when the detection circuit 346 detects that the access request fetched from the buffer 39a and the register 39b is a request with conflict, the transmission of the access request 350a is blocked through the inversion gate 347 and the OR gate 349. However, even in this case, if the conflict information count register 351 is not "0", the access request 350a is transmitted. At the same time, the value of the conflict information count register 351 is reduced by “1” through the adder 352.
“1” is added to the value of the conflict information count register 351 by the conflict resolution notification 241a from the instruction activation management circuit.

The above is the configuration and operation outline of the vector instruction execution control device and the access instruction processing device in the present invention.
Next, the flow of processing will be described with reference to one vector instruction sequence.

As a vector instruction sequence, consider the following instruction sequence in which the above-described Load / Store instruction is executed twice.

First, the first Load instruction is executed by the access instruction processor 3
And executed. Store instruction is preceded by Load
Although the instruction and the vector register to be used are the same, an access instruction for writing from the vector register VR0 to the main storage device by a chaining process (not shown) that defines writing to reading from the vector register as a series of processes. The processing is performed by the processing device 4. Next, 2
When trying to execute the first Load instruction, the first Load instruction
While the processing of the instruction is not completed, the management circuit 220 of the pipeline processing mechanism activates the instruction to indicate that the pipeline processing mechanism 3 is in use.
1. Suppressed through NOR gate 214 and decoding circuit 215. 1
When the processing of the second Load instruction is completed and the management circuit 220 indicates that the access instruction processing device 3 has become “empty”, the factor for inhibiting the instruction activation related to the pipeline processing mechanism is removed. On the other hand, the conflict of the vector register is not resolved until the processing of the first Store instruction is completed. However, in the case of the above-described embodiment, it is assumed that the conflicting instruction has not been executed at this time. Therefore, the activation signal 215a can be transmitted to the access instruction processing device 3 by adding the conflict presence signal 212a. Therefore, when the start signal to which the conflict presence signal 212 is added is sent to the access instruction processing device, the flip-flop indicating that the conflict presence instruction is being executed is set to "1" at the same time.
As a result, the subsequent conflicting instruction is the first St instruction
The reading operation from the vector register by the ore instruction is completed, and the operation is suppressed until the conflict is resolved.

The access instruction control circuit 33 of the access instruction processing device 3 having received the activation signal 215a flows the access request through the pipeline. However, conflict start information is added to the start signal, and the start signal is set in the code register 330. The access instruction control circuit 33 adds the conflict existence information to the head access request of the instruction and does not add it thereafter. Therefore, the transmission of the head element and resetting of the conflict existence information of the code register 330 by the signal 320a.

The access request sending control circuit 34 buffers the access request flowing from the upstream stage into a buffer 39a and a register 39b.
At the same time, the access request in the buffer 39a and the register 39b is taken out, and it is checked whether or not there is conflict information. Conflict presence information is added to the first access request corresponding to the second Load instruction, and if the conflict resolution notification 241a has not been sent from the instruction activation management circuit 21 at this time, that is, the conflict information count register 351 Indicates “0”, the access request 350
The transmission of a is suppressed, and the processing of the access instruction processing device 3 is stopped in this access request stage. On the other hand, when the reading of VR0 by the first Store instruction is completed, the notification is sent to the instruction activation management circuit 21, and the conflict resolution notification 241a is sent to the access instruction processing device 3 via the comparison circuit 240 and the AND gate 241. You. When the access transmission control circuit 34 receives the conflict resolution notification 241a, the circuit 34 sets the value of the conflict information count register to "1". This allows
The transmission of the inhibited access request 350a is restarted, the value of the conflict information count register 351 is reduced by "1", and the processing of the stopped access instruction processing device is restarted.

If the conflict resolution notification 241a arrives at the access transmission control circuit earlier than the access request with conflict information, the main memory is immediately stored when the access request with conflict information is fetched from the buffer 39a and the register 39b. The access request 350a is sent to the control device 8, and the conflict information count register 351 is sent.
Is reduced by “1”, and the conflict-related processing ends.

As described above, it is possible to realize a control method for processing a conflicting instruction to a stage in the middle of the pipeline.

〔The invention's effect〕

As described above, according to the present invention, even if a resource (a vector register, a pipeline processing mechanism, etc.) used by an instruction to be executed is already used (a conflict state) by a preceding instruction, the resource is Can be processed up to the stage immediately before the stage in which the instruction is actually used, so that the instruction can be processed without generating unnecessary idle time of the pipeline processing mechanism. Further, it is possible to avoid a situation in which the instruction following the conflicting instruction is excessively waited for the execution of the preceding instruction, and it is possible to suppress the occurrence of useless idle time in issuing the instruction.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a vector instruction execution control device and an access instruction processing device according to the present invention, FIG. 2 is a block diagram showing an overall configuration of the vector processing device, and FIG.
FIG. 4 is a block diagram showing the configuration of the vector instruction execution control device, FIG. 4 is a block diagram showing the configuration of the access instruction control circuit, and FIG. 5 is a block diagram showing the configuration of the access transmission control circuit. 1 ... Scalar processing unit, 2 ... Vector instruction execution controller, 3,4 ... Access instruction processor, 5,6 ... Calculator, 7 ... Vector register, 8 ... Main memory controller,
9: Main memory device, 20: Instruction register, 21: Instruction activation management circuit, 22: State management circuit, 33: Access instruction control circuit, 34: Access request transmission control circuit, 213:
Conflicted instruction execution display flip-flop, 21
0, 212, 219: decoding circuit, 220: pipeline processing mechanism state management circuit, 221: vector register state management circuit, 240: comparison circuit for creating a conflict resolution signal, 351
… Conflict information count register 346… Conflict presence information detection circuit 353… Non-zero detection circuit

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-118977 (JP, A) JP-A-58-114274 (JP, A) JP-A-63-127368 (JP, A)

Claims (3)

(57) [Claims] A vector register for holding data of a plurality of elements, and a plurality of pipeline processing mechanisms for continuously processing the plurality of elements with respect to the data held in the vector register; In a vector processing apparatus that allocates and processes individual vector instructions to each pipeline processing mechanism, a lift state is detected in which a resource specified by an instruction allocated to each pipeline is being used by a preceding instruction. A conf lift detecting mechanism, a mechanism for adding conf lift information indicating the conf lift state to the element of the instruction and sending the information to the pipeline processing mechanism when the conf lift state of the resource is detected, and When the cancellation of the lift state is detected, this cancellation information is sent to the pipeline. The pipeline processing mechanism, when detecting the lift information added to the instruction, stops the pipeline processing of the instruction at a specific stage, and is notified of the lift cancellation. And restarting the pipeline processing that has been stopped. 2. The pipeline processing mechanism includes a counter controlled by the lift cancellation notification and the end of processing of the instruction with the lift information, and the pipeline processing mechanism continuously and continuously sends the pipeline processing mechanism according to the value of the counter. 2. The control method for a vector processing device according to claim 1, wherein execution of a plurality of instructions to be sent is controlled. 3. The counter counts up (or down) in response to the lift lift elimination notification, and counts up in response to processing of the lift lift information instruction.
When the value of the counter is not a predetermined value, the pipeline processing mechanism does not stop the pipeline processing even if the instruction with the lift information reaches a specific stage. 3. The control method for a vector processing device according to claim 2, wherein the processing of the instruction with the lift information is stopped at a specific stage when the value of is a predetermined value.