JP2715893B2 - Electronic clock - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the construction of a power supply section in an electronic timepiece such as a quartz timepiece using electric energy as an energy source. In particular, the present invention relates to an improvement in a power supply unit of an electronic timepiece having a power supply in which the discharge characteristics of the power supply are not flat and the voltage changes as the discharge proceeds. 2. Description of the Related Art A conventional electronic timepiece, such as a quartz timepiece, which uses electric energy as an energy source, uses a power source having flat discharge characteristics, such as a silver battery, as its power source. This made full use of the energy of the power supply. [0003] However, silver batteries are expensive and have a drawback such as a long life of the batteries themselves. In recent years, alkaline manganese batteries and the like have been used as solutions to these problems, and the life of the batteries themselves has been reduced by using a solar battery as a power source.
Timepieces using high-capacity capacitors as secondary batteries have also been proposed. [0005] According to the above technique, the alkaline manganese battery does not have a flat discharge characteristic and has a large amount of energy even after the operation of the timepiece is stopped. I can't say it. 2
In the case of using a high-capacity capacitor as a secondary battery, the duration of time until the stop of the timepiece is naturally determined by the discharge characteristics of the capacitor, which has been a major problem in practical use. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional drawbacks and to make full use of the electric energy of the power supply even if a power supply that waits for non-flat discharge characteristics is used. [0007] Means for generating electric energy include a power supply A comprising a secondary battery for charging the electric energy, and a power supply B having a smaller electric energy capacity than the power supply A. A plurality of power supplies, and an auxiliary capacitor charged with the energy from the power supply A,
The connection relationship between the power supply A and the auxiliary capacitor is arbitrarily connected in parallel or in series, and the voltage level supplied from the power supply A to the power supply B is determined in advance.
It is characterized in that the voltage is raised to a predetermined voltage level . An embodiment of the present invention will be described with reference to the drawings. This embodiment is a timepiece using a solar battery as a power generation mechanism and an electric double layer capacitor as a secondary battery as a secondary battery. FIG. 1 shows the discharge characteristics of the electric double layer capacitor, and FIG. 2 is a block diagram of an embodiment according to the present invention. FIG. 3 is a circuit diagram of a conventional system. Conventionally, in FIG. 3, when the electric power generated by the solar battery 1 is charged to the electric double layer capacitor 12 and charged to the rated voltage or more, the limiter switch 13 is closed to stop charging the capacitor 12. The clock 14 operates using the solar battery 11 or the condenser 12 as a power supply. The diode 15 is a backflow prevention diode that prevents current from flowing into the solar battery when the generated electromotive voltage of the solar battery 11 becomes equal to or lower than the charging voltage of the capacitor 4. The discharge characteristics of the capacitor 12 after the light shines on the solar battery 11 when the capacitor 12 is fully charged are shown by the solid line Vss2 in FIG.
And a broken line V'ss1. The vertical axis is condenser 1
The voltage on the horizontal axis is time. The rated voltage of the capacitor in this embodiment is 1.8V. The operation stop voltage of the clock body is 0.9 V. At this time, the operation of the clock stops at time t2 after the solar battery stops emitting light. FIG. 2 is a block diagram of an embodiment according to the present invention. The electric power generated by irradiating the solar battery 1 with light is charged into the electric double layer capacitor 4 through the backflow prevention diode 3. At this time, if the generated electromotive voltage (Vssl) of the solar battery 1 becomes higher than the rated voltage, the limiter circuit 2 operates to stop charging the capacitor 4.
For example, the rated voltage is the rated voltage of the capacitor 4,
The limiter circuit is composed of a constant voltage diode.
When the voltage between D and VSSl becomes equal to or higher than the rated voltage, a current is supplied to bypass the charging current, or a switch is provided between VDD and VSS1 to bypass the charging current by detecting a reference voltage. The electric power charged in the capacitor 4 is optimally boosted by the multi-stage boosting charging circuit 5 and charged in the capacitor 6. A detailed description of this operation will be described later. The capacitor 6 serves as a power supply for a voltage detection circuit 7 for detecting the voltage VSS1 'of the capacitor 4, a control circuit 8 for causing the boost charging circuit to perform optimum boost charging based on the voltage detection output, and a clock circuit 9. Next, the operation of this embodiment will be described in detail with reference to FIG. Here, the broken line in FIG. 1 indicates the absolute value of the voltage VSS′1 of the large-capacity capacitor 4, and the solid line indicates the absolute value of the voltage VSS2 of the capacitor 6. A description will be given of a case where light does not shine on the solar battery 1 after the capacitor 4 is fully charged. When the voltage | VSS'1 | of the capacitor 4 is 1.2 V or more, the capacitor 4
The boost charging circuit 5 operates so that the voltage of the capacitor 6 and the voltage of the capacitor 6 become the same. Voltage of capacitor 4 | VSS'1 |
Is between 1.2V and 0.8V, the voltage is boosted twice by the boosting charging circuit 5 to charge the capacitor 6. FIG. 1 t1 to t3
It is a section of. Therefore, the voltage | VSS2 | of the capacitor 6 at this time is 1.8 V to 1.2 V. When the voltage | VSS'1 | of the capacitor 4 is 0.8 V to 0.6 V, the voltage is doubled by the boost charging circuit 5 and the capacitor 6
Is charged. In FIG. 1, it is a section from t3 to t4.
At this time, the voltage | VSS2 | of the capacitor 6 is 1.6 V
It becomes -1.2V. When the voltage | VSS'1 | of the capacitor 4 is 0.6 V or less, the capacitor 6 is boosted three times by the boost charging circuit 5 and charged. This is after t4 in FIG. As described above, according to the present embodiment, the voltage | VSS2 | of the capacitor 6, which is the actual power source of the timepiece, is maintained at 0.9V or more by the boost charging means. In FIG. 1, the operable time of the clock is extended from time t2 to time t5. In addition, according to the present embodiment, the voltage of the capacitor 4 which can only be used between 0.9 V and 1.8 V is 0.3 V according to the present embodiment.
To 1.8V, and uses the energy stored in the condenser 4 effectively. Next, a multi-stage boosting charging circuit 6, a voltage detecting circuit 7 in this embodiment. A specific example of the control circuit 8 will be described. FIG. 4 shows a basic form of the multi-stage boosting charging circuit 6, and FIG. 5 specifically shows the operation thereof.
(A) is a step-up operation, and (B) is a charging operation. The capacitors 4 and 6 in FIGS. 4 and 5 deviate from those in FIG. 2, and the capacitors 21 and 22 are auxiliary capacitors for boosting. Tr1 to Tr7 in FIG. 4 are FETs, and play the role of a switch for boosting the voltage. In FIG. 4, in order to make vsss'1 and vss2 the same potential without boosting, Tr3 and Tr4 may be turned on and the others may be turned off. FIG. 5A shows this state.
This is an operation at t0 to t1 in FIG. Also, t1 to t
For the 3 performing 1.5-times boosting charge is raised during Tr1, Tr3, Tr6 ON and OFF the other of the charging time T
r2, Tr4, Tr5, Tr7 are turned on and others are turned off. Similarly, in order to perform double boost charging at times t3 and t4, Tr1, Tr3, Tr5 and Tr7 are turned on during boosting and the others are turned off. In order to perform the operation and further perform the triple boosting at t4 to t5, the same operation as the double boosting charging is performed at the time of boosting, and Tr2, Tr4, Tr6 are turned on and the others are turned off at the time of charging. . When each FET is controlled as described above, the state shown in FIG. 5 is obtained, and each boosting charge becomes possible. FIG. 6 shows an embodiment of the multi-stage boosting charging circuit 5 which specifically realizes the above with an electronic circuit. In FIG. 6, capacitors 4, 6, 21, and 22 and FETs Tr1 to Tr7 are shown in FIG.
Is similar to However, Tr5, Tr6, Tr7
Since the current flows in both directions, a P-channel FET and an N-channel FET are combined. Also, φcl
Is a boost charge clock, and the logic level of the signal is "L"
At this time, boosting is performed, and at "H", charging is performed. Therefore, the circuit repeats boost charging in accordance with the cycle of φcl. AmpN, Amp1.5, Amp2, A
mp3 is a signal indicating a boosting factor, and when "H", indicates no boosting, 1.5-fold boosting, 2-fold boosting, and 3-fold boosting, respectively. Also, 61-
Reference numeral 64 denotes a known logic gate, and the ON / OFF timing of the FETs Tr1 to Tr7 is made by these gates, and the operation described with reference to FIGS. 4 and 5 is performed. Next, FIG. 7 shows a specific example of the voltage detection circuit 7. sp 'is a sampling signal, and when "H", the circuit operates, and when "L", the circuit state is fixed so that current is not consumed. The inside of the broken line is a known constant voltage circuit, and its output voltage is represented as VREG. Further, R1 and R2 are resistors, and have a maximum voltage of 1.8V of | VSS1 |. | VREG | = | VM | = R1 / (R1 + R2) × | VSS1 | = R1 / (R1 + R2) × 1.8 (1) It is set so as to satisfy the following. r1,
r2, r3, and R are similarly resistors, and | VS
The potential of the | VM | tap when S′1 | becomes 0.6 V, 1.8 V, and 1.2 V is set to be the same. One of the three tap potentials is selected by the transmission gate 71 (VREGT),
The data is compared with VM by the comparator 72. Comparator 7
2 is configured to output “H” when VM is lower than the selected tap potential, and to output “L” when the opposite is true and when SP ′ is “L”. Output co
mp is sent to the control circuit 8. T1.5, T2 and T3 are signals for selecting a transmission gate and are formed by the control circuit 8, and when "H", the transmission gate is turned on.
With the above configuration, VM and VREGT are compared, and the result (comp) and the transmission selection signal (T1.
5, T2, T3), vss'1 is t0 to t in FIG.
5 can be determined. This determination is made in the control circuit 8 described later. FIG. 8 shows a specific example of the control circuit 8, and FIG.
Is a timing chart. The timing chart shows that the left side of the wavy line indicates that the 1.5 ×
A transition to the double boost control state is shown, and the movement of each signal when shifting from the double boost state to the state without boost is shown on the right side of the wavy line x. In FIG. 8, 91,
94 is a D-type flip-flop that latches data at the falling edge of CL, 92 is a master latch that holds data when CL is "L", 93 is a 2-bit binary counter, and the other are known gates. Here, the operation of this control circuit will be described along the left side of the timing chart wavy line. First, before the sampling pulse SP becomes “H”, the boosting ratio is 1.5 times and the transmission gate selection signal is T1.5 which is “H”. The states are the master latch 92 and the binary counter 93, respectively.
Is remembered. Now, at the same time that the sampling pulse SP is output, a Reset signal is output, the binary counter 93 is reset, and the state returns to the initial state where T3 becomes "H". After that, comparator output comp by CP pulse
T3, T2, and T1.5 are sequentially selected until becomes "L". The voltage of the large-capacity capacitor 4 | vss'1 |
Is between 0.6 V and 0.8 V (t3 in FIG. 1).
7 to t4), as can be understood from the description of FIG. 7, when T2 becomes “H”, the potentials of VM and VREGT are inverted and c
omp becomes “L”. Therefore, this causes vss'1
Can be determined. Because the detection voltage of T3 is 0.6
V, and the detection voltage of T2 is 0.8 V. If the output of the comparator is inverted during this period, | VSS1
Can be defined to be 0.6V to 0.8V. When | VSS'1 | is 1.2 V or more, T
1.5 is “H” and comp remains “H”.
When comp becomes "L", the subsequent CP pulse is prohibited, and the state of the transmission gate selection signal is stored in the binary counter 93. Also, | VSS '
When 1 | is 1.2 V or more, T1.5 is "H" and comp remains "H". Therefore, how many times the voltage should be boosted can be determined based on the contents of the binary counter and the output of comp when the CP pulse has been output. The decision is made by the D-type flip-flop 94, the master latch 92, and some gates, and the operation is performed at the fall of SP. As described above, according to the present embodiment, the operable time of the timepiece is extended from time t2 to time t5 in FIG. Moreover, co-use according conventional 0.9V speaking at a voltage of the capacitor 4 in the present embodiment that was used only between 1.8V from 0.3V to 1.8V
It is clear that the energy stored in capacitor 4 is being used effectively. In this embodiment, three types of boosting means, 1.5 times, 2.0 times and 3.0 times, are provided in 5 in FIG. Although the present invention is switched and used, the present invention is not limited to these three types, and one type or many types may be prepared, and various magnifications may be considered. In this embodiment, the voltage is detected by detecting the voltage of the capacitor 4 (1.8, 1.2,
Of course, a method of detecting the voltage of the capacitor 6 (0.8 V, 0.6 V) (1.8 V, 1.2 V) and comparing the content of the booster 5 to determine the boosted state is also possible. This method has an advantage that the detection voltage may be small. In addition, the power generation unit 1 is not limited to a solar battery, and may be anything that generates power. In addition, as described above, the effects of the present invention are not lost even when a normal battery is formed by combining 1 and 2. In FIG. 1, the clock stops when v'ss1 is between 0.3 V and OV, and the oscillation circuit of the clock stops the oscillation. When the oscillation stops, the clock signal for boosting stops being generated, so that the boosting operation also stops. If the solar cell 1 and the charging circuit are connected in this state, even if the solar cell is irradiated with light, current flows only into the charging circuit, and the oscillation circuit does not immediately oscillate. As a result, the booster circuit also operates. You don't need a clock. In order to solve such a problem, when the oscillation of the oscillation circuit stops, the connection between the solar cell and the charging circuit may be disconnected, and the solar cell and the oscillation circuit may be directly connected. A specific example will be described with reference to the example of FIG. In FIG . 10, reference numeral 102 denotes a clock circuit. The limiter circuit 2 in FIG. 2 is removed for simplification of description, and the multi-stage booster circuit 5, the voltage detection circuit 7, and the control circuit 8 are simplified as a booster circuit 119 and a logic circuit 118. [0031] with the following FIG. 10 a description of the power control. First, the secondary battery 103 (condenser) is set to a low voltage state (0.3 V or less). If the oscillation signal 123 of the oscillation circuit 108 is oscillating, the oscillation stop detection circuit 117 detects the stop, the control signal 113 becomes L, the transmission gate 114 is turned on, and the transmission gates 115 and 10
5 becomes OFF. Therefore, the power supply 120 of the oscillation circuit 108
Are turned off with the boosted power supply 121 by the booster circuit 119 and turned on with the solar cell side power supply 122.
When light is applied to the oscillation circuit 108, the oscillation stop detection circuit 11
7. An oscillating voltage is supplied to the logic circuit 118 to start oscillating. When oscillation starts, a boosting clock 124 necessary for boosting is generated, and the boosting circuit 119 causes the secondary battery 103
, And a high voltage is generated in the boost power supply 121.
On the other hand, when the oscillation starts, the transmission gate 114 is turned off and the transmission gate 11 is turned off.
5 and 105 are turned ON, the power supply system of the clock circuit 102 is configured such that the solar cell 101 charges the secondary battery 103,
The clock circuit 102 operates by the high voltage obtained by boosting the pond 103 . That is, even if the voltage of the secondary battery is low, the watch operates immediately. As described above, according to the present invention, the voltage level of the electric energy of the power supply A can be predetermined.
Voltage to the power supply B
The energy of the power supply A can be used as a clock drive source without waste. As a result, the duration of the power supply of the electronic timepiece that does not require battery replacement can be dramatically increased. Also, batteries such as alkaline manganese batteries and lithium batteries can be utilized with little energy loss.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining the discharge characteristics of a capacitor and the effects of the present invention. FIG. 2 is a block diagram of one embodiment according to the present invention. FIG. 3 is a diagram showing a conventional example. FIG. 4 is a diagram showing a basic form of a multi-stage booster circuit. 5A to 5D are diagrams showing specific examples of the operation in FIG. 4; 5 (B) to 5 (D), (A) shows a boosting operation, and (B) shows a charging operation. [FIG. 6] A diagram showing an embodiment as an electronic circuit. FIG. 7 is a diagram showing a specific example of a voltage detection circuit. FIG. 8 is a diagram showing a specific example of a control circuit. FIG. 9 is a timing chart of a control circuit. FIG. 10 is a block diagram showing an application example of the present invention. [Description of Signs] 1 ... Solar battery 2 ... Limiter circuit 4 ... Condenser 5 ... Boosting means 9 ... Watch body

Claims (1)

(57) [Claims] Means for generating electric energy, a plurality of power supplies including a power supply A comprising a secondary battery for charging the electric energy, and a power supply B having a smaller electric energy capacity than the power supply A; An auxiliary capacitor to be charged, wherein the connection between the power supply A and the auxiliary capacitor is arbitrarily connected in parallel or in series, and a voltage level supplied from the power supply A to the power supply B is predetermined. An electronic timepiece characterized by being boosted to a given voltage level .