JP2712730B2 - Evaluation chip - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an evaluation chip, and more particularly, to an evaluation chip that emulates a reset function of a single-chip microcomputer.

[Conventional technology]

The reset function of conventional single-chip microcomputers includes a central processing unit (hereafter CP
Write U. ) Immediately starts operation (hereinafter referred to as reset mode 1), and a method in which the CPU starts operation after counting the oscillation stabilization time of the oscillator after reset input is released (hereinafter referred to as reset mode 2). There is.

In reset mode 1, the oscillation stabilization time is not counted by the built-in counter after reset input is released, and
Since the CPU starts operation immediately after the reset input is released, it is possible to reduce the time required for the rise at the time of reset in the application system.

However, in resetting at power-on, since a reset signal having a time width including the oscillation stabilization time of the oscillator is input, it is necessary to externally configure a reset signal generation circuit.

Therefore, there is a disadvantage that the number of components increases in the application system, so that the mounting area increases and the cost increases.

In reset mode 2, there is no need to configure an external circuit for generating a reset signal having a time width including the oscillation stabilization time. Therefore, the number of components can be reduced in an application system, and the mounting area and cost can be reduced. is there.

However, if the oscillation stabilization time has not elapsed at reset,
It has the disadvantage that U does not work. In particular, the oscillation stabilization time is usually as long as 10 ms, which poses a problem when it is necessary to start operation immediately after reset release. That is, in a product in an application field in which the system must be started immediately and real-time properties are required, the reset mode 1 in which the oscillation stabilization time is not counted inside the single-chip microcomputer because the system must be started in a short time.
Is useful.

Also, in the consumer products that do not require much real-time performance, there is a strong demand for lowering the product unit price, and it is necessary to reduce the cost.

Therefore, since the oscillation stabilization time counter is not required externally, the reset mode 2 that can reduce the mounting cost is useful.

Conventionally, there are two types of reset methods of a single-chip microcomputer described above, and emulation of each reset method is performed by each individual evaluation chip.

The structure and operation of a conventional evaluation chip of a single-chip microcomputer having a built-in reset mode 2 will be described with reference to FIGS.

First, the configuration of the evaluation chip
This will be described with reference to the drawings.

FIG. 4 is a block diagram of an evaluation chip of a conventional single-chip microcomputer. The evaluation chip 400 includes a CPU 420 and a memory 430.
, Peripheral circuit 410, internal bus 440, standby circuit 45
0, an oscillation circuit 460, a reset circuit 470, a terminal 480, a terminal 481, and a ▲ ▼ terminal 490. The internal bus 440 is an address data bus that connects the CPU 420, the memory 430, and the peripheral circuit 410.

The oscillation circuit 460 connects an oscillator to the terminals 480 and 481 to perform an oscillation operation, and supplies an internal clock signal 461 to the standby circuit 450 and the reset circuit 470.

In addition, the oscillation operation is stopped by the pulse output of the standby signal 421, and the oscillation operation is started by the level detection signal 472.

The standby circuit 450 is a circuit that performs clock output control during standby and receives an internal clock signal 461 as an input and receives a pulse-like overflow signal 473 and supplies an internal clock signal 451 to the peripheral circuit 410, the CPU 420, and the memory 430.

The reset circuit 470 generates an internal reset signal 471 based on the negative logic reset signal 491 and the internal clock signal 461 input to the terminal 490 and outputs the signal to the peripheral circuit 410, the CPU 420, and the memory 430.

When the internal reset signal 471 is “1”, the peripheral circuit 410 and CPU4
20 and the memory 430 are in a reset state, and when "0", the reset state is released. The reset circuit 470 outputs a level detection signal 472 to the oscillation circuit 460, and outputs the overflow signal 47
3 is output to the standby circuit 450. Peripheral circuit 410
Performs each peripheral operation in synchronization with the internal clock signal 451. The CPU 420 is a central processing unit that controls the evaluation chip 400, and outputs a standby signal 421 to the standby circuit 4.
50 and output to the oscillation circuit 460. Standby signal 421
Is a pulse signal output by execution of the dedicated instruction.

The memory 430 stores programs and data to be fetched and executed by the CPU 420.

FIG. 5 shows a block diagram of the reset circuit 470, and mainly the reset function will be described.

 First, the configuration will be described.

The reset circuit 470 includes a low level detection circuit 500, a rising edge detection circuit 510, an oscillation stabilization time counter 520, and an SR.
It is composed of a flip-flop 530 and an AND gate 540.

The low-level detection circuit 500 receives the reset signal 491, sets the level detection signal 472 to “1” by detecting the low level, and changes to “0” when the edge detection signal 511 is received.

The oscillation circuit 460 starts an oscillation operation in synchronization with the rise of the level detection signal 472 and supplies an internal clock signal 461.

The rising edge detection circuit 510 outputs the reset signal 491
When the rising edge of the reset signal 491 is detected, a pulse-like edge detection signal 511 synchronized with the rising edge of the internal clock signal 461 is output. The AND gate 540 receives the input of the internal clock signal 461 and the inverted signal of the level detection signal 472, and outputs the level detection signal 4
When 72 is “0”, the internal clock signal 461 is output as the output signal 541. The oscillation stabilization time counter 520 starts the counting operation in synchronization with the output signal 541 when the level detection signal 472 becomes “0”. When the counter overflows, an overflow signal 473 is output to clear the counter and stop the operation. The standby circuit 450 starts supplying the internal clock signal 451 by the pulse output of the overflow signal 473. The SR flip-flop 530 uses the level detection signal 472 as a set input and the overflow signal 473 as a reset input, and receives an input pulse to set an internal reset signal.
471 is set to “1”, and set to “0” when a reset input pulse is received.

Next, the operation of the reset circuit 470 will be described mainly with reference to the timing chart of FIG.

FIG. 6 is a timing chart when the stop state of the evaluation chip 400 is released by a reset input signal. First, the transition operation to the stop state will be described. CPU 420 executes the dedicated instruction to execute the standby signal.
421 is output. Upon receiving the standby signal 421, the standby circuit 450 stops supplying the internal clock signal 451,
At the same time, the oscillation circuit 460 stops the oscillation operation and sets the evaluation chip 400 to the stop state.

Next, the release operation in the reset mode 2 in the stop state will be described.

When the reset signal 491 becomes “0”, the low level detection circuit 500 detects the low level and sets the level detection signal 472 to “1”. When the level detection signal 472 becomes “1”, the SR flip-flop 530 is set. Therefore, the internal reset signal 471 becomes “1”, and the CPU 420, the peripheral circuit 410, and the memory 430 are reset. At the same time, the level detection signal 4
The oscillation circuit 460 starts the oscillation operation in synchronization with the rise of 72. Next, when the reset signal 491 changes from “0” to “1”, the rising edge detection circuit 510 detects a rising edge and outputs an edge detection signal 511. When the low-level detection circuit 500 receives the edge detection signal 511, the low-level detection circuit 500
To “0”. When the level detection signal 472 becomes “0”, AND
The gate 540 supplies the internal clock signal 461 as an output signal 541 to the oscillation stabilization time counter 520 to start the counting operation. The oscillation stabilization time counter 520 outputs an overflow signal 473 upon completion of the oscillation stabilization time counting, and stops the counting operation. The SR flip-flop 530 is reset by the overflow signal 473. Therefore, the internal reset signal 451 becomes “0”. At the same time overflow signal 473
Accordingly, the standby circuit 450 supplies the internal clock signal 451. Therefore, the reset state of the CPU 420, the peripheral circuit 410, and the memory 430 is released when the internal reset signal 471 becomes “0”.

After releasing the reset state, the CPU 410 starts executing the program stored in the memory 420 in synchronization with the internal clock signal 451.

Since the oscillation circuit normally requires several tens of milliseconds from the oscillation stop state to the start of oscillation and stabilization, the oscillation stabilization time counter is set to count a time corresponding to the oscillation stabilization time. Therefore, in the conventional reset method using the reset circuit, the CP is released after the reset input is released.
Since the oscillation stabilization time must be waited for U to start operation, a product incorporating the reset mode 1 cannot be emulated with the conventional evaluation chip.

[Problems to be solved by the invention]

The evaluation chip with a built-in conventional reset circuit described above is a product with a built-in reset method in which the CPU starts operating immediately after reset input is released because the CPU starts operation after counting the oscillation stabilization time after reset input is released. However, there is a drawback in that emulation of the device cannot be performed, and a new evaluation chip must be developed.

[Means for solving the problem]

An evaluation chip of the present invention is an evaluation chip including a central processing unit, and a reset circuit that receives a reset signal and supplies an internal reset signal to the central processing unit in response to the reset signal, wherein the reset circuit includes: A mode setting register in which the set value is stored by the central processing unit, means for resetting the central processing unit when the reset signal is active, and output in response to the reset signal changing from active to inactive Means for generating a second signal that is output after a predetermined time from when the first signal and the reset signal become inactive from active, and receives the first signal and the second signal, A selector for selecting and outputting either the first signal or the second signal in response to the set value; Means for canceling the reset state of the central processing unit.

That is, the above-described evaluation chip incorporating the reset circuit starts operation of the CPU after the oscillation stabilization time elapses after reset release, whereas the evaluation chip incorporating the reset circuit according to the present invention includes a mode setting register. And a selector, and the selector has a function of starting the operation of the CPU by selecting either the first signal or the second signal according to the mode of the mode setting register. Since the CPU can start operation immediately after reset input is released, both reset methods can be selected. Therefore, products incorporating each reset method can be emulated with the same evaluation chip.

〔Example〕

 FIG. 1 is a block diagram showing a reference example of the present invention.

The configuration and operation of an evaluation chip incorporating a reset circuit according to a reference example will be described with reference to FIG.

The evaluation chip incorporating the reset circuit of the reference example has an external terminal for switching the reset method, and has a feature that the reset method of the evaluation chip can be switched by a signal level input to the external terminal. The evaluation chip of the first embodiment is different from the conventional example only in that the mode selection terminal 100 and the selector 110 are added. Therefore, the description of the same components as those of the conventional example is omitted, and only the differences are described. Will be described. The mode selection terminal 100 is an external input terminal for selecting a reset method of the evaluation chip 400. When the mode selection terminal 100 is “1”, the mode signal 101 becomes “1”, and when it is “0”, the mode signal 101 becomes “0”. The selector 110 selects the edge detection signal 511 or the overflow signal 473 according to the mode signal 101 and outputs the output signal 111. The mode signal 101 is "1".
The edge detection signal 511 is selected at the time, and the overflow signal 473 is output at the time of "0". The output signal 111 is a standby circuit
The standby circuit 450 starts supplying the internal clock signal 451 according to the output signal 111.

Next, a reset operation of the evaluation chip of the reference example will be described with reference to FIG. 2 and FIG. In addition,
The operation of transition to the stop state is the same as that of the conventional example, and therefore will be omitted, and only the operation at the time of release will be described. The mode selection terminal 100 of the evaluation chip 400 is set to “1” or “0” in advance according to the reset method of the emulated product.

First, the emulation of the reset mode 2 will be described with reference to FIG.

Set the mode selection terminal 100 to “0”. Since the mode selection terminal 100 is “0”, the mode signal 101 becomes “0”, and the selector 110 selects the overflow signal 473. The selector 110 outputs the overflow signal 473 as the output signal 111 to the reset input of the SR flip-flop 530. The operation of the selector 110 after the selection of the input signal is as shown in FIG. (However, the overflow signal 473 in FIG. 6 is the same as the output signal 111 here.) Therefore, the evaluation chip 400 performs the reset operation in the reset mode 2.

Next, the emulation of the reset mode 1 will be described with reference to FIG.

Set the mode selection terminal 100 to “1”. Since the mode selection terminal 100 is “1”, the mode signal 101 becomes “1”, and the selector 110 selects the edge detection signal 511. The selector 110 outputs the edge detection signal 511 to the reset input of the SR flip-flop 530 as an output signal. When the reset signal 491 becomes “0”, the low-level detection circuit 500
Detects the low level and sets the level detection signal 472 to “1”. The level detection signal 472 sets the SR flip-flop 530 in synchronization with the rise. Therefore, the internal reset signal 471 becomes “1”, and the CPU 420, the peripheral circuit 410, and the memory 43
0 is reset. At the same time, in synchronization with the rise of the level detection signal 472, the oscillation circuit 460 starts the oscillation operation and supplies the internal clock signal 461. Next, reset signal 491
Rising edge detection circuit 510 when "1" changes from "0" to "1"
Detects a rising edge and outputs an edge detection signal 511. Low level detection circuit 5 by edge detection signal 511
00 sets the level detection signal 472 to “0”. Edge detection signal 5
11 is output as output signal 111 and SR flip-flop 520
Reset. Therefore, the internal reset signal 471 becomes “0” in synchronization with the rise of the internal clock signal 461.
At the same time, the standby circuit 450 supplies the internal clock signal 451 to the CPU 420, the peripheral circuit 410, and the memory 430 by the output signal 111.

The reset state is released when the internal reset signal 471 becomes “0”.

As described above, the evaluation chip 400 performs the reset operation in the reset mode 1, and when the reset input is released, the CPU 420 immediately starts the program execution operation.

Therefore, the evaluation chip 400 is set to the reset mode 1 by setting the mode selection terminal 100 in addition to the conventional example.
Emulation can be performed by the reset method described above.

FIG. 3 is a block diagram showing a first embodiment of the present invention.

The configuration and operation of an evaluation chip incorporating a reset circuit in the first embodiment will be described with reference to FIG.

The evaluation chip having a built-in reset circuit according to the present embodiment includes a mode selection register for switching the reset method, and has a feature that the reset method can be switched by the set value of the mode selection register.

The evaluation chip incorporating the reset circuit of the first embodiment is different from the first embodiment in that the mode terminal 100
Only the difference between the present embodiment and the mode selection register 300 is described below. The mode selection register 300
Connected to the CPU 420 via the internal data bus 440,
This is a 1-bit register for selecting the reset method of the evaluation chip 400. Mode select register
Data is set to 300 by a dedicated instruction. Mode signal 3
02 is “1” when the mode selection register 300 is “1”,
This signal is “0” when “0”. Write signal 301 is CPU42
0 is a write signal to the mode selection register 300 that is output, and when "1", data is written. The selector 110 selects the edge detection signal 511 when the mode signal 302 is “1”,
When "0", the overflow signal 473 is selected.

Normally, the evaluation chip sets data in the mode selection register 300 in advance in order to set the mode register corresponding to the function of the product to be emulated in advance. The setting of the mode selection register 300 is set by the monitor program of the emulator.

The mode selection register 300 is a register that can be written only by the emulator.
▼ Not cleared by reset input to terminal 490.

Next, the operation of the first embodiment will be described. The emulation of the reset mode 1 will be described. The dedicated signal sets the write signal 301 to “1” and sets “1” in the mode selection register 300. Mode selection register 300 is "1"
As a result, the mode signal 302 becomes “1”, and the selector 110 selects the edge detection signal 511. Therefore, the evaluation chip 400 performs the reset process in the reset mode 7 method.

Next, the emulation of the reset mode 2 will be described. The write signal 301 is set to “1” by the dedicated instruction, and “0” is set to the mode selection register 300. Since the mode selection register 300 is “0”, the mode signal 302 becomes “0” and the selector 110 selects the overflow signal 473.

Therefore, the evaluation chip 400 performs the reset process in the reset mode 2 method.

Evaluation chip 400 is in mode selection register 3.
By setting data in advance to 00, emulation of reset mode 1 and reset mode 2 is possible.

In the first embodiment, data is set in the mode selection register 300 using a dedicated instruction, but address mapping can also be performed.

〔The invention's effect〕

As described above, the present invention has a mode selection register and a selector in a conventional evaluation chip, and the selector sets either the rising edge detection circuit edge detection signal or the oscillation stabilization time counter overflow signal according to the setting value of the mode selection register. Select the reset processing (reset mode 1) in which the CPU starts operation immediately after the reset input is released or the reset processing (reset mode 2) in which the CPU starts operation after counting the oscillation stabilization time after the reset input is released. This has the effect of emulating two types of reset methods with the same evaluation chip.

Further, by selecting the reset processing according to the set value of the mode selection register, the same evaluation chip can emulate two types of reset methods without increasing the number of external terminals.

[Brief description of the drawings]

FIG. 1 is a block diagram of an evaluation chip according to a reference example of the present invention. FIG. 2 is an operation timing chart when the stop state is released by a reset signal in the evaluation chip of the reference example and the first embodiment.
FIG. 4 is a block diagram of an evaluation chip according to a first embodiment of the present invention. FIG. 4 is a block diagram of a conventional evaluation chip. FIG. 5 is a block diagram of a reset circuit of the conventional evaluation chip. 7 is an operation timing chart when a stop state is released by a reset signal in a conventional evaluation chip. 100: Mode selection terminal, 101: Mode signal, 110:
Selector, 111: output signal, 300: mode selection register, 301: write signal, 302: mode signal, 400:
Evaluation chip, 410 ... Peripheral circuit, 420 ...
Central processing unit (CPU), 430 memory, 440 internal bus, 450 standby circuit, 451 internal clock signal, 460 oscillator circuit, 461 internal clock signal, 470
…… Reset circuit, 471 …… Internal reset signal, 472 ……
Level detection signal, 473 overflow signal, 480 terminal, 481 terminal, 490 terminal, 491 terminal
... Reset signal, 500 ... Low level detection circuit, 510 ...
Rising edge detection circuit, 520: oscillation stabilization time counter, 530: SR flip-flop, 540: AND gate, 541: output signal.

Claims (2)

(57) [Claims] 1. An evaluation chip comprising: a central processing unit; and a reset circuit that receives a reset signal and supplies an internal reset signal to the central processing unit in response to the reset signal. A mode setting register in which a set value is stored by the central processing unit; a means for resetting the central processing unit when the reset signal is active; and a response when the reset signal goes from the active state to the inactive state. Means for generating a first signal and a second signal which are output after a predetermined time has elapsed from when the war reset signal becomes inactive from the active state, and the first signal And receiving the second signal, and selectively outputting either the first signal or the second signal in response to the set value. An evaluation chip, comprising: a selector to perform the operation; and means for receiving the output of the selector and releasing the reset state of the central processing unit. A central processing unit; an oscillation circuit for generating a clock signal by driving the central processing unit; and a reset circuit receiving a reset signal and supplying an internal reset signal to the central processing unit in response to the reset signal. A valuation chip, wherein the reset circuit receives the reset signal, outputs a level detection signal when the level of the reset signal is a predetermined level, drives the oscillation circuit, and synchronizes with an input of an edge detection signal. A level detection circuit that stops outputting the level detection signal, an edge detection circuit that detects an edge of the clock signal during a period in which the reset signal is not received, and outputs the edge detection signal in synchronization with the edge; After counting the clock signal several clocks from the stop of the output of the level detection signal, the clock signal A counter for outputting an overflow signal in synchronization with an edge of the register, a register storing a set value by the central processing unit, receiving the edge detection signal and the overflow signal, and receiving the edge detection signal and the overflow signal according to the set value. And a logic circuit for selecting and outputting any one of the following, and a logic circuit for generating the internal reset signal in response to the level detection signal and stopping the generation of the internal reset signal in response to the output of the selector, The central processing unit is in a reset state by the generation of the internal reset signal, and is released from the reset state in response to the stop of the generation of the internal reset signal,
An evaluation chip, wherein acceptance of the clock signal from the oscillation circuit is permitted.