JP2712645B2 - Motion vector transmission method and apparatus, and motion vector decoding method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial Fields B Overview of the Invention C Prior Art D Problems to be Solved by the Invention (FIGS. 19 and 20) E Means for Solving the Problems (FIGS. 15 and 16) F operation (FIGS. 15 and 16) G embodiment (FIGS. 1 to 18) (G1) Principle of video signal transmission (FIGS. 1 and 2) (G2) Configuration of embodiment (G2- 1) Configuration of transmitting device (Fig. 3) (G2-2) Motion vector detection circuit (Figs. 4 to 9) (G2-3) Run-length Huffman coding circuit (Figs. 10 to
(Fig. 16) (G2-4) Configuration of receiver (Figs. 17 and 18) (G3) Operation of embodiment (G4) Effects of embodiment (G5) Other embodiments Effects of H invention BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion vector transmission method and apparatus, and a motion vector decoding method and apparatus, and is particularly applicable to a case where a moving image video signal is subjected to highly efficient encoding processing and transmitted.

B. Summary of the Invention The present invention relates to a motion vector transmission method and apparatus, and a motion vector decoding method and apparatus, wherein a quotient and a remainder are calculated by dividing data based on a motion vector between first and second images. By calculating the quotient, the quotient is subjected to variable-length encoding using a predetermined VLC table to generate a variable-length code, and by transmitting information indicating the divisor used in the division operation, the variable-length code, and additional bits indicating the remainder, The motion vector can be optimized and transmitted with a simple configuration.

C Conventional Technology Conventionally, in a so-called moving image video communication system for transmitting a video signal composed of a moving image to a remote place, such as a video conference system and a video phone system, in order to efficiently use the transmission capacity of a transmission path, An inter-frame correlation of a video signal is used, thereby improving the transmission efficiency of significant information.

That is, the transmitting apparatus detects a motion vector between frames, and transmits deviation data between a frame image reproduced by the motion vector and the current frame image together with the motion vector.

In the receiving apparatus, the current frame image is reproduced by displacing the frame image used as the reference for the motion vector detection (hereinafter referred to as a reference frame) by the amount of the motion vector, and adding the transmitted deviation data.

With this configuration, since there is a correlation between frames in the video signal, the transmission efficiency can be remarkably improved as compared with the case where the current frame image is directly transmitted.

D. Problems to be Solved by the Invention By the way, when a motion vector is detected and a video signal is transmitted in this way, it is necessary to transmit a frame image serving as a reference for detecting a motion vector. A method of transmitting a frame image by a transmission procedure as shown in FIG. 19 can be considered.

That is, the frame image FM serving as one reference is subjected to, for example, an intra-frame encoding process and transmitted.

On the other hand, in the frame images F1, F2, F3,...
Set FM, F1, F2 ... as the reference frame and set the motion vector
V ₁ , V ₂ , V ₃ ... And deviation data are transmitted.

In this way, the frame image FM
After reproducing F1, the subsequent frame image F2 can be reproduced with reference to the reproduced frame image F1, and successive frame images can be transmitted with high efficiency.

However, in this method, since a subsequent frame image is reproduced with reference to the immediately preceding frame image, once a transmission error occurs, the error propagates to the subsequent frame image.

Therefore, for example, a transmission procedure as shown in FIG. 20 can be considered.

That is, for each predetermined frame, the frame image FM is subjected to intra-frame encoding processing and transmitted.

Further, frame images F1, F2, between the frame images FM and the frame images to be transmitted after being subjected to the intra-frame encoding process.
In F3, the motion vector and the deviation data are transmitted with reference to the frame image FM1.

In this way, error propagation can be prevented, and image quality degradation can be effectively avoided.

However, in the case of this method, for example, the frame image FM and
Among F1, when detecting the motion vector V ₁ in the range of ± 7 pixels, between the frame image F2 frame image FM and subsequent, it is necessary to detect the motion vector V ₂ in the range of up to ± 14 pixels.

In yet between the frame image FM and F3, must be the motion vector V ₃ detected in the range of up to ± 21 pixels, there is a problem that the code length of the motion vectors that amount transmitted is increased.

As one method for solving this problem, when transmitting a motion vector, a method of encoding and transmitting the motion vector so that the code length becomes shorter as the appearance probability becomes higher (that is, an optimization process). Can be considered.

However, in the case of transmitting a motion vector between one frame, two frames, and so on, the appearance probabilities of the motion vector values are different from each other.
There is a problem that it is not possible to perform an optimization process with a simple configuration so as to reduce the data amount as a whole.

The present invention has been made in consideration of the above points, and has been made in consideration of the above, and when transmitting a motion vector between a first image and a second image, a motion vector transmission that can optimize and transmit the motion vector with a simple configuration. A method and an apparatus thereof and a motion vector decoding method and an apparatus thereof are proposed.

Means for Solving E Problem In order to solve such a problem, in the present invention, the first
And a motion vector transmission method and apparatus for transmitting a motion vector between images, wherein a division operation is performed on data based on the motion vector to obtain a quotient and a remainder, and the quotient is variable using a predetermined VLC table. A variable length code is generated by performing long coding, and information indicating the divisor used in the division operation, the variable length code, and additional bits indicating the remainder are transmitted.

Further, in the present invention, the encoder performs a division operation on data based on the motion vector between the first and second images to obtain a quotient and a remainder, and encodes the quotient into a variable-length code using a predetermined VLC table. A motion vector decoding method for generating a variable length code, and decoding coded motion vector data transmitted in the form of information indicating a divisor used in the division operation, an additional bit indicating a variable length code and a remainder, and The apparatus receives information indicating the divisor used in the division operation, a variable-length code, and an additional bit indicating the remainder, and transmits the received information indicating the divisor used in the division operation, the additional bit indicating the variable-length code and the remainder. The decoding is performed to reproduce the motion vector.

Function F In the motion vector transmission method and apparatus, and the motion vector decoding method and apparatus, a division operation is performed on data based on a motion vector between the first and second images to obtain a quotient and a remainder, and the quotient is determined as a predetermined value. A variable-length code is generated by using the VLC table to generate a variable-length code, and the information indicating the divisor used in the division operation, the variable-length code, and an additional bit indicating the remainder are transmitted, so that the motion vector can be simplified. Can be optimized and transmitted.

G Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

(G1) Principle of video signal transmission When the video signal encoding method according to the present invention is applied to a video signal transmission system, a video signal is transmitted by a method as shown in FIG.

That is, the transmitting device sequentially transmits frame data F0, F1, F
2, a video signal D _v (FIG. 1 (A)) continuous of F3... Is divided into a predetermined frame group and processed.

That is, in this embodiment, the transmitting device divides the frame data F0, F1, F2, F3,... Into frame groups in units of six frames, and sets the first frame data F0, F6 of each frame group.
Is subjected to intra-frame encoding and transmitted.

Here, in the intra-frame encoding process, for example, a compression process is performed to obtain a difference between pixel data adjacent one-dimensionally or two-dimensionally along a scanning line direction. This is a process of forming transmission frame data obtained by compressing the transmission frame data.

Therefore, in the receiving apparatus, the transmission frame data subjected to the intra-frame encoding processing is sequentially added to the transmission frame data for the one frame, whereby
Frame data for one frame can be reproduced.

On the other hand, the transmitting apparatus performs frame-to-frame encoding processing on frame data F1, F2, F3,... Other than the head frame data F0, F6 of each frame group and transmits the frame data.

Here, the inter-frame encoding process first detects a motion vector between the frame data of the reference predicted frame and the frame data to be encoded, and then displaces the frame data of the predicted frame by the amount of the motion vector. The frame data (hereinafter, referred to as prediction result frame data) is formed, and deviation data between the prediction result frame data and the frame data to be coded is subjected to a coding process together with a motion vector to form transmission frame data. It is a process to do.

Accordingly, in the transmitting apparatus, frame data F1, F2, F3 other than the first frame data F0, F6 of each frame group are provided.
, A motion vector is detected for each of the predetermined predicted frames, and an inter-frame encoding process is performed.

Further, at this time, the transmitting apparatus is configured to allocate two predicted frames to each of the frame data F1, F2, F3,..., And detects a motion vector for each predicted frame.

Further, in the transmitting device, based on the detected two motion vectors, the frame data of the prediction result is formed from the frame data of the prediction frame, and then the frame data of the interpolation prediction result is interpolated by interpolating the frame data of the two prediction results. Data is formed, and frame data with the smallest amount of deviation data is selected from the frame data of the prediction result and the frame data of the interpolation prediction result, and the inter-frame coding process is performed (that is, in the selection prediction process). In the following, the frame data input earlier is predicted as frame data input before the frame data to be encoded, and the frame data input later as the frame data to be encoded is predicted. Frame prediction is used for post-prediction and interpolation prediction is used for frame data. Referred to as a prediction).

Thus, the transmitting apparatus selectively performs the inter-frame encoding processing so as to minimize the data amount of the transmission frame data, and thus transmits the video signal with improved transmission efficiency.

Further, in the transmitting apparatus, when performing the inter-frame encoding process, first, the fourth and fourth frame data F3 and F9 of each frame group are referred to as the frame data F0 and F
6, F6 and F12 are set as prediction frames and subjected to inter-frame encoding processing (hereinafter referred to as level 1 processing), and then the remaining frame data F1, F2, F4, F5. .. Are set as prediction frames, and an inter-frame encoding process is performed (hereinafter, referred to as a level 2 process).

That is, in the inter-frame encoding process, there is a feature that the amount of data to be transmitted can be reduced as compared with the intra-frame encoding process. Therefore, when transmitting a video signal, the amount of frame data to be inter-frame encoded is increased. Thus, the entire video signal can be transmitted with a small amount of data.

However, when the frame data to be subjected to the inter-frame encoding process increases, the inter-frame encoding process must be performed on the frame data of a frame far away from the reference predicted frame.

Therefore, it is necessary to detect a motion vector between frame data that are far away from each other, and the process of detecting a motion vector becomes complicated. Particularly, when performing a selection prediction process, the number of motion vectors to be detected increases. This complicates the configuration of the transmission device.

However, as in this embodiment, the frame data F0 and
F6 is set as a prediction frame, and frame data F3 is first subjected to inter-frame encoding processing, and then the frame data F3
And set the frame data F0, F6 as a predicted frame,
If the frame data F1, F2, F4, F5 ... in the meantime is subjected to inter-frame coding processing, motion vectors can be detected between relatively close frame data, and video signals can be efficiently transmitted with a simple configuration. can do.

Thus, in the level 1 inter-frame encoding process,
The transmitting apparatus sets the leading frame data F0 of the frame group and the leading frame data F6 of the subsequent frame group as prediction frames serving as references for motion vector detection, and performs pre-prediction and post-prediction, respectively.

That is, the transmitting apparatus transmits the frame data F0 and F6.
After detecting the motion vectors MV3P and MV3N for pre-prediction and post-prediction between the fourth frame data F3 and the fourth frame data F3 (FIG. 1 (B)), respectively, The frame data F0 and F6 of the prediction frame are displaced to form frame data FP and FN of the prediction result for pre-prediction and post-prediction.

Subsequently, the transmitting device linearly interpolates the frame data FP and FN to form prediction result frame data FPN for interpolation prediction.

Further, the transmitting device performs frame data FP, FN and FPN.
And deviation data ΔFP, ΔFN and ΔFP of the frame data F3
After obtaining N, from the deviation data ΔFP, ΔFN and ΔFPN,
Deviation data ΔFP, ΔFN or ΔFPN with the smallest data amount
Is converted to transmission frame data F3X together with the motion vectors MV3P and MV3N (FIG. 1 (D)).

Thus, in the receiving apparatus, after reproducing the original frame data F0 and F6 from the transmission frame data F0X and F6X formed by the intra-frame encoding process, based on the reproduced frame data F0, F6 and the transmission frame data F3X. Thus, the original frame data F3 can be reproduced.

On the other hand, in the level 2 processing, the transmitting device
First and second frame data of each frame group
For F1 and F2, F7 and F8,..., The first frame data F0 and F6 and the fourth frame data F3 and F9 are set as prediction frames, and are subjected to pre-prediction and post-prediction, respectively.

Therefore, in the transmitting device, the frame data F0 and F3
Based on the motion vectors MV1P and MV1N, MV2P and MV2N
(FIG. 1 (C)), the motion vector MV1P is detected.
And MV1N, MV2P, and MV2N, form frame data FP and FN of the prediction result, and form frame data FPN of the interpolation prediction result.

Further, based on the frame data FP, FN and FPN, after obtaining the deviation data ΔFP, ΔFN and ΔFPN, respectively, from the deviation data ΔFP, ΔFN and ΔFPN, select the deviation data ΔFP, ΔFN or ΔFPN with the smallest data amount. Then, together with the motion vectors MV1P and MV1N, MV2P and MV2N, they are converted into transmission frame data F1X and F2X.

Similarly, for the fifth and sixth frame data F4 and F5, F10 and F11,..., The fourth frame data F3 and the leading frame data F6 of the subsequent frame group
Is set as a prediction frame, and pre-prediction and post-prediction are performed, respectively.

Here, when the motion vectors MV4P and MV4N, MV5P and MV5N are detected, respectively, the transmitting apparatus forms the frame data FP, FN and FPN of the prediction result based on the motion vectors MV4P and MV4N, MV5P and MV5N, respectively. Deviation data ΔF
After obtaining P, ΔFN and ΔFPN, the deviation data ΔFP, ΔFN
And ΔFPN, the deviation data ΔF with the smallest data amount
Select P, ΔFN or ΔFPN to select the motion vectors MV4P and MV
With 4N, MV5P and MV5N, transmission frame data F4X and F4X
Convert to 5X.

Thus, the frame data is divided into six frames and transmitted by combining the intra-frame encoding process and the inter-frame encoding process, thereby reproducing the frame data F0, F6,. ,
The remaining frame data can be sequentially reproduced, and thus, even if an error occurs, error propagation to other frame groups can be prevented. It can be transmitted efficiently.

Further, even if the data is reverse-reproduced or randomly accessed, the frame data can be reliably reproduced, and the deterioration of the image quality can be effectively avoided and the video signal can be transmitted with high efficiency.

Further, in this embodiment, the transmission frame data F0X to F5X are rearranged in the order of the intra-frame encoding process and the inter-frame encoding process in each frame group and transmitted (FIG. 1 (E)). At this time, the transmission frame data F0X to F5X are added with the prediction frame data and identification data representing the transmission frame data subjected to the intra-frame encoding process, and transmitted.

That is, in the frame data F1, F2 and F4, F5, the frame data F0, F3 and F3, F6 of the predicted frame are required for encoding and decoding, respectively.

On the other hand, in the frame data F3, the frame data F0, F6 of the predicted frame for encoding and decoding is used.
Is required.

Therefore, as shown in FIG. 2, in the transmitting apparatus, frame data to be subjected to intra-frame encoding processing is represented by symbol A, and frame data to be processed at levels 1 and 2 is represented by symbols B and C.
, The transmission frame data DATA ((FIG. 2 (A))
Are output in the order of frame data A0, B3, C1, C2, C4, and C5.

At this time, the transmitting apparatus transmits a prediction index PIND for identification of pre-prediction, post-prediction, and interpolation prediction together with the transmission frame data.
EX, a pre-prediction reference index PID (FIG. 2 (B)) and a post-prediction reference index NID (FIG. 2 (C)) representing the predicted frames of the pre-prediction and the post-prediction, respectively, are transmitted and received. The transmission frame data can be easily decoded in the device.

In the configuration third diagram of (G2-1) transmission device (G2) Example 1 shows a transmission system of the video signal transmission system formed by applying the above-mentioned video signal transmission method, an input video signal VD _IN Highly efficient transmission frame data DA
After converting to TA, record it on a compact disc.

The transmission device 1 supplies the input video signal VD _IN to the image data input unit 2, where the luminance signal and the color difference signal constituting the input video signal VD _IN are converted into digital signals, and the data amount is reduced to 1/4. Reduce.

That is, the image data input unit 2 performs a one-field drop-down circuit (not shown) of the luminance signal converted into the digital signal.
, And the luminance signal for the remaining one field is thinned out every other line.

Further, the image data input unit 2 deletes two color difference signals converted into digital signals by one field, and then alternately selects and outputs one line at a time.

Further, the image data input unit 2 converts the thinned-out luminance signal and the selectively output color difference signal into data of a predetermined transmission rate via a time axis conversion circuit.

Thus via the image data input section 2 performs preliminary processing to the input video signal VD _IN, is adapted to generate image data D _V of consecutive sequential frame data described above.

When the start pulse signal ST is input, the rearrangement circuit 4 sequentially receives the frame data A0, C1, C2, B3, C4, C5, A6,
C7, the image data D _V input in the order of ..., after dividing the frame group at 6 frames, the order in which encoding processing
A0, A6, B3, C1, C2, C4, C5, A12, B9, C7,... Are rearranged and output.

If the frame data is rearranged and processed in the encoding order as described above, the subsequent intra-frame encoding process and inter-frame encoding process can be simplified accordingly.

Further, when the end pulse signal END rises, the rearranging circuit 4 rearranges the input frame data up to immediately before the end pulse signal END, and then stops outputting the frame data.

Further, the rearrangement circuit 4 outputs a frame group index GOF, a signal level rising at the beginning of each frame group, a pre-prediction reference index PID, a post-prediction reference index NID, and a temporary index TR indicating the order of frame data in the frame group. I do.

The motion vector detection circuit 6 receives the image data D _VN sorted, processed divides each frame data in a predetermined macro unit block.

At this time, the motion vector detection circuit 6 delays the frame data A0, A6,... For intra-frame encoding by a predetermined time and outputs the frame data to the subtraction circuit 8 that continues for each macro unit block. For the frame data B3, C1, C2, C4,... To be converted, the motion vectors MVP and MVN are detected for each macro unit block with reference to a predetermined predicted frame.

Further, at this time, the motion vector detection circuit 6 obtains deviation data between the frame data of the prediction result and the frame data to be subjected to the inter-frame encoding processing in the absolute value sum circuit,
Error data ER which is a sum of absolute values of the deviation data is obtained.

Thus, in this embodiment, the quantization step size and the like are switched by using the error data ER, whereby the deterioration of the image quality can be effectively avoided and the video signal can be transmitted efficiently. .

Further motion vector detecting circuit 6, as well as rearranged image data D _VN, frame group Indetsukusu GOF, forward prediction reference Indetsukusu PID, the rear prediction criteria Indetsukusu NID and temporary indenyl try TR, by the amount of the motion vector detection processing time delay Then, the data is output to the subsequent processing circuit for each macro unit block.

Subtraction circuit 8, by obtaining the difference data of the predicted data D _PRI and the image data D _VN is outputted from the adaptive prediction circuit 10, to create a difference data D _Z output to the discrete cosine transformation circuit 12.

Here, in the intra-frame encoding process, the adaptive prediction circuit 10 outputs an average value of image data of each pixel as prediction data _DPRI for each macro unit block.

On the other hand, in the inter-frame encoding process, the adaptive prediction circuit 10 performs a selection prediction process to select pre-prediction, post-prediction or interpolation prediction, and then converts the frame data of the selected prediction result to a prediction frame. outputs for each macro unit block as the data D _PRI.

Thus, the difference data D _Z (the difference data ΔFP, ΔFN having the smallest data amount in FIG.
P, whereas it is possible to obtain an equivalent to DerutaFN), the frame data to be processed in frame coding, it is possible to obtain the deviation data D _Z from the mean value.

The discrete cosine transform circuit 12 is a DCT (discret
using techniques e cosine transform), converts the deviation data D _Z for each macro unit block.

The multiplication circuit 14 is a discrete cosine conversion circuit 12 based on the control data output from the weight control circuit 16.
Is weighted.

Thus, in this embodiment, by performing a weighting process on the coefficient composed of the output data of the discrete cosine transform circuit 12, the image signal is effectively prevented from being degraded and the video signal is transmitted efficiently.

The requantization circuit 18 requantizes the output data of the multiplication circuit 14.

At this time, the requantization circuit 20 switches the quantization step size on the basis of the control data output from the data control circuit 20, so that the output data amount of the discrete cosine transform circuit 12, the input data amount and the error of the buffer circuit 21 are changed. The quantization step size is switched on the basis of the data ER, whereby the output data of the discrete cosine transform circuit 12 is re-quantized to reflect the nature of the image, and image data is effectively avoided to avoid image quality degradation. Is transmitted with a fixed data amount.

The inverse requantization circuit 22 receives the output data of the requantization circuit 18 and executes a requantization process reverse to that of the requantization circuit 18, thereby reproducing the input data of the requantization circuit 18.

The inverse multiplication circuit 24 is an inverse requantization circuit opposite to the multiplication circuit 14.
The output data of 22 is subjected to a multiplication process, whereby the input data of the multiplication circuit 14 is reproduced.

The discrete cosine inverse transform circuit 26 converts the output data of the inverse multiplying circuit 24 in reverse to the discrete cosine transform circuit 12, thereby reproducing the input data of the discrete cosine transform circuit 12.

The addition circuit 28 adds the prediction data _DPRI output from the adaptive prediction circuit 10 to the output data of the discrete cosine inverse conversion circuit 26, and outputs the result to the adaptive prediction circuit 10.

Therefore, in the adaptive prediction circuit 10, the frame data _DF obtained by reproducing the input data of the subtraction circuit 8 can be obtained through the addition circuit 28.
The _DF is selectively taken in to set a prediction frame, and then a selection prediction result is obtained for the frame data input to the subtraction circuit 8.

Thus, by inputting the frame data rearranged in the processing order, the adaptive prediction circuit 10 only needs to sequentially take in the frame data _DF selectively and detect the selection prediction result, and the configuration is accordingly simpler. Video signals can be transmitted.

The run-length Huffman encoding circuit 30 includes a requantization circuit.
After the Huffman encoding process of the variable length encoding process is performed on the output data 18, the output data is output to the transmission data synthesis circuit 32.

Similarly, the run-length Huffman encoding circuit 34 converts the motion vectors MVN and MVP for each macro unit block into an optimized Huffman code, and outputs the result to the transmission data synthesis circuit 32.

Transmission data combining circuit 32, in synchronism with the frame pulse signal S _FP, the output data of the run-length Huffman coding circuit 30 and 34, the prediction Indetsukusu pIndex, forward prediction reference Indetsukusu PID, post prediction criteria Indetsukusu NID and temporary indenyl try TR Are output together with the control information of the weight control circuit 16 and the data amount control circuit 20 in a predetermined order.

At this time, the transmission data synthesizing circuit 32 generates a macro unit block, a block unit group, each frame data,
A header is arranged for each frame group, and data such as a predicted index PINDEX is added to the header, whereby the receiving device can decode transmission data based on the data added to the header. ing.

The rearranging circuit 33 rearranges the output data of the transmission data synthesizing circuit 32 in the order of the encoding processing for each frame group and outputs the data to the buffer circuit 21, thereby transmitting the transmission frame data DATA via the buffer circuit 21. Is output.

Thus, the transmission frame data DATA obtained by encoding the input video signal VD _IN with high efficiency can be obtained. By recording the transmission frame data DATA together with the synchronization signal etc. on a compact disc, it is possible to effectively avoid the deterioration of the image quality and to reduce the video signal. Can be recorded at high density.

(G2-2) Motion Vector Detection Circuit As shown in FIGS. 4 and 5, the motion vector detection circuit 6 includes a pre-prediction reference index PID, a post-prediction reference index NID, and a temporary index TR (see FIG. ), (B) and (C)), the image data _DVN output from the sorting circuit 4 is processed.

That is, in the motion vector detection circuit 6, the read-only memory circuits 72 and 73 receive the pre-prediction reference index PID and the post-prediction reference index NID, respectively, and when the pre-prediction reference index PID and the post-prediction reference index NID have the value 3, The switching control data SW1 and SW2 (FIGS. 5D and 5E) at which the level falls are created.

The read-only memory circuit 74 has a temporary index
Upon receiving the TR, when the temporary index TR has a value of 0 (that is, corresponding to the frame data to be subjected to the intra-frame encoding process), the intra-frame encoding process control data PINTRA (FIG. 5 (F)) at which the logical level rises is changed. create.

Similarly, read only memory circuits 75, 76, 77, 78, 79
Means that the temporary index TR has the value 3, 1,
In the case of 2, 4, and 5 (that is, corresponding to the frame data B3, C1, C2, C4, and C5 of the inter-frame encoding process), the inter-frame encoding control data WB at which the logical level rises
3. Create WC1, WC2, WC4, WC5.

The delay circuit 80 controls the inter-frame encoding process control data WC5.
, The switching control data BON (FIG. 5 (G)) in which the logical level rises sequentially at the head of each frame group is created from the second frame group.

The OR circuit 82 controls the inter-frame encoding process control data WC5.
And the intra-frame encoding control data PINTRA, thereby generating frame memory control data WAP (FIG. 5 (H)).

Thus, the motion vector detection circuit 6 operates based on these control data created by the read-only memory circuits 73 to 79, the delay circuit 80, and the OR circuit 82.

The block forming circuit 84 outputs the frame pulse signal _SFP (fifth signal).
FIG image data D _V (I sequentially inputted in synchronization with the (I))
N) (FIG. 5 (J)), each frame data is divided into predetermined macro unit blocks.

Here, as shown in FIG. 6, each frame data (6
In FIG. 7A, the display screen is divided into 5 × 2 in the vertical and horizontal directions and divided into ten block unit groups (the sixth block).
FIG.

Further, each block unit group is divided into 33 macro unit groups (FIG. 6 (C)) by dividing 3 × 11 in the vertical and horizontal directions, and in the transmitting apparatus 1, the frame data is divided into the macro unit groups. Are sequentially processed.

Note that one macro unit group has 8
Image data for pixels is assigned to one block, and image data for 6 blocks in total is assigned.

Against further the 6 blocks, the luminance signal into four blocks Aspect 2 × 2 blocks fraction _{Y 1, Y 2, Y 3} , Y 4 are assigned respectively the luminance signal to the remaining two blocks Y _1, Y _2,
The color difference signals C _R and C _B corresponding to Y ₃ and Y ₄ are assigned.

Thus, frame data divided into 15 × 22 macro unit blocks can be obtained via the block forming circuit 84.

The delay circuit 85 delays the frame data output from the block forming circuit 84 by five frame periods required for the motion vector detection processing and outputs the delayed frame data.

Thus, the motion vector detection circuit 6 divides the image data _DV (OUT) (FIG. 5 (K)) into macro-unit blocks and outputs them in synchronization with the detection of the motion vector.

The delay circuit 86 has a frame group index GOF (IN)
(FIG. 5 (L)) is delayed only 5 frame period, thereby the motion to the vector detection image data D _V output from the circuit 6 (OUT), a timing matched frame group Indetsukusu GOF of (OUT) (FIG. 5 (M)) is output.

The post-prediction frame memory circuit 88, the pre-prediction frame memory circuit 89, and the inter-frame memory circuit 90 store frame data serving as a reference for detecting a motion vector.

That is, when the intra-frame encoding process control data PINTRA rises, the post-prediction frame memory circuit 88
Captures D _V, thereby via the post prediction frame memory circuit 88, after the frame data A0 is output for the period of one frame period, continuous period frame data A6 subsequent 6 frame period, followed by six-frame period can time frame data A12 of obtaining image data D _NV continuous (FIG. 5 (N)).

On the other hand, when the frame memory control data WAP rises, the pre-prediction frame memory circuit 89 takes in the frame data output from the post-prediction frame memory circuit 88.

As a result, of the six frame periods in which the frame data A6 is output from the rear prediction frame memory circuit 88 via the front prediction frame memory circuit 89, the frame data A0 for the first five frame periods continues, and then the next six frames continuous period frame data A6 period can be a period frame data A12 of the subsequent 6 frame cycles to obtain the image data D _PV continuous (FIG. 5 (O)).

This interframe memory circuit 90 for the captures image data D _VN when interframe coding processing control data WB3 rises.

Thus, the image data D _INT (FIG. 5 (P)) in which the fourth frame data B3, B9, and B15 are respectively continuous for a period of six frame periods is obtained via the inter-frame memory circuit 90.

The selection circuits 92 and 93 _provide image data D _NV and D
It received _INT, the image data D _PV and D _INT, cut-over control data
The contact is switched based on SW1 and SW2.

As a result, the selection circuits 92 and 93 sequentially switch and output the frame data A0, A6, B3,... Serving as a reference for the motion vector detection to the subsequent variable read memory circuits 94 and 95.

That is, the motion vectors MV3N and MV of the frame data B3
When 3P is detected, frame data A6 and A0 are output to the variable read memory circuits 94 and 95, respectively.

On the other hand, among the level 2 processing, the frame data C1
When detecting the motion vectors MV1N, MV1P and MV2N, MV2P of C2 and C2, output the frame data B3 and A0 to the variable read memory circuits 94 and 95 respectively, and the motion vectors MV4N, MV4P and MV5N of the frame data C4 and C5. When detecting MV5P, frame data A6 and B3 are output to variable read memory circuits 94 and 95, respectively.

By the way, when the motion vector of the frame data C1 is detected based on the frame data A0, for example, in a range of eight pixels in the vertical, horizontal, and vertical directions, the motion vector of the frame data C2 is detected based on the frame data A0.
It is necessary to detect a motion vector in a range of 16 pixels.

Similarly, in order to detect the motion vectors of the frame data C4 and C5 on the basis of the frame data A6, it is necessary to detect the motion vectors in the range of 16 pixels and 8 pixels in the vertical and horizontal directions, respectively.

Accordingly, when detecting a motion vector in the level 2 processing, it is necessary to detect the motion vector within a range of up to 16 pixels in the upper, lower, left and right directions.

On the other hand, in order to detect the motion vector of the frame data B3 based on the frame data A0 and A6, it is necessary to detect the motion vector in a range of 24 pixels in the upper, lower, left, and right directions.

Accordingly, in the motion vector detecting circuit 6, when the frame data is divided into predetermined frame groups and the frame data in each frame group is subjected to the inter-frame encoding and transmitted, the motion vector detection range is wide. become,
The structure may be complicated accordingly.

For this reason, in this embodiment, after detecting the motion vector of level 2 first, the motion vector detection range of the frame data B3 is set with reference to the detection result, and the motion vector detection circuit 6 Is simplified.

That is, as shown in FIGS. 7 and 8, each frame data C from frame data A0 to frame data B3 is set.
1, C2 sequentially detects motion vectors V _1, V _2, V ₃ for,
Detect the sum vector V ₁ + V ₂ + V ₃ of the motion vectors V ₁ , V ₂ , V ₃ .

Further, the motion vector detection range of the frame data B3 is set around the position offset by the sum vector V ₁ + V ₂ + V ₃ , and the motion vector is detected in the motion vector detection range.
Detect MV3P.

In this way, the motion vector MV3P can be detected in a narrow motion vector detection range.

In the case of this embodiment, in the level 2 motion vector detection process, since the motion vectors for pre-prediction and post-prediction are detected, the motion vectors MV1P and
By detecting the MV1N and setting the motion vector detection range around the position offset by the motion vectors MV1P and MV1N, the motion vector MV3P can be detected in a narrow motion vector detection range.

Therefore, the selection circuit 96 first converts the frame data C1, C2, C4, and C5 to be processed at level 2 into the subtraction circuit KN ₀
KKN ₂₅₅ and KP ₀ KKP ₂₅₅ .

On the other hand, in level 1 processing, the selection circuit
The reference numeral 96 switches contacts, and stores the frame data B3 once stored in the inter-frame memory circuit 90 into a blocking circuit 97.
In divided similarly macro unit block and block circuit 84, applied to subtraction circuit KN ₀ Kn ₂₅₅ and KP ₀ ~Kp _255, detects a motion vector for thereby sequentially frame data C1, C2, C4 and C5 Thereafter, a motion vector is detected for the frame data B3.

The selection circuits 92 and 93 switch the contacts according to the motion vector detection order, and when the frame data C1, C2, C4 and C5 are input to the motion vector detection circuit 6, the variable read memory circuits 94 and 95 respectively transmit the data. After sequentially outputting the frame data B3 and A0, B3 and A0, A6 and B3, A6 and B3, the subsequent frame data of one frame cycle
A6 and A0 are output.

The subtraction circuits KN _{0 to} KN ₂₅₅ and KP _{0 to} KP ₂₅₅ are connected in parallel with 256 × 2 subtraction circuits and sequentially input image data of a luminance signal constituting each macro unit block.

Variable read memory circuits 94 and 95 on the other hand, based on the control data D _M outputted from the vector generating circuit 98, parallel subtraction circuit frame data inputted through the selection circuit 92 and 93 KN ₀ To KN ₂₅₅ and KP _{0 to} KP ₂₅₅ .

That is, the variable read memory circuits 94 and 95
In the process of, when the first image data of the first macro unit block is inputted to the subtraction circuit KN ₀ Kn ₂₅₅ and KP ₀ ~Kp _255, the range of vertical and horizontal 16 pixels centered the image data The image data (that is, the image data in the motion vector detection range) is divided into subtraction circuits KN _{0 to} KN ₂₅₅ and KP _{0 to} KP
Output to ₂₅₅ .

Variable read memory circuits 94 and 95 Similarly, the second image data of the first macro unit block is subtraction circuit KN ₀ Kn
₂₅₅ and KP _{0 to} KP ₂₅₅ , image data in a range of 16 pixels above, below, left, and right around the second image data is subtracted from the frame data of the prediction frame by subtraction circuits KN _{0 to} KN
And outputs the N ₂₅₅ and KP ₀ ~KP _255.

Thus, the variable read memory circuits 94 and 95 are at level 2
In the processing of the image data to be inputted to the subtraction circuit KN ₀ Kn ₂₅₅ and KP ₀ ~Kp _255, and outputs the image data of the sequential motion vector detection range.

As a result, in the processing of level 2, the subtraction circuit KN ₀
Through Kn ₂₅₅ and KP ₀ ~Kp _255, for each image data of the frame data for detecting a motion vector, it is possible to obtain the deviation data at the time of moving the frame data of the predicted frame by the motion vector detecting range.

On the other hand, in the level 1 processing, the variable read memory circuits 94 and 95 store the frame data C1, C2, C4, C5
Subtraction circuits KN _{0 to} KN ₂₅₅ and KP _{0 to} KP
The input image data _255, the image data from the predicted motion vector MV3NY, around the image data amount corresponding displacement of MY3PY, the image data in the range of vertical and horizontal 16 pixels, the subtraction circuits KN ₀ Kn and outputs it to the ₂₅₅ and KP ₀ ~KP _255.

Thereby, in the processing of level 1, the subtraction circuit KN ₀
Through KN ₂₅₅ and KP _{0 to} KP ₂₅₅ , deviation data when the predicted frame is moved in the motion vector detection range displaced by the predicted motion vectors MV3NY and MY3PY for each image data of the frame data B3. Can be obtained.

The absolute value sum circuits 100 and 101 are respectively provided with a subtraction circuit KN _0.
Receiving the subtracted data Kn ₂₅₅ and KP ₀ ~KP _255, after detecting the absolute value sum of the subtraction data for each subtraction circuit KN ₀ Kn ₂₅₅ and KP ₀ ~KP _255, the absolute value for each macro unit block Output the sum.

As a result, in the processing of level 2 via the absolute value summation circuits 100 and 101, when the prediction frame is sequentially moved in the motion vector detection range centered on the macro unit block for each macro unit block, 256 (ie, 16 × 16) deviation data can be obtained.

On the other hand, in the processing of the level 1, the prediction frame is sequentially moved for each macro unit block within the motion vector detection range displaced by the predicted motion vectors MV3NY and MY3PY based on the macro unit block. 256 deviation data at the time of the execution can be obtained.

The comparison circuits 102 and 103 receive the 256 pieces of deviation data output from the absolute value summation circuits 100 and 101, and when the image data of the predicted frame is moved up, down, left, and right by 0 pixels (that is, the predicted frame is moved). The error data D _OON and D _OOP are output to the comparison circuits 105 and 106.

Further comparison circuit 102 and 103 detects a minimum value from the remaining deviation data, and outputs as the error data ER (ER _N and ER _P), to detect the position information of the deviation data of the minimum value.

Thus, by switching the quantization step size of the requantization circuit 18 based on the error data ER and controlling the weighting processing of the multiplication circuit 14, the properties of the image can be reflected in the requantization processing, and Can be effectively avoided and the video signal can be transmitted.

Further, based on the minimum deviation data, it is possible to detect the position information at which the predicted frame is moved so that the deviation data is minimized, whereby the motion vector can be sequentially detected for each macro unit block.

Comparator circuit 105 and 106 is adapted to obtain a comparison result of the error data ER _N and ER _P and deviation data D _OON and D _OOP.

At this time, as shown in FIG.
, The error data ER _N and ER _P and deviation data D _OON and D
_OOP is As represented by, when the error and the deviation amount per pixel are exchanged, the 0 vector is preferentially selected as the motion vector in a range where the error and the deviation amount are small.

That is, in a range where the error and the deviation amount are small, even if the comparison circuits 102 and 103 generate the deviation data ΔEN and ΔEP (FIG. 1) based on the motion vector, but the deviation data ΔEN and ΔEP are generated with the zero vector. However, the data amounts of the deviation data ΔEN and ΔEP cannot be reduced so much, and the data amount as a whole increases by transmitting the detected motion vector composed of the significant information.

Therefore, in this embodiment, the comparison circuits 105 and 106 preferentially select the 0 vector as the motion vector, so that the entire video signal is efficiently transmitted.

Thus, the comparison circuits 105 and 106 output switching signals to switch the contacts of the selection circuits 107 and 108, and according to the priorities shown in FIG. 9, the zero vector data MV ₀ and the comparison circuits 102 and
The motion vector output from 103 is selected and output, whereby the motion vectors MViN and MViP (FIGS. 5 (Q) and (R)) can be obtained via the selection circuits 107 and 108.

The motion vector memory circuits 110 to 113 and 114 to 117 take in the motion vectors MViN and MViP in accordance with the inter-frame coding control data WC1, WC2, WC4, and WC5, and thereby, the frame data C1 to be processed at level 2 respectively. , C2,
For C4 and C5, motion vectors MV for post-prediction and pre-prediction
Import 1N, MV2N, MV4N, MV5N and MV1P, MV2P, MV4P, MV5P.

On the other hand, the addition circuits 120 to 122 and 123 to 125 are provided with the motion vectors MV1N, MV2N, MV4N, MV5N and MV1P, MV2P, stored in the motion vector memory circuits 110 to 113 and 114 to 117, respectively.
Receiving MV4P, MV5P, motion vectors MV1N, MV1P, MV2N and
MV2P addition result and motion vectors MV4N, MV4P, MV5N and
The addition result of MV5P is divided by 1/2 divider circuits 127 and 128, respectively.
Output to

That is, as described above, in this embodiment, after detecting the motion vector of level 2 first, the detection range of the motion vector of the frame data B3 is set in advance with reference to the detection result, so that the maximum A motion vector is detected in a range of 16 pixels on the left and right, and the configuration of the entire motion vector detection circuit 6 is simplified accordingly.

Therefore, the adder circuits 120 to 125 and the 1/2 divider circuits 127 and 128
By obtaining the addition result of the value 1/2 for the motion vectors MV1N to MV5P, After creating the predicted motion vectors MV3NY and MV3PY represented by, the predicted motion vectors MV3NY and MV3PY are output to the addition circuits 132 and 133 via the selection circuits 130 and 131.

Here, the selection circuits 130 and 131 output the switching control data BO
By switching the contacts according to N, for the frame data C1, C2, C4, and C5 to be processed at level 2, data D _ON and D _OP having a value of 0 are selectively output, whereas
For frame data B3 to be processed at level 1, the predicted motion vectors MV3NY and MV3PY are selectively output.

Summing circuits 132 and 133, the output data MV3NY selection circuits 130 and 131, D _ON and MV3PY, the D _OP, vector generator 98
Is added to the control data D _M output from.

As a result, for the frame data C1, C2, C4, and C5, a motion vector is detected within the motion vector detection range centered on each macro unit block, whereas for the frame data B3, prediction is performed from each macro unit block. A motion vector is detected in a motion vector detection range displaced by the motion vectors MV3NY and MV3PY.

Therefore, frame data separated by a plurality of frames
Motion vectors between A0 and B3, B3 and A6 can be reliably detected in a narrow motion vector detection range, and thus motion vectors can be detected with a simple configuration.

Further, the motion vectors of the pre-prediction and post-prediction of the frame data C1 and C2 are averaged, and the motion vector MV for pre-prediction is calculated.
By setting the motion vector detection range of 3P, averaging the motion vectors for pre-prediction and post-prediction of the frame data C4 and C5, and setting the motion vector detection range of the motion vector MV3N for post-prediction, Vectors can be reliably detected.

The addition circuits 135 and 136 add the predicted motion vectors MV3NY and MV3PY to the motion vectors output from the selection circuits 107 and 108 in the processing of level 1 and output the resultant, thereby obtaining motion vectors MV3P and MV3N, Thus, the motion vectors MV3N and MV3P between frame data far apart can be detected with a simple configuration as a whole.

The counter circuit 138, after being cleared by the interframe coding processing control data WC5, consist of quinary counter circuit adapted to sequentially count the frame pulse signal S _FP, sequentially circulates from the value 0 to the value 4 The motion vector selection data MVSEL (FIG. 5 (S)) is output.

The selection circuits 139 and 140 provide the motion vector selection data MVSE
The contacts are sequentially switched according to L, whereby the addition circuit 135
And 136, the motion vectors MV3N and MV3P output from the motion vector memory circuits 110 to 117, and the motion vectors MV1N to MV5P stored in the motion vector memory circuits 110 to 117 are sequentially run-length-Huffman-coded.
Thus, the motion vectors MVN and MVP (FIGS. 5 (T) and (U)) can be sequentially obtained for each macro unit block via the motion vector detecting circuit 6.

(G2-3) Run-length Huffman coding circuit As shown in FIG. 10, the run-length Huffman coding circuit
34 is a motion vector MV of the pre-prediction of the frame data C1 and C4.
1P, MV4P and frame data C2, C5 post-prediction motion vectors MV2N, MV5N (ie, adjacent frame data A0,
(Which is a motion vector detected using B3 and A6 as reference frames, hereinafter referred to as a 1-times vector) is supplied to the selection circuit 150.

The adder circuit 151 generates the post-prediction motion vectors NV1N and MV4N of the frame data C1 and C4 and the motion vectors MV2P and MV5P of the pre-prediction of the frame data C2 and C5 (that is, the frames separated from the reference frame data A0, B3 and A6 by two frames). Data vector, hereinafter referred to as a double vector). When the value is positive, the value 1 is added and output. On the other hand, when the value is negative, the value -1 is subtracted and output. .

On the other hand, the 1/2 dividing circuit 152 receives the output of the adding circuit 151 and outputs the result of the 1/2 dividing to the selecting circuit 150 except for the remainder.

That is, the adder circuit 151 and the 1/2 divider circuit 152 convert the motion vectors MV1N, MV4N and MV2P, MV5P into motion vectors for one frame and output them.

On the other hand, the adding circuit 153 calculates the motion vectors MV3P and MV3N of the frame data B3 (that is, the reference frame data
A0, A6, which is a motion vector of frame data separated by 3 frames, hereinafter referred to as a triple vector). When the value is positive, the value 2 is added and output, while when the value is negative, The value -2 is subtracted and output.

The 1/3 dividing circuit 154 receives the output of the adding circuit 153,
The remainder is output to the selection circuit 150 except for the remainder.

That is, the adding circuit 153 and the 1/3 dividing circuit 154 convert the motion vectors MV3P and MV3N into motion vectors for one frame, and output them.

By doing so, the appearance probabilities of the values of the motion vectors input to the selection circuit 150 are set to the same value, whereby each motion vector can be easily optimized.

That is, as shown in FIG.
In FM, F1, F2, and F3, the motion vectors V ₁ , V ₂ , and V _{3 based} on the frame FM are as follows when the frame correlation is strong between the frames FM, F1, F2, and F3: V ₂ ≒ 2V ₁ (5) V ₃ 33V ₁ (6)

Accordance connexion, the motion vector V _X of general frame spaced x frames may represent the following formula _{V X ≒ xV 1 ...... (7} ).

This is as shown in FIG. 12, when the value of the motion vectors statistically representing the appearance probability at the a, if multiplied by x probability φV1 of the motion vector V _1: (a) in the horizontal direction, motion It can be seen that the probability φV _X (a) of the vector V _X can be expressed.

The value of the sub connexion motion vector V _X divided by x, is expressed by the value a with the exception of the less, the occurrence probability of the motion vector V _X 1 / XφV _X
(A) is consistent with the appearance probability φV1 of the motion vector V ₁ (a), the division result of the motion vector V _X and the motion vector V ₁ using the same table, it can be seen that be optimized.

Based on this principle, the run-length Huffman encoding processing circuit 34 gives the selected output of the selection circuit 150 to the read-only memory circuit 156, and uses the selected output as an address,
The data DV1 stored in the read-only memory circuit 156 is output.

Here, as shown in FIG. 13, the read only memory circuit
Numeral 156 is set so that variable-length coded data whose code length is sequentially increased centering on the input data of value 0 with respect to the input data is output, whereby the motion converted into one frame is set. Optimally encode the vector.

That is, when a motion vector value is statistically detected, a motion vector having a value of 0 has the highest appearance probability, and the appearance probability decreases as the motion vector value increases.

Therefore, in this embodiment, the amount of data required for motion vector transmission is reduced as a whole by performing encoding processing so that a motion vector having a value of 0 becomes the shortest code table. Signals are transmitted efficiently.

Further, the read-only memory circuit 156 outputs the output data DV1.
Is output together with the data DV1.

The remainder output circuit 160 outputs the output data of the addition circuit 153 to the value 3
After that, the remainder data is output to the read-only memory circuit 162.

As shown in FIG. 14, the read only memory circuit 162
Outputs the remainder data DV2 having a code length of 1 with a code length of 1 for input data having a value of 0, whereas outputs 1, 2 having a code length of 2 with respect to input data having a value of 1 and value 2. And the value 1,
The remainder data DV2 of 1 is output.

Here, the input data of the read-only memory circuit 162 is a remainder obtained by converting the triple vector subjected to the addition and subtraction processing by the addition circuit 153 into one frame, so that the appearance probability of the value 0 is the highest and the value is large. , The appearance probability decreases.

Therefore, in this embodiment, the residual data DV2 having the shortest code length is output for input data having a value of 0, which has the highest occurrence probability, so that the data amount required for motion vector transmission can be reduced as a whole. As a result, the moving image video signal is efficiently transmitted.

Further, the read-only memory circuit 162
And outputs code length data DLL2 representing the code length of the surplus data DV2 in synchronization with.

The selection circuit 164 switches contacts in synchronization with the selection circuit 150, and selects and outputs the least significant bit and the remainder data DV2 of the output data output from the addition circuit 151.

That is, the selection circuit 164 stops the selection output operation for the 1 × vector.

Further, the selection circuit 164 outputs the input least significant bit data for the double vector, thereby selecting the selection output of the value 1 to the parallel / serial conversion circuit 166 when the value of the double vector is an even value. When the value of the double vector is an odd value and a value 0, the selected output of the value 0 is output to the parallel-serial conversion circuit 166.

Further, the selection circuit 164 selects and outputs the remainder data DV2 for the triple vector.

The selection circuit 168 provides input data DLL0 and D0 of value 0 and value 1
By receiving the LL1 and the code length data DLL2 and switching the contacts in synchronization with the selection circuit 164, the code length data DL2 representing the code length of the selected output data DJ output from the selection circuit 164 is output.

The addition circuit 170 outputs the addition result of the code length data DL1 and DL2 to the parallel-serial conversion circuit 166.

As shown in FIG.
After adding the output data DJ of the selection circuit 164 and the addition data of the addition circuit 170 to the output data DV1 of the read-only memory circuit 156, the data is converted into serial data and output.

Thereby, through the parallel / serial conversion circuit 166,
The output data DV1 output from the read-only memory circuit 156 and the code length data DL1 of the output data DV1 are converted into serial data and output for the one-time vector.

Against twice vector hand, when the value of twice the vector is an even value, read only the output data DV1 output from the memory circuit 156 is the remainder bit b ₁ of a value 0 is added, this code length After adding data obtained by adding 1 to the data DL1, the data is converted into serial data and output.

Further, when the value of the double vector is an odd value and a value 0, the remainder bit b1 of the value ₁ is added to the output data DV1, and after adding the value 1 obtained by adding the value 1 to the code length data DL1, It is converted to serial data and output.

Against 3 times vector contrast, triple vector has a value 0 or a value ± (3n + 1) when (n = 0,1,2 ......), added the remainder bit b ₁ of a value 0 in the output data DV1 And
After adding data obtained by adding the value 1 to the code length data DL1, the data is converted into serial data and output.

Furthermore, the triple vector has the value ± (3n + 2) (n = 0,
1, 2,...), Remainder bits b ₁ and b ₂ of values 1 and 0 are added to the output data DV 1, and the code length data DL
When the added data obtained by adding the value 2 to 1 is added, converted into serial data and output, the triple vector has a value ± (3n + 3) (n = 0, 1, 2,...) output data DV1 to the remainder bits b ₁ and b ₂ values 1 and a value 1 is added, thereto to addition data obtained by adding the value 2 to the code length data DL1 is added, is output after being converted into serial data.

Thus, on the transmission target side, the data of the motion vector subjected to the variable length coding processing in this manner is converted into a one-time vector, a two-time vector based on the pre-prediction reference index PID, the post-prediction reference index NID, and the temporary index TR. It can be determined whether the vector is a vector or a triple vector, and the original motion vector can be decoded based on the determination result.

Thus, the one-time vector, the two-time vector, and the three-time vector can be subjected to the variable-length encoding process using one type of table stored in the read-only memory circuit 156, giving priority to the one having a high appearance probability. Accordingly, the motion vector can be optimized with a simple configuration.

Further, by performing the encoding process in this manner, the motion vector can be transmitted while maintaining the detected accuracy, and thus the video signal can be transmitted efficiently with the image quality deterioration being effectively avoided.

(G2-4) Configuration of Receiving Device In FIG. 17, reference numeral 200 denotes a receiving device as a whole,
Playback data D _PB obtained by playing a compact disc
Is received by the receiving circuit 201.

The receiving circuit 201 detects the head of each frame group based on the data added to the
D _VPB outputs the detection result.

As a result, as shown in FIG.
Can obtain continuous image data D _VPB (FIG. 18 (A)) of frame data PA0, PB3, PC1, PC2,... Which have been sequentially subjected to intra-frame coding processing and inter-frame coding processing.

The rearrangement circuit 203 outputs the transmission frame data PB3, PC1, PC2,... That have been subjected to the inter-frame encoding with a delay of 7 frame periods, whereby the transmitting apparatus 1 performs intra-frame encoding and inter-frame encoding. Frame data in the processing order (that is, the same as the decoding processing order)
PA0, PA6, PB3, PC1, PC2,... Are rearranged and output (FIG. 18 (B)).

The buffer circuit 204 temporarily stores the image data _DVPBN output from the rearrangement circuit 203, and then outputs the image data _DVPBN to the subsequent separation circuit 206 at a predetermined transmission rate.

The separation circuit 206, based on the data added to the transmission data, based on the frame group index GOF, pre-prediction reference index PID, post-prediction reference index NID, temporary index TR, prediction index PINDEX, data DC
(DCM-Y, DCM-U, DCM-M), QUANT, and motion vector data MVD-P and MVD-N are reproduced and output to a predetermined circuit.

As a result, the control circuit 207 controls the compact disk drive reproducing system, and reproduces the data sequentially recorded on the compact disk to obtain the image data _DVPBN, as described above with reference to FIG. ing.

Further, the separation circuit 206 removes the header from the image data D _VPB and outputs the result to the run-length Huffman inverse encoding circuit 210.

The run-length Huffman decoding circuit 210 performs the inverse processing of the run-length Huffman coding circuit 30 (FIG. 3), thereby reproducing the input data of the run-length Huffman coding circuit 30 on the receiving device 200 side. .

The inverse quantization circuit 211 outputs the output data of the run-length Huffman inverse encoding circuit 210 and the data QUAN added to the macro unit block and indicating the quantization step size.
Receiving T, the re-quantization circuit 18 performs a re-quantization process reverse to that of the re-quantization circuit 18 in the same manner as the inverse re-quantization circuit 22 (FIG. 3). To reproduce.

The inverse multiplication circuit 212 receives the output data of the inverse requantization circuit 211, executes the inverse multiplication of the multiplication circuit 14 (FIG. 3) based on the data added to each macro unit block, and thereby receives the data. On the device 200 side, the input data of the multiplication circuit 14 is reproduced.

The discrete cosine inverse transform circuit 213 converts the output data of the inverse multiplying circuit 212 into the discrete cosine transform circuit 1.
2 (FIG. 3), thereby reproducing the input data of the discrete cosine transform circuit 12.

The addition circuit 218 converts the prediction data D _PRI output from the adaptive prediction circuit 214 into a discrete cosine inverse conversion circuit 213.
And outputs the result to the adaptive prediction circuit 214.

The run-length Huffman inverse coding circuit 220 decodes the pre- and post-prediction motion vectors MVP and MVN, which have been subjected to the variable-length coding in the run-length Huffman coding circuit 34 of the transmission device 1, and outputs the decoded data to the adaptive prediction circuit 214. Output.

The adaptive prediction circuit 214 reproduces the prediction data _DPRI output from the adaptive prediction circuit 10 of the transmission device 1, based on the output data D _TIN of the addition circuit 218, the motion vectors MVP, MVN, and the like.

That is, the adaptive prediction circuit 214 calculates the prediction data D for the frame data A0 and A6 subjected to the intra-frame encoding processing.
DC level data DC is output to the adding circuit 218 as _PRI .

As a result, the frame data A0 and A6 subjected to the intra-frame encoding processing can be reproduced via the addition circuit 218.

Further, the adaptive prediction circuit 214
In the same manner as described above, it has a pre-predicted frame memory circuit, a post-predicted frame memory circuit, and an inter-frame memory circuit, and stores the reproduced frame data A0 and A6 in the pre-predicted frame memory circuit and the post-predicted frame memory circuit (the 18 (C) and (D)), prediction data D of frame data B3
Create a _PRI .

As a result, the frame data B3 that has been subjected to the level 1 inter-frame encoding processing can be reproduced via the adding circuit 218.

Further, the adaptive prediction circuit 214 stores the reproduced frame data B3 in the inter-frame memory circuit (FIG. 18 (E)), and stores the prediction data of the frame data C1, C2, C4, C5.
D _PRI is generated, and thus the frame data C1 and C1 that have been subjected to the level 2 inter-frame encoding processing via the adding circuit 218.
2, C4, C5 can be reproduced.

Further, the adaptive prediction circuit 214 returns the reproduced frame data A0, A6, B3,... To the original arrangement order and outputs it (FIG. 18 (F)).

The receiving apparatus 200 has an interpolation circuit (not shown), and interpolates and outputs the lines and frames thinned out by the transmitting apparatus 1 based on the reproduced frame data. To reproduce the input video signal VD _IN .

Thus, a video signal recorded on a compact disk by performing high-efficiency code processing can be reproduced.

(G3) Operation of Embodiment In the above configuration, the input video signal VD _IN is converted into a digital signal by the image data input unit 2, the data amount is reduced to 1/4, and the frame data A0, C1, C
2, C3... Are converted into a continuous video signal VD (FIG. 1 (A)).

The video signal VD is output by the rearranging circuit 4 to the frame data A0,
After C1, C2, C3,... Are divided into frame groups in units of six frames, the order of encoding processing A0, A6, B3, C1, C2, C4,
C5 ... (that is, the order of frame data A0 and A6 to be subjected to intra-frame encoding processing, frame data B3 to be subjected to level 1 inter-frame encoding processing, and frame data C1, C2, C4 and C5 to be subjected to level 2 inter-frame encoding processing) ), And are output together with predetermined identification data GOF, PID, NID, and TR.

Thus, the order of encoding processing A0, A6, B3, C1, C2, C
After sorting into 4, C5, C7, ...
By outputting with F, PID, NID, and TR added, the subsequent intra-frame encoding process and inter-frame encoding process can be simplified.

The rearranged image data _DVN is divided into macro-unit blocks by the block forming circuit 84 of the motion vector detecting circuit 6, and then output to the adaptive prediction circuit 10 at a predetermined timing.

Further, among the rearranged image data _DVN , the frame data A0, B3, and A6 are stored in the pre-prediction frame memory circuit 89, the inter-frame memory circuit 90, and the post-prediction frame memory circuit 88, respectively, whereby the selection circuit 139 is provided. And 1
, The motion vectors MV3P, MV3N, MV1P, MV1N, MV2P, MV2N... Of the frame data B3, C1, C2,.

On the other hand, the image data output to the adaptive prediction circuit 10
D _VN is the luminance signal for each macro unit block, the average value of the image data of the color difference signal is obtained, the average value data is output to the transmission data composition circuit 32 as a direct current data DC.

Further, the image data D input to the adaptive prediction circuit 10
_{The VN} is selected and predicted based on the frame data A0, A6, and B3 (consisting of the frame data reproduced by the adding circuit 28), and the post-prediction, pre-prediction, and interpolation prediction are performed for each macro unit block. Deviation data ΔFN, ΔFP, ΔFNP
(FIG. 1) is obtained.

The deviation data .DELTA.FN, .DELTA.FP and .DELTA.FNP are detected with the smallest data amount, and the selection prediction result is detected for each macro unit block.

Post-prediction, pre-prediction, interpolation predicted frame data FN, F
P and FNP are selected and output in accordance with the result of the prediction selection, whereby prediction data _DPRI is created and output to the subtraction circuit 8.

On the other hand, the selection prediction result is output to the transmission data combining circuit 32 as the identification data PINDEX.

The prediction data D _PRI is _{converted into} image data by the subtraction circuit 8.
D _VN is subtracted, and thereby the deviation data D _Z is created.

The deviation data D _Z is calculated by the discrete cosine conversion circuit 12.
Then, using the DCT method, conversion is performed for each macro unit block.

The output data of the discrete cosine conversion circuit 12 is
After being weighted by the multiplication circuit 14 in accordance with the error data ER output from the motion vector detection circuit 6, the requantization circuit 18 outputs the error data ER, the output data amount of the discrete cosine transform circuit 12, Requantization is performed with a quantization step size corresponding to the input data amount of the buffer circuit 21.

Thus, while performing the weighting process, the error data ER,
By requantizing with a quantization step size corresponding to the output data amount of the discrete cosine transform circuit 12 and the input data amount of the buffer circuit 21, the moving image video signal is of high quality and each frame data is of a predetermined data amount. Can be transmitted.

The requantized image data is subjected to a variable length encoding process in a run-length Huffman encoding circuit 30, and then to a transmission data combining circuit 32, which is subjected to a variable length encoding process in accordance with a predetermined format. Recorded on a compact disc in a predetermined format.

On the other hand, the motion vector detected by the motion vector detection circuit 6 is output to the run-length Huffman coding circuit 34.

Here, the motion vector is converted into a vector for one frame, and then adaptively encoded. The data representing the type of the residual data and the motion vector (ie, the pre-prediction reference index PID, the post-prediction reference index NID, the temporary index) TR can be detected) and recorded on a compact disc.

Further, the requantized image data is supplied to an inverse requantization circuit.
22, inverse multiplication circuit 24, discrete cosine inverse conversion circuit
26, the data is inversely converted to the input data of the discrete cosine conversion circuit 12, and then the adaptive prediction circuit 10
_Is added to the prediction data D _PRI output from, to convert the input data of the subtraction circuit 8 into frame data _DF reproduced.

Thus, the frame data _DF is stored in the adaptive prediction circuit 10, and is used as a prediction frame for pre-prediction and post-prediction, respectively.

As a result, the prediction data _DPRI is created for the frame data subsequently input to the subtraction circuit 8, and the transmission frame data DATA can be sequentially obtained.

On the other hand, in the receiving device 200, the reproduction data D _PB obtained by reproducing the compact disc is
After the head of each frame group is detected, it is output to the rearrangement circuit 203 together with the detection result, and the frame data PA0, PB3, PC1, PC2,... … Continuous image data D
_Sorted into _VPBN .

The rearranged frame data is stored in a buffer circuit 204.
Is output to the separation circuit 206, where the frame group index GO added to the frame data and transmitted.
F, the pre-prediction reference index PID, the post-prediction reference index NID, and the like are reproduced.

The frame data output from the separation circuit 206 is supplied to a run-length Huffman inverse encoding circuit 210 and an inverse requantization circuit 21.
1, inverse multiplication circuit 212, discrete cosine inverse conversion circuit
The input data of the discrete cosine conversion circuit 12 is reproduced by the inverse conversion via 213.

The output data of the discrete cosine inverse transform circuit 213 is added to the prediction data D _PRI output from the adaptive prediction circuit 214 by an addition circuit 218, and the resultant addition data is obtained.
D _TIN is output to adaptive prediction circuit 214.

In the adaptive prediction circuit 214, the transmitted DC level data DC is output as the prediction data _DPRI for the frame data subjected to the intra-frame encoding processing, whereby the frame data A0, A6, and A12 are output through the addition circuit 218. Are successively reproduced to obtain output data _DTIN .

Frame data A of the output data D _TIN of the adder circuit 218
0 and A6 are used in the adaptive prediction circuit 214 to decode the following frame data B3, C1, C2, C4,..., And the decoded frame data A0, A6, B3, C1, C2, C4,. The selection prediction circuit 214 can reproduce the moving picture video signal which is arranged and output in the original order and thus transmitted with high efficiency coding.

(G4) Effect of Embodiment According to the above configuration, the double vector MV1N, MV2P, MV4
By converting the N, MV5P and triple vectors MV3N and MV3P into vectors for one frame, and performing variable-length encoding with priority on the one with a high appearance probability, encoding can be performed using a common table. Thus, the motion vector can be optimized with a simple configuration.

(G5) Other Embodiments (1) In the above-described embodiment, a case is described in which successively continuous frame data is divided in units of six frames, and motion vectors separated by two and three frames detected therein are transmitted. As described above, the present invention is not limited to this,
The present invention can be widely applied when transmitting a motion vector between frames separated by a plurality of frames.

(2) Further, in the above-described embodiment, the case where a video signal is recorded on a compact disk has been described. However, the present invention is not limited to this, and when recording a video signal on various recording media such as a magnetic tape, the present invention is further applicable. Can be widely applied to direct transmission to a receiving device.

H Effects of the Invention As described above, according to the present invention, a quotient and a remainder are obtained by performing a division operation on data based on a motion vector between the first and second images, and the quotient is calculated using a predetermined VLC table. Variable length code to generate a variable length code and transmit the information indicating the divisor used in the division operation, the variable length code, and additional bits indicating the remainder, to optimize the motion vector with a simple configuration. And a motion vector decoding method and a motion vector decoding method and a motion vector decoding method and a motion vector decoding method.

[Brief description of the drawings]

FIG. 1 is a schematic diagram for explaining a video signal transmission system according to an embodiment of the present invention, FIG. 2 is a schematic diagram for explaining its operation, and FIG. 3 is a block diagram showing the overall configuration of a transmission apparatus. ,
FIGS. 4 (1) and (2) are block diagrams showing a motion vector detecting circuit, FIGS. 5 (1) and (2) are schematic diagrams for explaining the operation, and FIG. 6 is a diagram for explaining frame data. 7 and 8 are schematic diagrams for explaining the principle of motion vector detection, FIG. 9 is a characteristic curve diagram for explaining priority detection of motion vectors, and FIG. 10 is a run-length Huffman. FIG. 11 is a block diagram showing an encoding circuit, and FIGS. 11 and 12 are schematic diagrams for explaining the encoding process of a motion vector.
13 and 14 are schematic diagrams for explaining a read-only memory circuit, FIGS. 15 and 16 are schematic diagrams showing encoded motion vector data, and FIG. 17 is a block diagram showing a receiving apparatus. FIG. 18 is a schematic diagram for explaining the operation, and FIG.
FIG. 19 and FIG. 20 are schematic diagrams used to explain the problem. 1 ... transmitting device, 4, 33, 203 ... rearranging circuit, 6 ...
Motion vector detection circuit, 10, 214 ... Adaptive prediction circuit, 18
…… Requantization circuit, 22, 211 …… Inverse requantization circuit, 200…
... Receiving device.

Claims (8)

(57) [Claims] 1. A motion vector transmitting method for transmitting a motion vector between a first image and a second image, wherein a division operation is performed on data based on the motion vector to obtain a quotient and a remainder. A motion vector transmission characterized by generating a variable length code by performing variable length coding using a VLC table, and transmitting information indicating a divisor used in the division operation, the variable length code, and an additional bit indicating the remainder. Method. 2. The variable length code according to claim 1, wherein said additional bit is added after a least significant bit of said variable length code.
2. The motion vector transmission method according to item 1. 3. A motion vector transmitting apparatus for transmitting a motion vector between a first image and a second image, comprising: means for dividing a data based on the motion vector to obtain a quotient and a remainder; A variable-length coding unit that generates a variable-length code by performing variable-length coding using a predetermined VLC table; and transmits information indicating a divisor, and the additional bits indicating the variable-length code and the remainder used in the division operation. A motion vector transmission device, comprising: transmission means. 4. The motion vector transmission device according to claim 3, wherein said transmission means adds said additional bit after a least significant bit of said variable length code. 5. An encoder divides data based on a motion vector between the first and second images to obtain a quotient and a remainder, and encodes the quotient into a variable length code using a predetermined VLC table. Motion vector decoding for generating a variable length code by decoding the information indicating the divisor used in the division operation and the encoded motion vector data transmitted in the form of the variable length code and the additional bit indicating the remainder. Receiving the information indicating the divisor used in the division operation, the variable length code, and the additional bit indicating the remainder, the information indicating the divisor used in the received division operation, the variable length code, and the remainder. A motion vector decoding method characterized by decoding the additional bits shown to reproduce the motion vector. 6. The motion vector decoding method according to claim 5, wherein the additional bit is added after a least significant bit of the variable length code. 7. An encoder performs a division operation on data based on a motion vector between the first and second images to obtain a quotient and a remainder, and encodes the quotient into a variable-length code using a predetermined VLC table. Motion vector decoding for generating a variable length code by decoding the information indicating the divisor used in the division operation and the encoded motion vector data transmitted in the form of the variable length code and the additional bit indicating the remainder. In the conversion device, means for receiving information indicating the divisor used in the division operation, the variable length code and an additional bit indicating the remainder, information indicating the divisor used in the received division operation, and a variable length code Means for decoding an additional bit indicating a remainder to reproduce the motion vector. 8. The motion vector decoding apparatus according to claim 7, wherein the additional bit is added after a least significant bit of the variable length code.