JP2707595B2 - ROM code number reading circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ROM code number reading circuit, and more particularly, to an integrated circuit including a ROM of an ion implantation switching system, a ROM code attached to identify contents of the ROM. It relates to a circuit for reading a number.

[Conventional technology]

Generally, in an integrated circuit including an ion implantation switching type ROM, it is common that lots having different ROM contents are simultaneously flowing through a production line at the time of manufacturing. Mixing may occur in a wafer or a product assembled with resin encapsulation, and it is necessary to read and confirm the contents of the ROM of the product assembled with the wafer or resin encapsulation.

In an integrated circuit including an ion implantation switching ROM, no trace of the ion implantation remains on the wafer, so even if a code number that identifies the contents of the ROM is implanted on the ion implantation mask, the appearance of the wafer can be improved. It is not possible to know the code number of the identification simply by looking at the microscope.

Therefore, conventionally, to know the code number for identifying the contents of the ROM from the wafer, as shown in FIG. 3, the gate and the source are ground potentials (hereinafter referred to as GND), and the drains are the test pads PAD1 'to PAD12'. The N-channel transistors 301 to 312 connected to are connected by the number necessary to represent the ROM code number, and are read out.

In this case, the three decimal digits of the 1 digit, the 10 digit, and the 100 digit are each represented by 4 bits so that a code number for identifying the contents of the ROM from 000 to 999 can be represented. The first place is N
The order of the channel transistors 301 and 10 is the N-channel transistor 305, and the order of the 100 is the N-channel transistor 30
Let 9 represent the LSB.

When the ROM code number is "024", ions are implanted into the N-channel transistors 303 and 306 of FIG. 3 on the ion implantation mask. Even if the gate is connected to GND, applying a voltage to the drain causes a drain current to flow in the ion-implanted N-channel transistor.
Probes are connected to the test pads PAD1 'to PAD12' shown in FIG. 3, and if a current flows, it is determined to be "1". If no current flows, it is determined to be "0".

Since no ion is implanted at the hundreds digit, no current flows through the N-channel transistors 309 to 312, so that "0000" is displayed in binary notation and a decimal "0" is read. Since it is injected, it becomes “0100” in binary notation and the decimal “2” can be read.
Since the first digit is ion-implanted into the N-channel transistor 303, it becomes "0010" in binary notation and becomes "4" in decimal notation.
Can be read, and as a result, a three-digit ROM code number “024” of a decimal number is read.

[Problems to be solved by the invention]

In the conventional ROM code number reading circuit described above, in addition to the normal bonding pads of the semiconductor integrated circuit, a test pad for reading a code number for identifying the contents of the ROM is provided on the wafer. When the code number to be read is read, the test probe must be set up on the test pad. However, since the probe is manually operated using a probe connection device, it cannot be easily performed.
In addition, since the code number can be read only in a wafer state, there is a fatal defect that the code number cannot be read in a product sealed with resin.

In contrast to the above-described conventional ROM code number reading circuit, the present invention uses the sources of the two N-channel transistors as power sources.
The gate is connected to GND, the drain is connected to GND, and the signal at the connection point and the internal ROM are switched by a test signal and output to the output terminal of the ROM. One of the two transistors is ion-implanted so as to output "1" in accordance with the bit contents constituting the ROM code number, and the binary information is switched to the output terminal of the ROM for output. By doing so, it has an original content that you can know the ROM code number.

[Means for solving the problem]

The ROM code number reading circuit of the present invention is a circuit for reading a ROM code number in an integrated circuit including an ion implantation switching type ROM, wherein the ROM code number is connected in series between a power supply and GND, and each gate is connected to GND. Number of N-channel transistors equal to the number of bits constituting the number, and the two N-channel transistors
When ions are implanted into the N-channel transistor on the power supply side of the channel transistor and not implanted into the N-channel transistor on the GND side, a high level (corresponding to bit data 1) is obtained from the connection between the two N-channel transistors.
When the ion signal is extracted into the N-channel transistor on the GND side of the two N-channel transistors and is not implanted into the N-channel transistor on the power supply side, a low level (bit data 0
The output signal of the N-channel transistor and the bit output of the ROM are switched in response to a test signal to exclusively output the output terminal of the ROM. And a transfer gate for outputting.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, which corresponds to a 12-bit output ROM.

Each pair of 100 and 101, 102 and 103 is composed of two N-channel transistors connected to the power supply and GND, each gate to GND, and one drain to the other drain for ion implantation. , 105 and 104 are transfer nodes for switching the connection point between the N-channel transistors 100 and 101 and the output signal OUT1 of the ROM 113, and 107 and 106 are
A connection point of the channel transistors 102 and 103 and a transfer gate for switching the output signal OUT2 of the ROM 114, an inverter 108 for inverting a test signal, 109 to 112 for an output buffer, and PAD1 to PAD12 are output terminals of the ROM.

If the test signal TEST is set to “0” during normal operation,
Output signals OUT1 and OUT2 from ROM 113 and 114 are output terminals PAD1 to PAD
Output to AD12.

When reading the ROM code number, the test signal TEST is set to "1" and the connection point of the two N-channel transistors connected in series is connected to the output terminal PAD1 through the inverters 109 to 112.
~ Output to PAD12.

When outputting "0" as the output signals OUT1 and OUT2 of the ROMs 113 and 114, ion implantation is performed to synchronize with the N-channel transistors 101 and 103, and "1" is output as the output signals OUT1 and OUT2 of the ROMs 113 and 114. In this case, ion implantation for synchronizing with the N-channel transistors 100 and 102 is performed. When the ROM code numbers 000 to 999 are represented by three decimal digits, twelve output terminals may be used since four bits represent the decimal number of one digit in binary.

As described above, if ions are implanted into either the power supply side or the GND side transistors corresponding to the numbers for identifying the contents of the ROM, the test signal TEST is set to “1”, and the output is A code number for identifying ROM contents can be output to terminals PAD1 to PAD12.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
It corresponds to a 4-bit output ROM.

Reference numerals 200 to 211 denote N-channel transistors whose gates are connected to GND and whose drains are connected to each other in order to perform synchronized ion implantation, and 200 to 201, 202 and 203, 204 and 205
LSB of 1 digit, 10 digit, 100 digit, 206 and 207,208 and 209,21
0 and 211 are used to represent the 1's digit, 10's digit, and 100's MSB, respectively. 212 to 219 are transfer gates for switching a signal at a connection point of two N-channel transistors connected in series and output signals OUT1 to OUT4 from a ROM (not shown), and 224 to 229 are decoders for test signal TEST1 and TEST2 signals. , Four NOR gates and two inverters, 230 to 223 are output buffer inverters, and PAD1 to PAD
D4 is an output terminal of the ROM.

During normal operation, both test signals TEST1 and TEST2 are set to “0”
Output terminal PA of the output signals OUT1 to OUT4
Output to D1 to PAD4.

When reading the ROM code number, it is 1 in binary 4 bits.
The ROM code is assigned to the output terminals PAD1 to PAD4 by associating the 1 digit, 10 digit, and 100 digit represented by two decimal numbers with the test signals TEST1, TEFT2 “01”, “10”, and “11”, respectively. Print the number.

In this embodiment, by using two test signals,
The number of ROM output signals that read the ROM code number
There is an advantage that the number of bits can be greatly reduced from 12 in the first embodiment to 4 and the present invention can be applied to a ROM having a small number of output bits.

In the above embodiment, the ROM code number is set to 10
The case of a three-digit base number will be described, but it is clear that an appropriate number of bits may be selected according to the number of digits of the number for identifying the contents of the ROM.

〔The invention's effect〕

As described above, the present invention converts a plurality of transistor pairs in which a ROM code number is written and a ROM output signal into
The configuration is such that it is switched by a test signal and exclusively output to the ROM output terminal, so that the complicated operation of connecting the probe to the test pad as in the past is not required, and the normal ROM output is probed in the wafer state. You can easily read the number that identifies the contents of the ROM simply by connecting the needle of the card.
Further, even in a product assembled by resin sealing, there is an unprecedented effect that the identification number of the ROM can be read directly from the pins of the IC.

In particular, R due to mixing with another lot with a different ROM content
At the time of confirming the number for identifying the contents of the OM, the number for identifying the contents of the ROM can be easily read.

Also, at the time of wafer P / W test, the tester automatically reads the number of the ROM of the wafer, selects the test pattern corresponding to the content of the ROM, and tests it. It is also possible to do a P / W test.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a second embodiment of the present invention, and FIG. 3 is a conventional circuit diagram. 100 to 103,200 to 211,301 to 312 ... N-channel transistor, 104 to 107,212 to 219 ... Transfer gate, 10
8,109-112,230-233,228,229 ... Inverter for inverting transfer gate switching signal, 113 ... ROM, 224-227 ...
NOR gate, PAD1 to PAD12 ... Output terminals, PAD 'to PAD1
2 '… Test pad.

Claims (1)

(57) [Claims] 1. A circuit for reading a ROM code number in an integrated circuit including an ion implantation switching type ROM, wherein a bit is connected in series between a power supply and a GND, and each gate is connected to the GND and constitutes the ROM code number. The same number of two N-channel transistors, the two N-channel transistors being ion-implanted into N-channel transistors on the power supply side of the two N-channel transistors and not being implanted into the N-channel transistors on the GND side; A high-level (corresponding to bit data 1) output signal is taken out from the connection portion of the N-channel transistor, and ions are implanted into the N-channel transistor on the GND side of the two N-channel transistors and ion-implanted into the N-channel transistor on the power supply side When not injecting, a low level (corresponding to bit data 0) output signal is taken out from the connection section. Further, a transfer gate for switching between an output signal of a connection portion of the two N-channel transistors and a bit output of the ROM in response to a test signal to exclusively output to an output terminal of the ROM is provided. Characteristic ROM code number reading circuit.