JP2698431B2 - Timeout detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding a timeout detection device for monitoring the time of an instruction accompanied by a temporary suspension of a CPU, it has conventionally been difficult to set an optimal timeout time for each event, and to operate the system. A first register for accepting an external time-out time setting value asynchronously with a system operation; and a first register for receiving the time-out time setting value from outside. A second operating in synchronization with the system that receives the value
, A circuit for instructing the contents of the first register to be transferred to the second register in synchronization with the system, a timeout counter, a timeout value is not detected for a specific value of the set value, and other settings are not performed. Means for detecting a timeout based on the count value of the counter is provided.

[Industrial Application Field] The present invention relates to a timeout detection device provided in an information processing system for monitoring the time of an instruction accompanied by a temporary suspension of a central processing unit (hereinafter, also simply referred to as a “CPU”).

2. Description of the Related Art A timeout detection device has at least one timeout counter for monitoring the time of an instruction such as an I / O (input / output) instruction and a DIAGNOSE (diagnosis) instruction that involves a pause of a CPU. . I / O for this timeout
This will be described using an instruction as an example. When the CPU executes the I / O command, the CPU temporarily suspends until the I / O device receives the command and returns a response. If the I / O device or the like normally returns a response to the instruction, the pause of the CPU is released, and the processing is resumed from the next instruction. However, if the I / O device does not respond for some reason, the CPU will remain in a dormant state forever, and eventually the system will stop. In order to avoid this problem, in the case of instructions that involve a temporary suspension of the CPU, after the instruction is started, a certain period of time determined by each instruction waits for the end of the instruction. As a result, a time-out interrupt is generated, and a time-out process is performed.

Hereinafter, a specific example will be described. FIG. 2 is a diagram showing a configuration example of a conventional timeout detection circuit. FIG. 2A shows a configuration diagram, and FIG. 2B shows a count state of a timeout counter in the configuration diagram.

In the example of the figure, the event for which the timeout time is to be measured is A
5-1 to A-3 are examples of three types, where 51 and 52 are NOR circuits (NOR), 53 is a timeout counter, 54 to 56 are AND circuits (AND), and 57 is an OR circuit (OR). The signals of the alphabetic characters are as follows.

+ OPSR_COUNT_DISABLE... This is an operation control signal of the timeout detection circuit. When this signal is “1”, the increment signal (+ INC) to the timeout counter 53 is not input.

−0.25_PULSE …… 0 for counting of the timeout counter.
Pulse at 25-second intervals, + TIME_OUT_A: signal that becomes "1" when a timeout is detected in any of events A-1 to A-3, + INC: timeout counter increment (I
ncrement) pulse, + CLEAR .... Clear signal for clearing the count of the timeout counter 53, + TIME_OUT_A-1 to A-3 ..... each event (A-1 to A-)
This signal is set to “1” when the timeout of 3) is detected.

That is, in this example, when an arbitrary event An (for example, waiting for completion of an I / O instruction) among the events A-1 to A-3 occurs, the fixed period is several hundred milliseconds to several seconds. The time-out counter 53 is incremented by "+1" by a count pulse, for example, a count pulse (-0.25SEC-PULSE) at intervals of 0.25 seconds shown in FIG. 2 (b).

When the count value of the timeout counter 53 reaches a predetermined value (3 seconds in the case of the event A-1 in FIG. 2), + TIME_O
Timeout is detected by the signal UT_A-n, and + TIME_OUT_A is generated by the OR circuit (OR) 57, and the signal + TIME_OUT_A is generated.
_OUT_A is returned to the NOR circuit (NOR) 52 to stop the increment signal (+ INC) of the timeout counter 53 and not to count up. Once the timeout signal is generated, until the event An falls,
Continue to generate timeout signal + TIME_OUT_A.

If the event An occurs but the event falls before the timeout occurs, the count of the timeout counter 53 is cleared.

Also, a plurality of monitoring events are provided as shown in FIG.
It is possible to detect multiple timeouts. In this case, it is necessary that the event cannot occur at the same time, such as an I / O instruction completion waiting event and a DIAGNOSE instruction completion waiting event.

[Problem to be Solved by the Invention] In the conventional example described above, the timeout period of several hundred milliseconds to ten and several seconds is predetermined according to the type of instruction, and this time-out time changes even if the speed of the I / O device increases. It was not something. However, if the speed of the I / O device increases, the time required for the I / O instruction should be reduced, and the timeout time should be reduced.

In addition, as the speed of the SVP (service processor) for executing the DIAGNOSE instruction increases, the timeout time of the DIAGNOSE instruction should also be reduced.

Especially when building an online system, even if the CPU is stopped for several seconds due to timeout waiting, other C
There is a case where the system is stopped due to being regarded as a hang-up (Hung up) by the PU or another system, and it is strongly desired to reduce the CPU stop time.

Here, as one conventional method, there is a method of changing a predetermined timeout time.
O devices and SVP must be accelerated at once, but it is difficult to accelerate these devices at once.

In addition, it is very difficult to accurately estimate the timeout time of a newly created I / O device before actually operating it. Therefore, a longer timeout period must be set.

Further, in a test or the like, there is a case where a timeout is not desired to be detected. For example, the processing on the SVP side of the DIAGNOSE instruction is performed in steps (INSTRUCTION
In the case of confirming in (STEP), the CPU cannot confirm the response process from the SVP unless it is stopped in a state of waiting for a response from the SVP. For this reason, conventionally, a timeout detection inhibition bit is provided in the OPSR which is the operation signal of the timeout detection circuit,
When this bit is activated, timeout detection has been disabled. However, in this method, it is not possible to activate one of the timeout factors and invalidate the other, so that it is not possible to confirm the DIAGNOSE instruction that performs processing when the I / O instruction times out. This is DIAGNO
This is because if the detection of the timeout is invalidated in order to confirm the SE instruction in steps, the timeout of the I / O instruction that triggers the activation of the DIAGNOSE instruction does not occur.

In addition, since the OPSR is generally designed as a level signal that does not change during operation, if the OPSR is changed to enable / disable the timeout, the CPU must always be stopped.

The present invention has been made in view of the above problems, and has as its object to provide an effective timeout detection device that can set an optimal timeout period for each event.

[Means for Solving the Problems] According to the present invention, the above-mentioned object is achieved by the means described in the claims.

That is, the present invention relates to an information processing system having a timeout detecting device for detecting a timeout of at least one event, wherein the set value of the timeout time of at least one event from the outside is asynchronous with the operation clock signal of the system. A first register for receiving and temporarily storing a set value of a time-out period of at least one event and operating in synchronization with an operation clock signal of the system; The contents of
A circuit for issuing an instruction to shift to the second register in synchronization with an operation clock signal of the system, a timeout counter for measuring a timeout waiting time, and detecting a timeout for a specific value of the set timeout time Means for generating a timeout signal when the time measured by the timeout counter is equal to or greater than the set timeout time when the value is other than the specific value. This is a time-out detection device.

[Operation] In the present invention, the timeout period is changed and invalidated.
By making it configurable while the CPU is running, I / O devices,
Optimum timeout time can be set for SVP, etc., and its validity / invalidity can be controlled for each factor. In addition, by changing the setting of the timeout time, the conventional setting of the timeout time was rather large, but by actually reducing the setting value sequentially from the maximum value while operating repeatedly, the optimum timeout time was set. Can be determined.

This makes it possible to detect an abnormality in an I / O device or the like in a shorter time, which leads to an improvement in the performance of the entire system. Particularly, it is very effective to construct a non-stop (NON-STOP) system.

More specifically, according to FIG. 1, for example, a timeout register is provided to make the timeout time variable. This timeout register is set with the optimal timeout time stored in the SVP before the normal operation of the system.

Here, it is conceivable that the timeout time is given as data of several tens of bits, but generally it is not necessary to be able to set a time of several microseconds in order to set a timeout time of several hundred milliseconds to several seconds. Therefore, it is sufficient to prepare a register having a bit width of about 1 to 4 bits for each timeout time.

At least one value of this timeout register, for example, zero is defined as timeout detection invalidity, and no timeout is detected at this time. With respect to other values, values from the maximum time to the minimum time that may be waited due to the cause are assigned so as to have an appropriate time interval. The setting of the timeout register is performed, for example, via a console data register that is an interface register with the SVP.

The console data register is written by an asynchronous signal from the SVP, and its contents are written to the timeout register by a signal that synchronizes the timeout register write instruction from the SVP with the system clock. At this time, the timeout counter is also cleared at the same time. By synchronizing the register writing with the system clock in this way, it is possible to change the timeout setting value even during the operation of the CPU during a test or the like.

Embodiment FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 1A is a diagram showing the configuration of the embodiment, FIG. 1B is a diagram showing the counting state of a timeout counter, and FIG. FIG. 5 is a diagram for describing setting of a timeout time.

In FIG. 1, 1 is a NOR circuit (NOR) to which events A-1 to A-3 are input, 2 is a NOR circuit (NOR) to which a count pulse or the like is input, 3 is a time-out counter for measuring time, Is a timeout detector for event A-1, 4a is a 2TO4 decoder for event A-1, 4b to 4d are AND circuits (AND) for event A-1, and 4e is an OR circuit (O for event A-1)
R), 5 is a timeout detector for event A-2, 6 is a timeout detector for event A-3, and 7 is each of events A-1 to A-1.
A-3 is an OR circuit (OR) for obtaining a logical sum of the timeout signal, 8 is a console data register for receiving a set value of the timeout time from the service processor (SVP), and 9 is a system clock signal for setting the timeout value. A time-out register is introduced from the console data register in synchronism with the control signal. A synchronization circuit 10 generates a load signal (LOAD) for introducing the set value of the time-out time from the console data register to the time-out register. 11 is an OR circuit (OR). It represents.

A signal indicated by alphabetic characters is a signal "LOAD" for introducing a set value of the timeout time into the timeout register 9 in synchronization with the system clock. Other signals are the same as those in FIG. is there.

 The operation of the embodiment of the present invention will be described below with reference to the drawings.

Here, the set value of the event A-1 of the time-out register 9 is 2 bits, and the count pulse is 0.0 shown in FIG.
It has a period of 25 seconds. Timeout register 9
Is zero, the timeout detection of event A-1 is disabled, and when the register values are 1, 2, and 3,
A timeout occurs in 1, 2, and 3 seconds. The writing of the set value to the timeout register 9 is first performed asynchronously from the SVP to the console data register 8 by an asynchronous bus (not shown), and then a load instruction (LOAD) from the SVP to the timeout register 9 is transmitted to the synchronization circuit 10. The value of the console data register 8 is loaded into the timeout register 9 by the system clock using the signal synchronized with the system clock. At this time, the contents of the timeout counter 3 are simultaneously cleared. For these reasons, the contents of the timeout register 9 can be changed during the operation of the CPU. The value of the time-out register 9 is decoded by the decoder 4a of 2TO4, and the outputs of the set values 1 to 3 are combined with the desired output of the time-out counter 3 and the signal indicating the event A-1, respectively.
The logical product is taken at 4d, and the logical sum of those outputs is ORed.
Signal + TIME indicating the timeout of event A-1 taken at 4e
_OUT_A-1. Similarly, for the events A-2 and A-3, the corresponding bits of the timeout register 9 are assigned, and unique timeout values are respectively assigned.

FIG. 1C shows the correspondence between the set value of the timeout register 9 and the timeout time.

[Effects of the Invention] As described above, according to the timeout detection device of the present invention, it is possible to set the change and invalidation of the timeout period during the operation of the CPU for each event accompanied by the temporary suspension of the CPU, An optimal timeout period can be set for a device, an SVP, and the like, and its validity / invalidity can be controlled for each factor.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of the present invention, and FIG. 2 is a diagram showing a configuration example of a conventional timeout detection circuit. 1 ... NOR circuit (NOR) to which events A1 to A3 are input, 2 ...
... NOR circuit (NOR) to which count pulse etc. is input, 3
...... Time-out counter for time measurement, 4 ... Event A
-1 timeout detector, 4a ... 2T for event A-1
O4 decoder, 4b to 4d ... AND circuit for event A-1 (AN
D), 4e: OR circuit (OR) for event A-1, 5: timeout detector for event A-2, 6: timeout detector for event A-3, 7: each event A OR circuit (O) for obtaining the logical sum of the timeout signals of -1 to A-3
R), 8: Console data register, 9: Timeout register, 10: Synchronization circuit, 11: OR circuit (OR)

Continuation of the front page (56) References JP-A-63-118955 (JP, A) JP-A-63-73443 (JP, A) JP-A-63-73442 (JP, A) JP-A-62-172442 (JP, A) , A) JP-A-60-235205 (JP, A)

Claims (1)

(57) [Claims] An information processing system having a timeout detecting device for detecting a timeout of at least one event, wherein a set value of a timeout period of at least one event from outside is asynchronously set with an operation clock signal of the system. A first register for receiving and temporarily holding, a second register for holding a set value of the time-out time of the at least one event, and operating in synchronization with an operation clock signal of a system; A circuit that issues an instruction to shift the contents of the second register to the second register in synchronization with the operation clock signal of the system, a timeout counter that measures a waiting time for timeout, and a specific value of the set timeout time If a timeout is not detected and the value is other than the specific value, the timeout In the means for generating a time-out signal when the measured time exceeds or equals the set timeout period, a timeout detecting apparatus is characterized by providing.