JP2697556B2 - Logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention constitutes a digital circuit.
This is related to basic logic gates, especially in milliseconds.
Rain current response, a problem called drain lag
Faster than milliseconds using field effect transistors
The basics used when configuring logic circuits that perform logical operations
It relates to the present logic gate .

[0002]

2. Description of the Related Art GaAs is suitable as a material for high-speed devices in terms of higher electron mobility than Si and low parasitic capacitance due to the use of a semi-insulating substrate.
Schottky gate field effect transistor (GaAsME)
SFETs) are widely used as microwave amplifiers. In addition, digital ICs, which are integrated, have been developed, and have begun to be used for processing digital signals at frequencies exceeding 1 GHz.

[0003] The circuit configuration used when configuring this high-speed digital circuit includes SCFL, DCFL, and BF.
There is something called L. FIG. 2 shows their basic configuration. 2A shows a three-input DCFL NOR circuit, FIG. 2B shows a three-input BFL NOR circuit, and FIG. 2C shows a two-input SCFL NOR circuit.

These are characterized by the required number of power supplies, power consumption, speed, the number of FETs per gate, etc.
They are used according to their characteristics.

[0005]

On the other hand, GaAs-based F
ET has a characteristic abnormality at a low frequency called a low frequency abnormality phenomenon. Among them, a phenomenon called drain lag is that when the drain voltage is changed, the drain current responds to the change with a delay several orders of magnitude slower than the device speed determined by the gate length, parasitic capacitance and transconductance. It is a phenomenon. For example, considering a DCFL inverter as shown in FIG.
A transient response as shown in FIG. This causes the following when focusing on the transistor 2 in FIG. When the voltage of the input terminal 1 is at a low level, the drain voltage of the transistor 2 is at a high level. When the voltage of the input terminal 1 changes from low level to high level, the output terminal 3 changes to low level. If there is no drain lag abnormal phenomenon with respect to the change in the drain voltage of the transistor 2 at this time, the intrinsic speed of the transistor, usually 10 ps
The current flowing through the transistor 2 changes at a speed of 100 psec from ec, and the transistor 2 enters a steady state. However, if there is a drain lag phenomenon, a response on the order of milliseconds as shown in FIG.

When a high-speed digital signal processing is performed by forming a logic circuit using a conventional DCFL circuit or the like with transistors having such characteristics, the ratio of the input signal low to high changes at a certain time interval. In this case, the drain lag phenomenon described above causes a fluctuation in drain current on the order of milliseconds in units of the time interval. This appears as a difference between the rising timing and the rising timing in units of time intervals, so that jitter noise increases. In the worst case,
Malfunction occurs when the ratio of low and high changes.
As described above, the drain lag phenomenon deteriorates reliability at a place different from the place where high-speed operation is performed.

What has been described above is that an IC for microwave application is used.
In the case where the band does not include the response of the drain lag as described above, it does not significantly affect the operation in the steady state, and becomes a problem in a digital IC or an analog circuit having a wide band from DC to high frequency.

An object of the present invention is to provide a logic circuit which is less susceptible to a low frequency abnormal characteristic called a drain lag phenomenon of an FET.

[0009]

A logic circuit according to the present invention comprises a first depletion-type FET having a drain electrode connected to a first power supply terminal, a gate and a source electrode connected to output terminals, and a drain. A first enhancement type FET having an electrode connected to the output terminal, a gate electrode connected to the input terminal, and a source electrode connected to a node; a drain electrode connected to the output terminal; and a gate electrode connected to the input terminal. And a second depletion-mode FET having a source electrode connected to the node, a drain electrode connected to the node, a gate electrode connected to the input terminal, and a source electrode connected to the second power supply terminal. The second connected to
And an enhancement type FET.

[0010]

FIG. 1 shows a single-stage inverter basic gate according to the present invention. The inverter gate includes a transistor TR4, which is a depletion-type FET having a drain electrode connected to the power supply _VDD and a gate and source electrode connected to the output terminal 12, a drain electrode connected to the output terminal 12, and a gate electrode Is connected to the input terminal 11 and the source electrode is connected to the node 13.
, A transistor TR1 which is a depletion-type FET having a drain electrode connected to the output terminal 12, a gate electrode connected to the input terminal 11, and a source electrode connected to the node 13, and a drain electrode connected to the node 13, the gate electrode is connected to the input terminal 11, and the source electrode is grounded.
And a transistor TR3 that is an ET.

When the input terminal 11 is low, the enhancement
The field-effect transistors TR2 and TR3 are off
And the field effect transistors TR2 and TR3 from the output terminal
Since only a small amount of current flows, such as leakage current,
A power supply voltage appears at the output terminal 12, and a high level appears.
Here, a field effect transistor, which is a depletion type FET, is used.
The transistor TR1 is connected to the input terminal 11 by a field effect transistor.
It becomes the form of the source follower with the load on the star TR4
The potential V of the terminal 13 is a field-effect transistor
Determined by the threshold value of TR1, the voltage is raised to V = (potential of input terminal)-(threshold value of field effect transistor TR1) .

Here, the operation of the field effect transistor TR1 is described.
If the threshold is appropriately selected, the potential of the terminal 13 becomes high level.
Output terminal 12 can be reduced to half. As a result,
Drain applied to field effect transistors TR2 and TR3
The in-voltage can be reduced to half the logic amplitude.
Wear.

The drain lag is the drain lag as described above.
A phenomenon in which the drain current fluctuates due to voltage fluctuation.
Therefore, the amount of change in drain current is related to the amount of change in drain voltage.
It is a phenomenon modeled by numbers. For example, N. Sch
einberg etc. (Journal of Solid
-State Circuit, Vol. 23, NO.
2, p605, 1988)
Instantaneous change when the voltage changes stepwise from 0 V to Vds
ΔId between the drain current and the steady state drain current between
Sets the gate voltage to Vgs and the transistor threshold to V
t and α, β, γ, and λ are constants and are expressed as Equation 1.
It is.

(Equation 1) ΔId = β (1 + λVds) tanh (αVds) ((γVds) ^Two  + 2γ ( Vgs-Vt) Vds) The amount of change in drain current with respect to drain voltage is simply
Although not proportional, the larger the drain voltage variation is,
Fluctuations increase. Therefore, as mentioned above,
The drain voltage applied to the transistors TR2 and TR3 is halved
Will be able to reduce the drain current fluctuation
Become.

In order to examine the effects of the present invention, a
N. road shown earlier. In a paper such as Scheinberg,
Field-effect transistor that models the drain lag
As a result of circuit simulation using
Sex was improved. As for the evaluated parameters, as shown in FIG. 3B, the output of the inverter when the input was changed from low to high was monitored, and the difference between the initial response and the low level in the steady state was defined as ΔV. Note that ΔV when simulating with the conventional DCFL shown in FIG.
The parameters of the drain lag model of the FET are selected so that

[0015]

[Table 1]

Here, W _TR1 and W _TR3 are the transistor widths of the transistors TR1 and TR3, respectively, and V _thTr1 is the threshold value of the transistor TR1. Thus, 30
% To about 50%.

Although the configuration of the inverter has been described above, when the transistors TR1, TR2 and TR3 are connected as one unit in parallel as shown in FIG. 4, a NOR logic circuit is obtained. When one unit is connected in series,
As shown in FIG. 5, it becomes a NAND logic circuit .

Here, the description has been given from the standpoint of a GaAs-based FET, but the present invention can be applied to other single-crystal SiFETs and amorphous Si FETs. Due to the nature of the drain lag, the greater the amount of change in the drain voltage, the greater the effect. Therefore, the present invention can exert an effect in a circuit having a large logic amplitude.

[0019]

According to the circuit system of the present invention, D
Compared with the CFL circuit, the output response abnormality due to the drain lag is improved by about 30% to 50% in the response characteristic of the inverter.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an inverter showing one embodiment of the present invention.

FIG. 2 is a diagram showing a basic gate of a conventional logic circuit.

FIG. 3 is a diagram illustrating an example of a response waveform of a circuit when a DCFL inverter is configured by a DCFL inverter circuit and a FET indicating a drain lag abnormality.

FIG. 4 Transistor TR1, TR2, TR3 is one unit
FIG. 2 is a diagram illustrating a NOR circuit configured by connecting in parallel as a unit.
You.

FIG. 5 Transistor TR1, TR2, TR3 is one unit
FIG. 2 is a diagram showing a NAND circuit connected in series as a
You.

[Explanation of symbols]

 11 input terminal 12 output terminal TR1, TR2, TR3, TR4 Transistor

Claims (3)

(57) [Claims] A first depletion-mode FET having a drain electrode connected to a first power supply terminal and a gate and a source electrode connected to an output terminal; a drain electrode connected to the output terminal; Is connected to an input terminal, a first enhancement type FET having a source electrode connected to a node, a drain electrode connected to the output terminal, a gate electrode connected to the input terminal, and a source electrode connected to the node. A second depletion type FET having a drain electrode connected to the node, a gate electrode connected to the input terminal, and a source electrode connected to a second power supply terminal. A logic circuit, comprising: 2. The first enhancement type FET,
A circuit portion composed of the second enhancement type FET and the second depletion type FET is
The drain of the first enhancement mode FET and the drain of the first
The drain of the depletion type FET of No. 2 is connected
The terminal is a first terminal, and the second enhancement type FE is
A first unit having a source terminal of T as a second terminal;
And connect multiple units in parallel with each terminal
2. The logic circuit according to claim 1, wherein the combined unit is replaced with a first unit . 3. The first enhancement type FET,
A circuit portion composed of the second enhancement type FET and the second depletion type FET is
The drain of the first enhancement mode FET and the drain of the first
The drain of the depletion type FET of No. 2 is connected
The terminal is a first terminal, and the second enhancement type FE is
A first unit having a source terminal of T as a second terminal;
A composite unit in which a plurality of these units are vertically connected in series
2. The logic circuit according to claim 1, wherein the unit is replaced by a first unit .