JP2695410B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is a read-only-memory (hereinafter referred to as ROM).
The present invention relates to a semiconductor integrated circuit device for reading a device. [Prior Art] A semiconductor integrated circuit device for reading a conventional ROM device is shown in FIG. In the figure, Q _N is a memory transistor, Q _{L to} Q _M
Is a transistor forming a bit line decoder selected by a bit line selection address (hereinafter referred to as Y address),
_{Q 1, Q 2, Q 3} , Q 4 are P-channel type _{transistor, Q 5, Q 6, Q} 7,
Q ₈ , Q ₉ and Q ₁₀ are N-channel type transistors, A is general R
OM device 1 bit line type CMOS sense amplifier, B is CM
OS differential amplifier, H is a constant voltage source for reference of the differential amplifier. Next, the operation will be described. Transistor of bit line decoder depending on Y address
When Q _{L to} Q _M are selected and turned on, the selected bit line M and common bit line C are connected. At this time, a "H" level as a selection signal is supplied to the gate of the memory transistor Q _N by the word line selection address (hereinafter, X address). At this time, the memory transistor Q _N has a threshold voltage (hereinafter
It is turned on or off in accordance with V _th ), but when V _th is lower than the “H” level of the X address, it is turned on, the common bit line C becomes “L” level, and V _th is When the voltage is higher than the "H" level of the X address, it is turned off and the common bit line C becomes "H" level. The level of the common bit line C is amplified by the P-channel type transistor Q ₂ and the N-channel type transistor Q ₇ and input to the differential amplifier B. At this time, the "H" level signal is input to the differential amplifier _{B "H 1", "L} " level "L _1"
Then, the potential of node D becomes "H ₁ " as shown in Fig.4.
- "L _1" during the memory transistor Q _N "0", varies in accordance with the "1". In the differential amplifier B, a constant voltage source H is connected to the normal node E as a reference power source of the differential amplifier B, and its potential is an intermediate potential between “H ₁ ” and “L ₁ ” (hereinafter referred to as “K” level). It is said that. Therefore, when the memory transistor Q _N changes from "0" to "1" in response to X or Y address switching, the potential of the node D changes from "H ₁ " to "L".
"Although the, the" ₁ "during the transition to, potential" L ₁ "from" H ₁ b, is reversed when it exceeds K "level consists previous state and the next state, a new memory information Amplify and output.
Similarly, when the memory transistor Q _N changes from "1" to "0", the potential of the node D changes from "L ₁ " to "H".
₁ "goes to," when it exceeds K "level, b, becomes to convey new information is inverted. Memory transistor Q _N
Is changed from "1" to "1" and from "0" to "0", the potential of the node D does not exceed the "K" level, and therefore the previous state is maintained. [Problems to be Solved by the Invention] Since the conventional semiconductor integrated circuit device is configured as described above, the time t ₁ from “H ₁ ” to “K” in FIG. 4 exceeds t ₁
And the time t ₂ from “L ₁ ” to “K” is almost the same, and the “K” level is set to “H ₁ ” to speed up the access time.
As shown in Fig. 5 (a), t ₁ becomes smaller and "H ₁ " → "K" becomes faster, but t ₂ becomes larger and "L ₁ " → "K" becomes It will be slower, and the "K" level will be changed to "L ₁ " as well.
As shown in FIG. 5 (b), when t ₂ becomes smaller, t ₁ becomes larger as t ₂ becomes larger, the balance between the two is lost, and the access time cannot be shortened. Also, as shown in Fig. 6, bring "H ₁ " and "L ₁ " close to each other and interpose the change width.
If t ₁ and t ₂ are reduced, even a faint noise or the like malfunctions, and the operation margin is lost, making it difficult to speed up the access time. The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor integrated circuit device capable of speeding up access time while maintaining a wide margin. [Means for Solving Problems] A semiconductor integrated circuit device according to the present invention is a memory circuit including a sense amplifier and a differential amplifier, is connected to the same common bit line as the sense amplifier, and is similar to the sense amplifier. A negative-phase signal circuit that outputs a negative-phase signal having a smaller amplitude than the output signal of the sense amplifier earlier than the output of the sense amplifier in response to a change in the common bit line is used as the reference voltage source. It is a thing. [Operation] In the present invention, the output signal of the negative-phase signal circuit serving as the reference voltage source also changes according to the change of the output signal of the sense amplifier.
The time from the start of change to the coincidence with the output signal of the anti-phase signal circuit is shortened, and the access time can be shortened. Embodiment An embodiment of the present invention will be described below with reference to the drawings. First
The figure shows a semiconductor integrated circuit device according to an embodiment of the present invention. In the figure, F is a negative-phase sense amplifier (negative-phase signal circuit) composed of transistors Q ₁ ′ and Q ₅ ′, and the other structure is the third. The description is omitted because it is the same as the conventional example shown in the figure. 2 shows the waveform of each part of the circuit device of this embodiment, where N is the output of the anti-phase sense amplifier F, which is also the reference potential of the differential amplifier B.
P is the output of the sense amplifier B, which is "H ₁ " and "L ₁ ".
It changes between. Next, the operation will be described. Memory transistor Q _N, memory information "1" of the memory transistor Q _N the transistor Q _L to Q _M of the bit line decoder is selected respectively to the common bit line C or "0" is transmitted. This minute change is input to the first-stage inverter circuit consisting of transistors Q ₁ and Q ₅ and amplified,
It is amplified and shaped into a wider amplitude by the next-stage inverter circuit composed of Q ₂ and Q ₇ , and input to the differential amplifier B via the node D. In parallel with this operation, the transistor Q ₁ ′, Q
_The negative-phase sense amplifier F composed of an inverter circuit composed of ₅ ′ performs the same operation as the first-stage inverter circuit of the sense amplifier A and outputs it to the node E. The differential amplifier B receives both outputs from the node E and the node D, determines and amplifies them, and outputs b. At this time, the change in the potential of each node is as shown in FIG. In FIG. 2, the period T ₁ is the time when the memory transistor Q _N is “0”, T ₂ is “1”, and T ₃ is “0” again. First, during T ₁ , node D is stable at “H ₁ ”, and node E is stable at “L ₂ ”. Next, when the memory transistor Q _N changes from "0" to "1", the node E changes gradually from "L ₂ " to "H ₂ " in response to the change in the voltage of the common bit line C, and the node D changes. Also gradually changes from "H ₁ " to "L ₁ " with a delay of one stage (t ₀ ) of the inverter circuit. The nodes E and D change toward each other and cross at the potential "K _H ". At this time, the output b of the differential amplifier B,
Is inverted. If the time until this crossover is t ₁ ′,
Relationship between the time t ₁ until beyond the fourth conventional decision point shown in FIG. "K" is, t ₁ 'the <t _1. And when entering the period T ₃ ,
This time, the node E changes from “H ₂ ” to “L ₂ ”, one inverter circuit stage later (t ₀ ), the node D also changes from “L ₁ ” to “H ₁ ”, and the potential “K _L "Cross with. At this time, the output b of the differential amplifier B is inverted again. If this time is t ₂ ′, the relationship with the conventional required time t ₂ is t ₂ ′ <t ₂ . When the memory transistor Q _N changes from “0” to “0” and from “1” to “1”, there is no problem because the output b, is not inverted as in the conventional case. Thus, in the device of this embodiment, both t ₁ ′ and t ₂ ′ are
It is shorter than ₁ and t ₂ , and the total access time is shortened. Further, such a circuit device can be configured by using the same circuit element, and since the output timings of the sense amplifier and the anti-phase signal circuit are relative, flexibility can be well determined, It is possible to easily manufacture a device having a desired function. As described above, according to the semiconductor integrated circuit device of the present invention, a negative-phase signal circuit that outputs a negative-phase signal having an amplitude smaller than that of the output signal of the sense amplifier earlier than the output of the sense amplifier is provided. Since it is provided and used as the reference voltage source, there is an effect that the access time can be shortened and a device having a good function can be easily obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a diagram showing waveforms of respective parts of the device of the above embodiment, and FIG. 3 is a conventional semiconductor. FIG. 4 is a circuit diagram showing an example of an integrated circuit device, and FIG. 4 is a diagram showing waveforms of respective parts of the conventional example.
5 (a), 5 (b) and 6 are diagrams showing waveforms of an example of speeding up in the conventional semiconductor integrated circuit device. In the figure, A ... Sense amplifier, B ... Differential amplifier,
C: common bit line, D, E ... node, F ... anti-phase sense amplifier (anti-phase signal circuit), H ... constant voltage source for reference, M ... bit line. In the drawings, the same reference numerals indicate the same or corresponding parts.

   ────────────────────────────────────────────────── ─── Continuation of front page    (56) References Japanese Patent Laid-Open No. 61-51696 (JP, A)                 JP-A-59-180891 (JP, A)                 JP 59-231795 (JP, A)

Claims (1)

(57) [Claims] A memory array consisting of a ROM; a bit line decoder in which a plurality of switching FETs for selecting a bit line of the memory array are connected in series; a sense amplifier connected to the top of the bit line decoder; An anti-phase signal circuit which is connected to the top of the line decoder and outputs an anti-phase signal having an amplitude smaller than that of the output signal of the sense amplifier earlier than the output of the sense amplifier, and an output signal of the sense amplifier and the anti-phase signal A semiconductor integrated circuit device, comprising: a differential amplifier which receives an output signal of the circuit and judges selected information. 2. 2. The semiconductor integrated circuit device according to claim 1, wherein the negative-phase signal circuit comprises an inverter circuit having a number of stages smaller than that of the sense amplifier by one or more stages.