JP2690423B2 - Frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer used in the microwave band.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a conventional frequency synthesizer disclosed in Japanese Patent Laid-Open No. 25113/1990. In the figure, 1 is a voltage controlled oscillator that oscillates at a frequency according to an error signal a and outputs a synthesizer frequency signal b to the outside, and 2 is a frequency division number determined according to a frequency division control signal c given from the outside. A frequency divider for dividing the signal output from the voltage controlled oscillator 1. Reference numeral 3 is a phase comparator which compares the phase of the signal output from the frequency divider 2 with the phase of the reference frequency signal d given from the outside, and generates an AC signal e based on the comparison result. This is an active loop filter that filters the AC signal e output from the phase comparator 3 to generate the error voltage a and outputs the error voltage a to the voltage controlled oscillator 1.

Further, in the active loop filter 4, 41 is a plurality of switches which are controlled by an open loop gain control signal f given from the outside and open / close the AC voltage e from the phase comparator 3, 42 Are a plurality of resistors connected to each of the switches 41 for determining the open loop gain of the active loop filter 4. Reference numeral 43 is an operational amplifier in which each of the resistors 42 is connected in parallel to its input terminal and outputs an error voltage a to the voltage controlled oscillator 1 from its output terminal, 44 is its feedback capacitor, and 45 is a feedback resistor. is there.

Numeral 5 gives the frequency division number control signal c to the frequency divider 2 and the open loop gain control signal f to the active loop filter 4 from the outside of the phase locked loop constructed as described above. It is a frequency control circuit.

Next, the operation will be described. As described above, the phase-locked oscillator including the voltage-controlled oscillator 1, the frequency divider 2 whose frequency division number can be changed by the frequency division number control signal c from the external frequency control circuit 5, the phase comparator 3, and the active loop filter 4. The frequency division number N is determined by the frequency division number control signal c from the frequency control circuit 5, and the loop operates as a frequency synthesizer. At that time, the open loop gain control signal f sent from the external frequency control circuit 5 opens and closes the switch 41 of the active loop filter 4 to switch the resistor 42 connected to the operational amplifier 43. The open loop gain is controlled. Then, the open loop gain K _B can be expressed as follows.

[0006] _{K B = K 1 · K 2} · (R 2 / R 1 (N)) / N where, K _1: the voltage controlled oscillator 1 of the modulation sensitivity K _2: detection sensitivity of the phase comparator 3 R _{1 (N )} : Parallel sum of resistance values of the resistor 42 connected to the operational amplifier N: Frequency division number of the frequency divider 2 R ₂ : Resistance value of the feedback resistor 45 of the operational amplifier 43

Accordingly, by setting divided into multiple stages by the R 1 _(N) dividing number N, the value of N is 2 × N, 3 × N, be varied ... to, R 1 and _(N), By controlling so as to be 1/2 times, 1/3 times, ..., It becomes possible to suppress the variation of the open loop gain K _B of the present apparatus, and a microwave band having a stable open loop gain characteristic over a wide band. The frequency synthesizer can be obtained.

[0008]

Since the conventional frequency synthesizer is constructed as described above, a stable open loop gain can be obtained over a wide band, but an active loop filter is provided by the external frequency control circuit 5. 4 has to be controlled, which not only complicates the control, but also increases the control lines from the frequency control circuit 5.
Further, when the frequency is set by the status of the digital switch or the like, the control digital switch of the switch 41 is required, and it is necessary to set them according to the frequency, which complicates the operation. There was a problem.

The present invention has been made to solve the above problems, and a frequency synthesizer in which an appropriate open loop gain is set and good characteristics are obtained by externally setting the frequency. Aim to get.

[0010]

A frequency synthesizer according to the present invention emits at a frequency corresponding to a given error voltage.
Oscillating voltage controlled oscillator and output from the voltage controlled oscillator
Specified signal by the given frequency division control signal
Frequency divider that divides by the number of divisions and output from the divider
The phase of the applied signal with the given reference frequency signal
Phase comparator that generates an AC signal by using
Multiple terminals for determining open loop gain
A resistor is connected to each resistor via a switch
By inputting the AC signal from the phase comparator, the AC signal
Signal to generate an error voltage to the voltage controlled oscillator
Active loop filter, and the active loop filter
The error voltage output by the converter is converted into a digital value and output.
And the frequency synthesizer has locked on.
Analog to put the digital value in hold status when
.Digital conversion circuit and analog / digital converter
The corresponding digital value output from the conversion circuit
Storage means for reading the stored data,
Based on the data read by the storage means,
The switching means for controlling the opening and closing of the switch of the loop filter.
It is provided .

[0011]

The switching means according to the present invention is provided with a given error.
A voltage controlled oscillator that oscillates at a frequency according to the voltage,
Divide the signal output from the voltage controlled oscillator
Divider that divides by the division number specified by the control signal
And the reference frequency given by the signal output from the frequency divider.
Phase ratio to generate an AC signal by comparing the phase with the wave number signal
Open loop gain at the input terminal of comparator and built-in operational amplifier
Multiple resistors are connected to determine each resistor
Input AC signal from the phase comparator through switch
To filter the AC signal to cause the voltage-controlled oscillation.
An active loop filter that produces an error voltage
The error voltage output from the active loop filter is
Converted to digital value and output, the frequency synthesizer
If the sizer locks on, it will
And an analog / digital conversion circuit for setting
The digital signal output from the analog-digital conversion circuit
Corresponding to the digital value, the previously stored data is read out.
Storage means and data read from the storage means
Opening and closing the switch of the active loop filter based on
It is equipped with switching means for controlling and switches according to the frequency division number.
The open / close gain is opened and closed to automatically set the open loop gain.
If the frequency synthesizer is locked on,
Stable by putting the digital value in the hold state
Get open loop gain.

[0012]

[Embodiment 1] An embodiment of the present invention will be described below with reference to the drawings. FIG.
FIG. 3 is a block diagram showing a frequency synthesizer according to Embodiment 1 of the present invention . In the figure, 1 is a voltage controlled oscillator,
2 is a frequency divider, 3 is a phase comparator, 4 is an active loop filter, 5 is a frequency control circuit, 41 is a switch, 42 is a resistor, 43 is an operational amplifier, 44 is a feedback capacitor, and 45 is a feedback resistor. However, since they are the same as or equivalent to those of the related art denoted by the same reference numerals in FIG. 4, detailed description thereof will be omitted.

Reference numeral 6 is a serial-parallel converter (hereinafter, S / S) for converting the frequency division control signal c given from the external frequency control circuit 5 from a serial signal to a parallel signal.
7 is a read-only memory (hereinafter referred to as ROM) as a storage means that is accessed according to the frequency division control signal converted into a parallel signal by the S / P converter 6. is there. Reference numeral 8 is a demultiplexer as switching means for controlling opening / closing of each switch 41 in the active loop filter 4 based on the data read from the ROM 7.

Next, the operation will be described. The frequency division number control signal c given from the external frequency control circuit 5 is input to the frequency divider 2 and also to the S / P converter 6 to be converted into a parallel signal. The output of the S / P converter 6 is connected to the address bus of the ROM 7 and also the ROM 7
Is connected to the input of the demultiplexer 8. Therefore, an address corresponding to the frequency division number designated by the frequency division number control signal c is set in the ROM 7, and the data read from the address is input to the demultiplexer 8. The demultiplexer 8 makes only one of the outputs corresponding to the output data of the ROM 7 significant, so that one of the switches 41 in the active loop filter 4 is turned on.

Here, the resistors 42 connected to the respective switches 41 have different resistance values R _{0 to} R ₃ , and are connected to the closed switches 41 under the control of the demultiplexer 8. The open circuit gains different from each other are set by inputting the AC voltage e from the phase comparator 3 to the operational amplifier 43 via the resistor 42 that is provided. As described above, by writing the predetermined data in the address of the ROM 7 corresponding to the frequency division number, it becomes possible to automatically set the open loop gain corresponding to the frequency division number.

Embodiment 2 FIG. In the above embodiment, the case where the frequency division number control signal c is given as a serial signal has been described, but it may be given as a parallel signal, in which case the S / P converter 6 is not necessary. .

Embodiment 3 FIG. In the first embodiment, the case where each switch 41 of the active loop filter 4 is controlled based on the frequency division control signal c has been described, but the control is performed based on the error signal a output from the active loop filter 4. You may do it. Figure 2 is omitted in block diagram showing a frequency synthesizer in accordance with a third embodiment of such a present invention, a description thereof will be denoted by the same reference numerals to the same parts in FIG. In the figure, 9 is an A / D conversion circuit for converting the error voltage a output from the active loop filter 4 from an analog signal to a digital signal and supplying it to the address bus of the ROM 7.

Next, the operation will be described. When the frequency division number of the frequency divider 2 is set by the frequency division number control signal c given from the external frequency control circuit 5, the error voltage a output from the active loop filter 4 changes and the voltage Controlled oscillator 1
Becomes the voltage level at which the oscillation frequency becomes a frequency corresponding to the frequency division number . On the other hand, output from active loop filter 4
The error voltage a is converted into a digital value having a predetermined number of bits by the A / D conversion circuit 9. A / D conversion circuit 9
The output of is connected to the address bus of ROM7
The OM 7 reads data from the address corresponding to this digital value and outputs it to the demultiplexer 8. Thereafter, as in the case of the first embodiment, this demultiplexer 8
Outputted by turning on one of the switches 41 of the active loop filter 4, the resistance value of the resistor 4 of the R ₀ to R ₃
One of the two is connected to the operational amplifier 43.

Therefore, by storing appropriate data in the ROM 7, it becomes possible to selectively turn on one of the switches 41 according to the frequency division number, and automatically open loop gain gain. Can be set. After the frequency synthesizer locks on, A
A lock-on signal g is applied to the / D conversion circuit 9 to put it in a hold state, and the switch 41 is fixed so as not to switch due to a minute fluctuation of the voltage level of the error voltage a so that a stable open loop gain is obtained. ing.

Embodiment 4 FIG. Next, a fourth embodiment of the present invention will be described with reference to the drawings. Figure 3 is a block diagram showing a frequency synthesizer in accordance with a fourth embodiment of such a present invention, and avoid duplication of description the same reference numerals are given to the same parts in FIG. In the figure, 1
Reference numerals 0 to 13 respectively compare the error voltage a output from the active loop filter 4 with the reference voltages V _{0 to} V ₃ and make a comparison signal significant when the error voltage a is higher. Reference numeral 14 denotes a latch circuit that holds the comparison signal from the comparison means and controls the opening and closing of the switch 41 of the active loop filter 4 based on the held data.

Next, the operation will be described. When the frequency division number of the frequency divider 2 is set by the frequency division number control signal c, the error voltage a output from the active loop filter 4 fluctuates as described in the third embodiment, and the error voltage a changes. 13 is input. Therefore, the comparison signals output from the comparison means 10 to 13 in which the reference voltages V _{0 to} V ₃ lower than the error signal a are output are significant, and the state is held by the latch circuit 14, and the active loop filter 4 is activated. The corresponding switch 41 is turned on. Therefore, the resistance values R _{a to} R of the resistors 42 connected to the respective switches 41 are
_{If d} is set as shown below, it is possible to automatically set the open loop gain as in the first to third embodiments.

R ₁ (N) is converted into R ₀ , R ₁ ,
If R ₂ and R ₃ are switched to, R _{a to} R _d can be calculated by the following formula.
It is sufficient to set it so as to satisfy.

The latch circuit 14 operates when the applied lock-on signal g is a pulse when the lock-off is performed or when the lock-on signal g is changed from the lock-off to the lock-on. Hold the data of and fix the open loop gain.

[0024]

As described above , according to the present invention,
Voltage controlled oscillation that oscillates at a frequency according to the specified error voltage
And a signal output from the voltage controlled oscillator
Divide by the divisor specified by the divisor control signal
Frequency divider and the signal output from the frequency divider.
Generates an AC signal by comparing the phase with the reference frequency signal
Open to the phase comparator and the input terminal of the built-in operational amplifier.
Multiple resistors are connected to determine the loop gain,
AC from the phase comparator through a switch to each resistor
By inputting a signal, the AC signal is filtered and the
An active loop filter that produces an error voltage for a voltage controlled oscillator.
Error output from the active loop filter
Convert the voltage to a digital value and output it,
If the wavenumber synthesizer is locked on, its digit
Analog-to-digital conversion times
Output from the analog-to-digital conversion circuit
Data stored in advance corresponding to the digital value
Is read from the storage means and the storage means
The S w of the active loop filter on the basis of the data
Switch for controlling the opening and closing of the switch.
Therefore, specify the frequency division number from the external frequency control circuit.
It is possible to set an appropriate open loop gain with
Has stable open-loop gain over a wide frequency range.
Frequency synthesizer, and control lines are increased
The frequency that is controlled only by the digital switch.
It has an effect that it can be applied to a wave number synthesizer.
In addition, downsizing and cost reduction of frequency synthesizer are realized.
Has an effect that can be. In addition, the frequency synthesizer
Appropriate open loop even if the error voltage fluctuates slightly after turn-on
It has the effect of maintaining the gain.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a frequency synthesizer according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a frequency synthesizer according to a third embodiment of the present invention.

FIG. 3 is a block diagram showing a frequency synthesizer according to a fourth embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional frequency synthesizer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 voltage controlled oscillator 2 frequency divider 3 phase comparator 4 active loop filter 7 storage means (ROM) 8 switching means (demultiplexer) 9 A / D conversion circuit 10 to 13 comparison means 14 holding means (latch circuit) 41 switch 42 resistor 43 operational amplifier

Claims (1)

(57) [Claims] 1. A voltage-controlled oscillator that oscillates at a frequency corresponding to a given error voltage, and a signal output from the voltage-controlled oscillator is divided by a frequency division number designated by a given frequency division number control signal. A frequency divider for frequency division, a phase comparator for comparing the phase of the signal output from the frequency divider and a given reference frequency signal to generate an AC signal, and an open loop at the input terminal of the built-in operational amplifier. A plurality of resistors for determining the gain are connected, and by inputting an AC signal from the phase comparator through a switch to each resistor, the AC signal is filtered to the voltage controlled oscillator. and active loop filter for generating an error voltage, converts the error voltage output from the active loop filter to Digitally Le value
And the frequency synthesizer has locked on.
An analog-to-digital converter circuit you the digital value to the hold state when, in correspondence with the digital value output from said analog-digital conversion circuits, pre
And SL憶means because the stored data is read, the frequency synthesizer comprising a switching means for performing switching control of the switches of the active loop filter on the basis of the read from the storage means data.