JP2687912B2 - Digital signal recording and transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION The present invention records and rewrites digital signals.
In particular, it distributes error detection and correction codes
Used in interleave circuit to generate and record in configuration
The present invention relates to a preferable digital signal recording and transmitting method. [0002] 2. Description of the Related Art A conventional digital signal recording / reproducing apparatus is
Input as described in JP-A-58-187039.
Interleaving due to block delay between each data
A method of recording and reproducing by applying a curve is adopted. this is
In devices like digital audio tape recorders
High-density recording results in bursty errors.
Increase, but convert this to random error, error detection
When the effect of plus sign is increased and error correction becomes impossible,
If the data before and after the
The correct average value of both data.
The purpose is to perform similar interpolation. Like this
In the case of audio signals and video signals, the average value of the error data is interpolated.
Even if it is, the signal output after D / A conversion is auditory
Or it does not hinder the eyesight. However, floppy
-It is used as a data recorder like a disc.
In a digital signal recording / reproducing device such as
Even if there is an error in the
There should be no leaks or erroneous corrections, and of course mean value interpolation
You can't use a method that converts data such as
No. Therefore, in tape recorders, etc.
To reduce the number, the recording density is lowered to reduce the error rate.
A common method is to reduce the amount. As an example of such a conventional technique, Japanese Patent Application Laid-Open No. 59-59
-84305 gazette is used exclusively for still image information.
For recording on a floppy disk for use with an electronic camera (still
Image using a camera or video floppy system
When recording digital data instead of
Bell. FIG. 2 is a diagram for recording data of an electronic camera.
It is a recording format. In the figure, (a) shows the frame structure.
However, one frame consists of 128 blocks
In addition, 21 corresponds to the head contact start position and is a margin.
Burst signals and the like are recorded. Also, the ID part is entered
This is an area to which a control signal other than the control signal is added. (B)
It shows the structure of one block, Sync is a synchronization signal,
BA is block address and subcode, CRC is B
It is a parity code for detecting an error in the A section. PCMda
The ta area has 32 samples (1 sample
8 bits are all 256 bits) and C₁, C_TwoIs
First for error detection and correction of PCMdata
In the area for recording the second code, for example,
The Lomon code or the like is generated and recorded. 22 is video
It is a magnetic sheet called a loppies disk, 2 in the figure.
Method of recording by dividing into 4 sectors as shown in 3 to 26
Is taken. FIG. 3 shows a conventional interleaved memory.
It is a map. BLOCK in the figure is one block shown in FIG.
S is a predetermined redundancy such as subcode.
An area for recording the code, D is a record of the input PCM data.
Recording area, C₁, C_TwoIs the first and second error detection and correction codes
This is an area for recording a redundant parity code according to. Traditional
With interleaving, each input data in chronological order is
Apply the same delay to the positions shown by arrow B in the figure.
Remember each. Also, from the data located at arrow B
Code C_TwoThe position of arrow Q due to the same delay as above.
To memorize. Furthermore, the first code C₁Is located at arrow A
PCM data and code C_TwoGenerated from and shown by arrow P
As shown in FIG. Where each
Code C from lock synchronization signal₁Up to arrow A and P in this order
Also, read out and record in the order of block numbers. did
Time-series data and code C input afterwards_TwoIs an arrow
The interface delayed by each block as shown by B and Q
-It will take a leave, and C₁Is one block
It will be completed and recorded. [0006] Interleaving according to the above conventional technique is performed.
In the recording method described above, there are two problems. First is heavy
Disappearance when performing after-recording by writing
False detection and correction of errors due to the rest should occur. Second
Is an interleave with a constant delay within a predetermined memory area.
Memory capacity by generating correction code
It is a mismatch with or deterioration of correction capability. Below this section
The subject will be described in detail. FIG. 4 is a diagram for explaining the first problem described above.
Inside a and b are the blocks in each frame signal and their blocks.
It is a check number. Here, (a) shows the signal in a normal state.
It shows the recorded positional relationship and responds to the rotation of the magnetic sheet.
TAC₁It is recorded at the position T that is sandwiched by the pulse.
You. Also, as shown in (a), overwrite from the top
Therefore, when after recording,
TAC_TwoThe position where the pulse is originally recorded as shown in (b) of the figure.
Consider a case where the position is deviated from the position T. At this time after record
The signal after swinging is as shown in Fig. 6 (c) and is indicated by E.
The part is at the end of the after-recording signal (b).
Old block data a₁₂₅, A₁₂₆Is wrong
Suppose At this time a₁₂₇, A₁₂₈Is old data
C is generated and recorded in the block complete form₁Ji by sign
If you check, it is not an error. Also during playback
It is originally recorded like the pulse RP in the figure (c).
The area R that has a margin before and after the area T
Since data detection is performed, after-recording is performed as shown in (b).
When data is read, the data is in the T area b_Three,
b_Four, ..., b₁₂₈, A₁₂₅, A₁₂₆, A₁₂₇, A₁₂₈Of 128
Individuals will be treated as newly recorded data
Become. As a result, a₁₂₅, A₁₂₆Is incorrect
If not, it is not judged as an error b_Three~ B₁₂₈And a₁₂₇,
a₁₂₈Error data a₁₂₅, A₁₂₆Error of
Correction will be made and erroneous correction will occur
become. Therefore, when recording is finished with the conventional device,
The after-recording shown in the shaded area of Fig.
To record no signal for a certain period as a swing margin
Circuit and equipment were required. Next, the second problem will be described. Digital record
The recording device is completed in blocks as described above.
Error correction code C₁Is added, but more effective correction
In a series of crosses that cross these to gain the ability
Second error correction code C_TwoIs often added. this
If the delay between adjacent data is increased,
Has the effect of improving the ability to correct
can get. However, the larger the delay, the more necessary
The required memory capacity also increases. Here certain blocks
C in a frame of numbers_TwoA place to complete the code
In the case of equality, the memory capacity is fixed, so
The maximum effect will be given if a larger delay is given in this area.
Can be demonstrated. However, as in the past
When increasing the distance d between adjacent data with delay,
If one frame consists of 128 blocks, C_TwoSign
128/36 or less when generated from 36 samples
Is 3 and the distance d between adjacent data is 3.
It becomes a block. However, if d is kept constant at 3, then 3
6 × 3 = 108 blocks, maximum 128 blocks
It's not that it's distributed efficiently, it's that
Correction capability for burst error
Would. [0009] SUMMARY OF THE INVENTION The object of the present invention is to
Solves problems and improves burst error correction capability
To provide a digital signal recording and transmitting method for
You. [0010] SUMMARY OF THE INVENTION The above-mentioned objects are
First error detection and correction by adding the first redundant code to the data group
A plus sign is formed and a predetermined number of the digital data or
Adds a second redundancy to the first redundancy code to add a second error detection
Output correction code, and a predetermined number of the digital data
Alternatively, a block is formed by the first redundant code and the second redundant code.
Structure, and one frame is composed of a plurality of blocks
In a digital signal recording and transmitting method for recording, a block
Address that identifies at least the block order
Information is added, and the first error detection and correction code is different.
Group of digital data recorded in the block
A plurality of first redundant codes generated from the digital data group
The second error detection and correction code is composed of
Information and a predetermined number of digital data or first redundant code
And the second redundancy, the first error detection and correction code
Digital data group and a plurality of first redundancy
Arbitrary blocks of adjacent data in which codes are recorded in a distributed manner
Arrange so that the distance between them is different in at least one place
And, for example, the first distance is d₁, The second distance is d_TwoAs
Achieved by recording. [0011] As a result, the first error detecting and correcting code is adjacent to the first error detecting and correcting code.
If the delay between data
(D₁+ D_Two) / 2, and d₁And d_TwoOptimally set the value of
This reduces the amount of memory compared to the case where a constant delay is given.
The delay amount can be increased with the capacity, and the correction for burst error is possible.
Positive ability is improved. Further, a block is added to the second error detection and correction code.
By including the address information of the
Improves error detection capability and blocks due to burst errors
It is possible to prevent erroneous detection of the address. [0013] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.
You. FIG. 1A shows the error detection / correction code generation or
Is a memory map for interleaving, and (b) is
FIG. 3 is an enlarged view of a part of the block configuration of FIG.
Correspondingly shown. Time series digit entered here
Tal data is black on the memory map in the order shown by arrow A '.
Round W₁~ W₃₂The ones that are sequentially stored in the position indicated by
Then, white circle D in the figure₁~ D_ThreeData at the position indicated by 32
C from arrow B'in this order_TwoSign q₀~ Q_ThreeGenerated, figure
It is stored at the indicated position. Where C_TwoCode is generated
Data D₁~ D₃₂Location of C and the generated C_TwoSign
q₀~ Q_ThreeIs a delay block between adjacent data
Non-linear form in which the distance d is alternately d = 3 and d = 4
It has become. Also C₁Code P₀~ P_ThreeData to generate
Is black circle W in the figure₀~ W₃₂And C_TwoCode Q₀~ Q_ThreeOf 37
Is generated in the order of the arrow A'and shown in (b).
P₀~ P_ThreePosition, that is, d '= 1
It will be stored in the position where the delay is applied. Remembered like this
Order to read the recorded data to record on the magnetic sheet
In the order of arrow A '. That is, in FIG. 1 (b)
As shown in the nth block, Sync, W₀,
S, P, W₁~ W₃₂, Q₀~ Q_Three, P₀, P₁’, P_Two’, P
_Three’ This result is the input time series
Input data without interleaving
Read and record in order. Also, C_TwoRegarding the code, d =
Non-linear interleaving of 3 and d = 4 is applied, 4 symbols
C₁Code P₀~ P_ThreeFor C_TwoDelay for code generation
Set the block distance d to the minimum value d = 3 or less
A scraper with a distance d '= 1 between adjacent blocks
It is recorded in the state that it has been tumbled. It is C in 4 blocks.
₁The code is complete. When recording by such a method, after-recording
ー The above question without a recording margin
The problem can be solved. Next, the situation will be described with reference to FIG.
You. 5, the same symbols as those in FIG. 4 have the same meanings.
Represents the same content. TAC here_TwoPa
After recording is performed with the
E residual block a₁₂₅~ A₁₂₆Occurs, (a
₁₂₅, A₁₂₆Is an error block) TAC_TwoNo pulse
Is detected and C is detected in the T'region.₁Sign check
If, for example, b₁₂₆Data W in block₀~ W₃₂,
Q₀~ Q_Three, And P in FIG._Four, P_Five, P₆, P₇No
C by data₁Check that all data is correct
If so, it is judged as correct data. But TAC_Two
Provide a circuit and device to detect and correct the pulse deviation
If not, TAC_TwoC that is not misaligned₁Choi
To perform C check using the data in the T "area.₁By
Error detection. For example, a₁₂₇block
Data W in₀~ W₃₂And Q₀~ Q_ThreeAnd P₈’, P₉’,
P_Ten", P₁₁Check by "W₀~ W₃₂And Q₀~ Q
_ThreeAnd P₈’, P₉’Is the old data that has disappeared,
P_Ten", P₁₁’Due to after recording
Since it is new data written, naturally C₁check
Then, an error will be detected. Similarly, a₁₂₈Block
Ku is also judged to be incorrect. Ie E_TwoIn the area
Erroneous detection of errors by determining all error data
Error and correction is not possible
E as an error block_TwoDetect the area and move from the T area
Check using the data in the T area that has been corrected correctly
It is possible to FIG. 6 is a diagram showing another embodiment according to the present invention.
6, the same reference numerals as those in FIG. 1 have the same meanings.
Is represented. Where C_TwoSign q₀~ Q_ThreeIs a delay block
C is set to interleave with d = 8, and C_TwoGenerated
For D₁~ D₁₆Data and D₁₇~ D₃₂Also about
This is a non-linear generation order with d = 3. Next to each other
C_TwoSign q₀, Q₁, Q_Two, Q_ThreeThe distance between delay blocks is
= 8, the adjacent C of 4 symbols₁Sign
p₀, P₁, P_Two, P_ThreeThe distance between the delay blocks is d ′ = 2
Can be done. In this embodiment, C₁Sign
After recording is completed in 7 blocks.
Equivalent to a device with a circuit configuration in which the engine is 6 blocks long.
You will have fruit. FIG. 7 shows another embodiment according to the present invention.
The same reference numerals as those in FIG. 1 represent the same contents having the same meaning.
It is. The time-series digital data input here is
Black circle W on the memory map in the order shown by arrow A '₁~ W₃₂
Assuming that the data will be sequentially stored in the positions shown in
Nakaguro Maru W₁~ W₃₂Position data shown in and assumed
C_TwoCode data Q₀~ Q_ThreeFrom 37 in the order of arrow A '
More C₁Code P₀~ P_ThreeIs generated and the position shown by the black circle
Is stored. Also C_TwoThe symbol is the position shown by the white circle in the figure
Arrow B'in the order, that is D₁~ D₁₆, D₁₇~ D₃₂And
And C₁Code P₀~ P_Three37 new from C_TwoGenerate code
And white circle q in the figure₀~ Q_ThreeMemorize at the position. Where C_TwoMark
Data D to generate the number₁~ D₁₆And D₁₇~ D₃₂
The delay block distance between adjacent data is d = 3.
P₀~ P_ThreeWith d = 4 and generated q₀~ Q_Three
Data is also set to d = 4. More like this
C in stored data_TwoCode Q₀~ Q_ThreeAnd C₁Mark
No.P₀~ P_ThreeFor q,₀~ Q_ThreeAnd p
₀~ P_ThreeAs shown in FIG.
Read to record on a magnetic sheet
The order of delivery is, for example, in the nth block in FIG.
For example, Sync, S, P, W₁~ W₃₂, Q₀, Q
₁, Q_Two, Q_Three, P₀, P₁, P_Two, P_ThreeIn order. This result
As a result, interleave the input PCM data.
Output in chronological order without calling, C₁And C_TwoSign
Therefore, non-linear interleaving will be applied. Next, digital signal recording for implementing the present invention
An embodiment of the digital signal processing circuit of the reproducing apparatus is shown in FIG.
And FIG. 9 will be described. Figure 8 shows the times that make up the recording system.
1 is an A / D converter, 2 is a subcode
Input interface, 3 is the block address and
ID code generation circuit, 4 parity generation circuit, 5 memo
6 is a memory address control circuit, 7 is C_Two
Code generator, 8 is C₁Code generation circuit, 9 is timing
The clock generation circuit 10 is a modulation circuit. Anna here
Log signal from input terminal A and sub signal from input terminal B
When input from, the analog signal is output by the A / D converter 1.
Convert to digital signal and configure 1 block
Block address and ID for each data to be collected
The code is a block address, and the ID code generation circuit 3
Generated. Further generated block address and
Parity from ID code to parity code such as CRC code
It is generated by the generation circuit 4. The output of the A / D converter
The digital signal is stored in the memory 5 in chronological order.
Read the data in the memory of C_TwoCode and C₁Sign
To C_TwoCode generation circuit 7 and C₁Generated by the code generation circuit 8
And store it in the memory 5. Then C_TwoSign and
C₁Data reading order for code generation or raw
When storing the generated code in the memory 5, the address is
For example, the order is as shown in the examples of FIGS. 1, 6 and 7.
The address control circuit 6 to control the memory 5
The data is read from the
Output terminal O by adding and digitally modulating
Output from a recording medium such as a magnetic floppy disk.
Record on the body. The timing clock generation circuit 9
A circuit that generates the timing clock required for each circuit
It is. FIG. 9 is a block diagram of a circuit which constitutes a reproducing system of the apparatus.
In the lock diagram, 11 is a data strobe circuit, 12 is a synchronization
Signal detection protection circuit, 13 demodulation circuit, 14 parity check
Check circuit, 15 is a memory, and 16 is an address code of the memory.
Control circuit, 17 is C₁Code demodulation circuit, 18 is C_TwoMark
No. decoding circuit, 19 is a timing clock generation circuit, 20
Is a D / A converter. In the figure, recorded on the recording medium
The reproduced signal is input to the input terminal IN and the
"1" of each signal or
The original is determined by determining "0" and the interval.
It is shaped into a rectangular modulated recording wave system. This square wave pattern
From sync signal detection protection circuit 12 to sync signal pattern
Data strobe circuit
The output of 11 is digitally demodulated by the demodulation circuit 13.
Obtain the original digital signal. Then check the parity
The block circuit 14 and the ID code
Detects code errors and demodulates the digital data
Data is stored in the memory 15 after absorbing the jitter component.
You. Furthermore, the data stored in this memory 15 is read.
Then C₁C for code decoding₁Decoding circuit 17 makes an error
Detect and C_TwoC in the decoding circuit 18_TwoCode decoding
Memory 1 for error detection and correction
The error data stored in 5 is corrected and replaced.
Then, the D / A converter 20 converts it to the original analog signal.
Then, the data is output from the output terminal OUT. Note that the timing
Does the lock generation circuit require timing for each circuit?
Generates and supplies a clock. The interface according to the present invention shown in FIG.
Address control circuit for memory that realizes leave
An example of the operation and circuit of FIG. 10 will be described with reference to FIGS.
I will tell. FIG. 10 shows the method of FIG. 1 showing an embodiment of the present invention.
11 is a memory map corresponding to.
An address control circuit that generates a dress. Figure
Numbers in the box of 10 are addresses for storing each data
In this embodiment, once stored in the memory,
PCM data, ID, subcode, C₁, C_TwoThe floppy
-Read data from memory for recording to disk
When incrementing, increment the address from 0 to 1 bit
This is an example designed to generate more. Entered here
The PCM data to be transmitted is 1 frame (32 bytes x 128 bytes).
It is controlled so that it becomes a lock unit, and the address
The address is 3, 4, 5, ..., 3, 4, 4 in FIG.
6, 47, ..., 77, 89, ..., 120, ..., 5495
Like filling the PCM data area in sequence.
ROM6 for generating PCM data write address in FIG.
The addresses are generated at 7,68. Here, ADR. R
OM2 has 32 address data of 3, 4, 5, ..., 34
Is output, and OFFSET. ROM2 has different blocks
0,43,86,12 as the offset amount for each
Outputting data such as 9, and adding with the adder 75
Generates the address shown in the PCMdata area by
Things. In addition, the cow that specifies the ROM address
The counters 64 and 62 are divided by 32 and divided by 128 counters.
Count that counts the number of data and the block number respectively
It is. One frame of data in the PCMdata area
After all are stored, the ID is generated and the address 0,
1, 2, 43, 44, 45, 86, ..., 5461, 54
62 and 5463 are sequentially stored. This operation is shown in FIG.
The frequency division counter 63 is used to write ID and parity.
0, 1, 2, 43, 4, 4 from the dress generation ROM 68
Read out 5, ..., Block number counter CNT₁₂₈By
ID, parity write address offset
0,43,86,129, ... was read from the ROM 67
It is realized by adding and adding. Next, C_TwoIn order to generate the code, the arrow B'in FIG. 1 is used.
In the order shown, ie, addresses 3,134,30 in FIG.
32 memory addresses in the order of 7, ... C_TwoGeneration day
Data read address and C_TwoData write address
Generation ROM 72 and C_TwoGeneration data read ad
Res and C_TwoOffset for data write address generation
Each address is generated by the ROM 71 and the data is read.
But four C_TwoCode Q₀, Q₁, Q_TwoAfter generating
The predetermined addresses shown in FIG.
Generate and store. Finally, the block stored in the above procedure
Address, PCM data, C_TwoC using sign₁Live sign
To achieve. That is, the 41 frequency division counter 66 and the number of blocks
Counter 62₁Generation data read address
And C₁ROM 73, 7 for generating data write address
4 is driven and both ROMs are added by the adder 75.
Generate a predetermined address 0, 3, 4, 5, ..., 37, 38
Read each data and make 4 C₁Code P₀, P₁,
P_Two, P_ThreeTo generate ROMs 73, 74 and addition
Addresses 39, 40, 41, 42 are generated by the device 62
And store it in this position. With the above, 1 frame including redundant code
All of the site data has been filled, and at this time 5
0, 1, 2, ..., 550 by the 504 frequency division counter 61
Whether the count value up to 4 is used as an address as it is in the memory
If you read the data from it and record it on a floppy disk
The interleaving of the present invention shown in FIG. 1 can be realized. In FIG. 11, MPX is a server for performing each of the above operations.
Sele so that the address specified by imming is output
It is a multiplexer with 5 inputs and 1 output that is switched by the ct signal.
Yes, to perform this Select signal and each operation
Required clock SCK₀~ SCK_FourIs the taimi shown in FIG.
It is generated by the synchronization clock generation circuit 9. Ma
The address generation circuit realized in FIG. 11 has a large capacity, for example.
It can also be realized by one ROM. Figure 12 shows the circuit
In the figure, 77 is a counter, 79 is a large capacity ROM or PLA
A circuit having a decoder function such as 5 is a memory. This
Here, the ROM 79 operates in the same manner as described with reference to FIGS.
It is designed to output address data sequentially,
First, the adder 77 is used to store the PCM data.
Less (13 bits × 32 words × 128 Block =
53.248 kbit), then address for ID storage
(13 bits × 3 words × 128 B1ock = 4.
992 kbit), C_TwoEach reading for generation and
Generated C_TwoAddress for storing the code (13 bits x
(32 + 4) word × 128Block = 66.56
kbit), C₁Each data reading for generation and
Generated C₁Address for storing the code (13 bits x
(37 + 4) words × 128 Brook = 68.22
4kbit) is output, so 24.128k bytes or more
The capacity may be less than or equal to Predetermined by this ROM 79
Generate the address of PCM data, ID, C_Two, C₁Mark
1 frame data including redundant code
Data to be stored on the disk after storing all
The address for reading data is output by the counter 78
By switching with the multiplexer 80, the interface of the present invention is
Address control circuit for memory that realizes leave
It constitutes. [0024] According to the present invention, at least two kinds or more
Different distances d₁~ Dn (delay amount), C_TwoSign
The difference between the adjacent data
The total amount of delay to complete the code is given by combining the delay amounts.
Closest to a fixed memory capacity (or number of blocks)
Therefore, you can set a fixed delay amount in a fixed memory area.
Efficient dispersion can be achieved compared to when given, and adjacent data
It is possible to increase the delay between data
The correction ability is improved. Further, even if the effect of claim 2 is
If C_TwoThe code is completed in frames, and one frame is 128 blocks.
Composed of lock, C_TwoThe code is generated from 36 samples
The first distance d₁As 3 blocks,
Second distance d different from this_TwoAdjoin as 4 blocks
Since the data is recorded by alternately giving it to each other,
Delay between adjacent data converted when a delay amount is given
Becomes (3 + 4) /2=3.5 blocks, and a constant delay d
= Burst error for 3 blocks
The correction ability by 0.5 block is improved. Also C_TwoSign
The total amount of delay to complete is 3.5 × 36 = 126 blocks
Equivalent to existing 128 blocks for data storage
The memory capacity of can be utilized to the maximum extent and the consistency is good. Further, C₁Block address information in the code
Information is included, the block address is detected incorrectly.
Even if it is₁Error detection by code
Can be issued to prevent false detection of block addresses
it can.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a memory map diagram of each data showing an embodiment of a recording method according to the present invention. FIG. 2 is a magnetic sheet format diagram showing a data recording method of an electronic camera. FIG. 3 is a memory map diagram showing interleaving of respective data, which is a conventional recording method. FIG. 4 is a conceptual diagram showing problems that occur in a conventional recording method. FIG. 5 is a conceptual diagram showing the effect of the present invention. FIG. 6 is a data memory map diagram showing another embodiment of the recording method according to the present invention. FIG. 7 is a memory memory map diagram showing another embodiment of the recording method according to the present invention. FIG. 8 is a block diagram of a recording system circuit of a recording / reproducing apparatus that realizes a recording method according to the present invention. FIG. 9 is a block diagram of a reproducing system circuit of a recording / reproducing apparatus that realizes a recording method according to the present invention. FIG. 10 is a data memory map diagram showing another embodiment of the recording method according to the present invention. FIG. 11 is a block diagram showing an embodiment of an address control circuit of a memory that realizes a recording method according to the present invention. FIG. 12 is a block diagram showing another embodiment of the address control circuit of the memory for realizing the recording method according to the present invention. [Description of Codes] W _{0 to} W ₃₂ ... C ₁ code generation PCM data, P _{0 to} P ₃ ... C ₁ redundant code, A '... C ₁ code generation order, D _{1 to} D ₃₂ ... C ₂ code generation PCM data, q ₀ to q ₃ ... C ₂ redundancy code, B '... C ₂ code generation sequence, d ... interblock delay distance by interleaving, 1 ... a / D converter, 2 ... input interface circuit of the subcode, 3 ... block address and ID code generating circuit, 4 ... parity generating circuit, 5 ... memory, the address control circuit 6 ... memory, 7 ... C ₂ code generation circuit, 8 ... C ₁ code generation circuit, 9 ... timing clock generation circuit, 10 ... Modulation circuit, 11 ... Data strobe circuit, 12 ... Synchronous signal detection protection circuit, 13 ... Demodulation circuit, 14 ... Parity check circuit, 15 ... Memory, 16 ... Memory address control times 17 ... C ₁ code decoding circuit, 18 ... C ₂ code decoding circuit, 19 ... Timing clock generation circuit, 20 ... D / A converter.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G11B 20/18 576 G11B 20/18 576F 20/12 102 9295-5D 20/12 102

Claims (1)

(57) [Claims] A first redundant code is added to the digital data group to form a first error detection / correction code, and a second error is added by adding a second redundancy to a predetermined number of the digital data or the first redundant code. A detection / correction code is formed, a block is formed by the predetermined number of the digital data or the first redundant code and the second redundant code, and one block is formed by a plurality of blocks and is recorded. In the digital signal recording and transmitting method, at least address information for identifying the order of blocks is added to the blocks, and the first error detection and correction code has a digital data group recorded in different blocks and the digital data. The second error detection and correction code is composed of a plurality of first redundant codes generated from a group, and the second error detection and correction code includes the address information and a predetermined number of the data. Adjacent data in which the digital data group and a plurality of first redundant codes which are composed of digital data or a first redundant code and a second redundant code and which constitute the first error detection and correction code are dispersedly recorded. The method for recording and transmitting digital signals, characterized in that the distances between the arbitrary blocks are recorded at different locations at least at one or more locations. 2. The first distance in which the digital data group forming the first error detection code and the plurality of first redundant codes are dispersedly recorded is 3 blocks, and the second distance is 4 blocks. 2. The digital signal recording and transmitting method according to claim 1, wherein the recording is performed by alternately arranging at a second distance.