JP2685283B2 - Communication method, parallel variable-length coding circuit, and parallel variable-length decoding circuit - Google Patents

Description

DETAILED DESCRIPTION [Table of Contents] Outline Industrial field of application Conventional technology Buffer memory load balancing parallel variable length coding circuit (Fig. 8) Buffer memory load balancing parallel variable length decoding circuit (9th embodiment) Fig.) Problems to be Solved by the Invention Means for Solving the Problem Action Embodiment Buffer memory load distribution type parallel variable length coding circuit (Fig. 2) Buffer memory load distribution type parallel variable length decoding circuit (Fig. 7) [Advantages of the Invention] [Outline] A communication method for transmitting signals having different occurrence probability distributions, and an improvement of the encoding circuit and the decoding circuit thereof, to make the occupying speed of the buffer memory uniform, to shorten the absolute delay time, etc. In order to achieve the above, on the transmission side, a plurality of data strings input with different occurrence probability distributions follow the respective occurrence probability distributions and the predetermined data The variable length encoder is switched for each data sequence every predetermined period period and is input to the variable length encoder. The data string input to the variable-length coding circuit is subjected to variable-length coding corresponding to the occurrence probability distribution of the data string in parallel in each variable-length encoder and transmitted, and on the receiving side. , According to the occurrence probability distribution corresponding to a plurality of data strings that have been variable-length coded and transmitted,
Further, it is switched to the variable length decoder for each predetermined data string and is input to the variable length decoder by switching every predetermined period period. The data string input to the variable length decoder is configured such that variable length decoding corresponding to the occurrence probability distribution of the data string is performed in parallel in each variable length decoder.

[Industrial applications]

The present invention relates to a communication method of signals having different occurrence probability distributions, a parallel variable length coding circuit, and a parallel variable length decoding circuit.

In recent years, the conventional telephony telephone switching network has been shifting to ISDN (Digital Integrated Services Network). In this ISDN, various media (telephone, images, etc.) can be transmitted. As one of them, image transmission includes various kinds of moving images such as TV relay of broadcast quality image signals, video conferences, and video telephones. Compared to other transmission media, the amount of information that these moving images must be transmitted per unit time is remarkably large, that is, high-speed transmission is required. Becomes A high-efficiency coding device is being developed as one technical means for satisfying this demand. In this type of device, high coding efficiency is pursued, and variable length coding is often used for that purpose. However, since the signal processed by the device is a very high speed signal as described above, very high speed processing is required for the signal processing in variable length coding and decoding.

[Conventional technology]

In the conventional variable length coding / decoding circuit, low-speed circuit elements are used in parallel to satisfy the high-speed signal processing required for the variable length coding / decoding circuit. An example of the circuit is shown in FIG. A variable length coding circuit C _i is provided corresponding to an input data string of a predetermined data length digitized for each image signal occurrence probability distribution P _i (i = 1, ..., N). The occurrence probability distribution P _i means that the difference information generated in the screen portion (background) where there is no difference between the frames on the time series of the frames is concentrated at almost 0, or even if the difference information occurs, the degree of discreteness is In the image portion that occurs only at a high price and has a movement between frames, a relatively large amount of small difference information corresponding to the movement is generated. Probability of occurrence of such various difference information is distributed in a time series, and the probability distribution of the difference information when the probability of the generated difference information is almost constant. .

The configuration of these variable length coding circuits C _i is composed of a variable length coding unit VWLC _i and a multiplexing circuit MPX _i . The variable length coding unit VWLC _i converts the input data string to the variable length coding unit VWLC _i into code length information (VWL
_i ) and a table for converting to code information (VWLD _i ),
The input data string is converted into code length information and code information. The multiplexing circuit MPX _i which receives both of these information (VWL _i and VWLD _i ) is responsive to the converted variable length information sequence, for example, a fixed information unit of 8 bits or 16 bits (write data unit). and outputs the write clock WCK _i synchronized with the asynchronous data WD _i and the asynchronous data WD _i. The asynchronous data WD _i is written in the buffer memory BM _i in response to the write clock WCK _i . It is read by the read clock RCK _i provided from the transmission device of the network for transmitting the data in the buffer memory BM _i . Thus, the input data string for each phase is variable length coded and transmitted.

Further, the conventional buffer memory load distribution type parallel variable length decoding circuit has a configuration as shown in FIG. 9, and the transmitted asynchronous data BMD _i is accumulated in the buffer memory BM-R _i while the read clock Read with RCK-R _i . The read asynchronous data BD-R _i is separated into code information (see FIG. 4) in the separation circuit DMPX _i that responds to the code length information VWL-R _i and is input to the variable length decoding unit VWLC-R _i . It In the variable length decoding unit VWLC-R _i , the decoding table provided therein is indexed by the code length information and the code information used for the separation of the code information, and the decoded data string (that is, the input in the encoding is input. The input data string) D _i that has been input is output for each input code information and code length information.

[Problems to be solved by the invention]

The above-mentioned conventional variable-length coding circuit plays a part in the economical transmission request of the image signal, but still has the following technical problems to be solved.

When each of the data strings having the above occurrence probability density distribution is input to the corresponding variable length coding circuit, the occurrence frequency of the data output from the variable length coding circuit is biased.
This means that the occupying speed of the buffer memory for inputting the data of which the occurrence frequency is high becomes high, and an overflow easily occurs in the buffer memory.

If the buffer memory capacity is increased in order to prevent this overflow, an increase in absolute delay time inevitably occurs, and the real-time property of transmission is lost. or,
The hardware for that is inevitably costly.

Also, in the conventional buffer memory load distribution type parallel variable length decoding circuit, since the input frequency of the asynchronous data input to the buffer memory BM-R _i is biased, the same problem as in the case of encoding occurs. .

The present invention was created in view of the above technical problems, and a communication method of signals having different occurrence probability distributions, which can achieve equalization of occupied speeds of buffer memories, reduction of absolute delay time, and the like, Another object of the present invention is to provide a parallel variable length coding circuit and a parallel variable length decoding circuit.

[Means for solving the problem]

According to the invention described in claim 1, a plurality of data strings having different occurrence probability distributions are input, the input plurality of data strings are subjected to a corresponding occurrence probability distribution, and a variable length encoder is provided for each predetermined data string. The variable-length encoder is switched every time a predetermined period elapses and is input to the variable-length encoder, and the input data string is subjected to parallel variable-length encoding corresponding to the occurrence probability distribution of the data string in each variable-length encoder. To the variable length decoder according to the occurrence probability distribution corresponding to the coded data sequence and receiving the plurality of data sequences that have been variable length encoded and transmitted. The variable-length decoder is switched at every elapse of the predetermined cycle period and input to the variable-length decoder, and the input data string is subjected to parallel variable-length decoding corresponding to the occurrence probability distribution of the data string in each variable-length decoder. Structure It is.

The invention according to claim 2 is, as shown in FIG. 1 (1), n different occurrence probability distributions P _i (i = 1, 2, ..., N)
Each of the occurrence probability distributions of the signals having the following, each of the parallel input data strings having a predetermined data length is Data input means 1 for sequentially outputting different one data outputs respectively, and a data string connected to the data output for each of the n data outputs and identifying a data string output to the data output as an input data string of the data string. A variable-length coding circuit 2 _i for performing variable-length coding corresponding to the signal MODE _i to output asynchronous data and a write clock synchronized with the asynchronous data, and connected to the output for each variable-length coding circuit, in response to said write clock provided a buffer memory 4 _i writing the asynchronous data, the buffer memory 4 _i read in is performed by a read clock applied thereto Configured by way.

The invention according to claim 3 is, as shown in FIG. 1 (2), each occurrence probability distribution for a signal having n occurrence probability distributions P _i (i = 1, 2, ..., N). For each of the parallel input data strings of a predetermined data length, one variable length code among the n variable length coding circuits sequentially different for each predetermined period period and for each input data string. Input in parallel to each encoding circuit, and in each input variable length encoding circuit, data input of parallel asynchronous data transmitted by performing variable length encoding in the occurrence probability distribution corresponding to the input data string, a buffer memory 5 _i writing each received asynchronous data from said input in response to the write clock is connected to the output of the buffer memory 5 _i, the received asynchronous data corresponding to the received asynchronous data read out from the buffer memory 5 _i Column identification information MODE-R _i In response, a plurality of variable length decoding circuits 3 _i for sequentially generating the decoded data sequence in which the corresponding reception asynchronous data is subjected to the variable length decoding and the order of the input data sequence at the time of encoding is reversed. A corresponding input is connected to each output of the plurality of variable-length decoding circuits 3 _i , and the same occurrence probability distribution is generated for the same occurrence probability distribution of the decoded data strings output to the respective outputs. And a data output means 8 for sequentially outputting to the output.

(Operation)

According to the first aspect of the present invention, a plurality of data strings having different occurrence probability distributions are input, and the input plurality of data strings respectively have corresponding occurrence probability distributions,
Further, the variable length encoder is switched for each predetermined data string every time a predetermined cycle period elapses and is input to the variable length encoder. The data string input to the variable length coding circuit is subjected to variable length coding corresponding to the occurrence probability distribution of the data string in parallel in each variable length encoder and transmitted.

On the receiving side that receives the plurality of data strings that have been variable-length coded and transmitted, the coded data strings are sent to the variable-length decoder for each predetermined data string according to the corresponding occurrence probability distribution. It is switched every time a predetermined period elapses and is input to the variable length decoder. The data string input to the variable length decoder is, in each variable length decoder,
Variable length decoding corresponding to the occurrence probability distribution of the data string is performed in parallel.

In variable-length coding and variable-length decoding, the variable-length coding, the variable-length encoder used for variable-length decoding, and the data string input to the variable-length decoder are the same. According to the occurrence probability distribution, and because the data is input to the variable-length encoder and variable-length decoder for each predetermined data string, the occurrence frequency of the data output from the variable-length encoder and variable-length decoder is biased. It becomes possible to output without.

According to the invention described in claim 2, parallel occurrence of predetermined data for each occurrence probability distribution for signals having different n occurrence probability distributions P _i (i = 1, 2, ..., N) Each of the long input data strings is output by the data input means 1 to one sequentially different data output of n parallel data outputs for each elapse of a predetermined cycle period and for each input data string. .

The data string connected to the data output for each of the n data outputs is input to the variable length coding circuit 2 _i, and variable length coding corresponding to the input data string identification signal MODE _{i of the} data string is performed. The variable length coding circuit 2 _i outputs the asynchronous data and the write clock synchronized with the asynchronous data by the variable length coding circuit 2 _i .

The asynchronous data output for each variable length coding circuit is
Data is written from the buffer memory 4 _i in response to the write clock and read by the read clock supplied to the buffer memory 4 _i .

The data strings input to the variable-length encoder are input to the variable-length encoder for each predetermined data string according to the corresponding occurrence probability distributions, so that the data output from the variable-length encoder is generated. The bias in the frequency is eliminated, and as a result, the occupying speed of the buffer memory 4 _i is equalized. This is useful for shortening the absolute delay time and the like.

According to the invention described in claim 3, n occurrence probability distributions P _i
For each occurrence probability distribution for a signal having (i = 1, 2, ..., N), each of the parallel input data strings having a predetermined data length is The occurrence probability distribution corresponding to the input data string is input in parallel to one variable length coding circuit which is different in sequence from the n variable length coding circuits for each column and is input in each variable length coding circuit. For each data input of parallel asynchronous data sent with variable length coding in
It is written in the buffer memory 5 _i in response to the write clock.

The received asynchronous data read from the buffer memory 5 _i is encoded by being subjected to variable length decoding in the variable length decoding circuit 3 _i in response to the received asynchronous data string identification information MODE-R _i corresponding to the received asynchronous data. Decoded data sequences that are in the reverse order of the input data sequence at that time are sequentially generated.

Of the decoded data strings output from each variable length decoding circuit 3 _{i, the} decoded data strings with the same occurrence probability distribution are sequentially output by the data output means 8 to the same occurrence probability distribution output.

Also in this variable length decoding, since the asynchronous data to the buffer memory 5 _i is equalized, the same operation effect as the variable length coding can be obtained.

〔Example〕

2 and 7 show an embodiment of the invention described in claims 1 to 3. FIG. 2 shows claims 1 and 2.
An embodiment of the described invention is shown. In this figure, 6 is a connection switching circuit, which has n different occurrence probability distributions P _i (i
= 1,2, ..., n), an input data string D _i of a predetermined data length for each occurrence probability distribution of an image signal (event) is generated by n switching instruction signals [n constant cycles (n For example, every 1 frame (1 line period)] is input to a predetermined variable length coding circuit 2 _p (p is one of i). The variable length coding circuit 2 _i has a variable length coding unit 22 _i and a multiplexing circuit 24 _i . The variable-length coding unit 22 _i uses n tables (hereinafter, 2 tables).
6 Refer to as _i . ), And the input data string SD _p from the connection switching circuit 6 (p represents each of the input data strings in the predetermined order as described above. The number is n or m other than n). The table 26 _i is selected by the table switching control signal MODE _i that is input synchronously, and the table 26 _i is indexed by the input data string D _i to obtain the code length information VWL _i and the code information VW.
Output LD _i . The variable length coding unit 22 _i is configured to have a ROM, a RAM, or a PLD (Programmable Logic Device). The multiplexing circuit 24 _i includes code length information VWL _i and code information VWL _i.
D _i receives, fixed data unit, for example, and outputs the asynchronous data WD _i and write clock WCK _i synchronized with the asynchronous data WD _i fixed length word (8 bits or 16 bits). Both outputs of the multiplexing circuit 24 _i are input to the buffer memory 4 _i .

Variable length coding under the above circuit configuration will be described.

Each input of the connection switching circuit 6, that is, each occurrence probability distribution of a signal
The input data string corresponding to P _i is input to the corresponding input terminal in the same manner as it is input to the variable-length coding circuit C _i (see FIG. 8) in the conventional system, while the switching control signal SHIFT thereof is It is given in a cyclical manner (cyclically) as shown in (1) of. The switching system in the connection switching circuit 6 based on this switching control signal is as shown in (I ₁ , I ₂ , ...
I _n ) and (O ₁ , O ₂ , ..., O _n ), the input data string D _i in the switching control signal l (one of l = 1, 2, ..., N) is If it is output from the connection switching circuit 6 as SD _j (one of j = 1, 2, ..., N ₎ , it will be output as SD _{(j + 1) in} the next switching control signal l + 1. To
As the switching control signal 1 progresses to the switching control signal n, each of the input data strings D _i is sequentially arranged in the variable length coding unit 22 _k (k = 1, 2, ..., N) corresponding to the switching control signal l. 1), that is, distributed distribution. Therefore, if, for example, the input data string D1 ¹ is output as SD ₁ (= D1 ¹ ) in the switching control signal l, the input data string Dn ⁿ in the switching control signal n is output as SDn (= D1 ⁿ ).

The variable-length coding unit 22 _i to which the respective input data strings (input data string sequences) distributed in this way are input is supplied to the table switching control signal string MODE _i corresponding to each of the input data strings. Is entered. Thus, in the variable length coding circuit 2 _i , the variable length coding process is performed under the above-mentioned conventional method for each of the input data strings of the occurrence probability distribution sequentially generated by the above switching method. For example, as an input data string to the variable length coding circuit 2 _i ,
Of the input data levels divided into 63 levels as shown in FIG. 4, 0 level, -3 level, 3 level, 0 level,
Assuming that an input data level of −59 levels is input to the input data sequence, the variable length coding unit 22 _i outputs the data from the variable length coding unit 22 _{i in} FIG.
The code length information and the code information as shown in are output. Then, the output as shown in FIG.
_When input to _i , the multiplexer 24 _i generates an output as shown in FIG. 5B, that is, asynchronous data of a fixed length word and a write clock synchronized with this asynchronous data. The remaining part of the code information for the code length information 12 that was not multiplexed as asynchronous data ((B) in FIG. 5) is multiplexed into the next asynchronous data. These outputs (asynchronous data and write clock) are input to the buffer memory 4 _i , and asynchronous data are written therein. Such writing in the buffer memory 4 _i is generated each time there is an output from the multiplexing circuit 24 _i . And
The reading from the buffer memory 4 _i is performed by the read clock RCK _i provided from the transmission device of the network as in the conventional case. BMD _i shows the output.

As described above, since the input data string given to each variable length coding circuit is the input data string of all the occurrence probability distributions, the generation frequency of the output data of the variable length coding circuit as in the conventional method is not biased. , Will be even. Therefore, the occupying speeds of the buffer memories 4 _i are also equalized, and overflow does not occur there (see FIG. 6). As a result, the absolute delay time is shortened, the circuit scale of the buffer memory is also reduced, and the cost is reduced.

FIG. 7 shows an embodiment of the invention described in claims 1 and 3. In this figure, 5 _i (i is the same as in FIG. 2)
Is the asynchronous data sent from the sender as described above
It is a buffer memory BM-R _i for each BMD _i . Each of the buffer memories BM-R _i is given a write clock WCK-R _i for writing the asynchronous data BMD _i from the network. 3 _i
Is a variable length decoding circuit, which comprises a separation circuit 34 _i and a variable length decoding unit 32 _i . The separation circuit 34 _i performs the separation processing of the asynchronous data RD-R _i read from the buffer memory 5 _i in response to the read clock RCK-R _i input from the separation circuit 34 _i, by the variable length decoding unit 32 _i. Code length information given by VWL
Outputs the code information DMPXD _i performed according -R _i. The variable length decoding unit 32 _i decodes n pieces of switching control signals MODE-R _i , which are obtained by reversing the order of the n pieces of switching control signals used in the above-mentioned variable length encoding. Have a table. The index of each decoding table is performed by the separated code information and the corresponding code length information input thereto, and the encoded data string (corresponding to the input data string before encoding,
It outputs one of n occurrence probability distributions). Reference numeral 7 is a connection switching circuit, and a switching instruction signal SHIFT-R which causes switching in the reverse order of the switching of the connection switching circuit in the above-mentioned variable length decoding is given to the switching control input. Further, the output of the variable length decoding circuit is connected to the n switching inputs one by one, and the decoded data string for each occurrence probability distribution is output to each of the n switching outputs. The operation of the buffer memory load balancing type parallel variable length decoding circuit will be described below.

The asynchronous data BMD _i received from the network is the write clock WCK-R which is also provided from the network.
_It is written to the buffer memory 5 _{i by i} . The asynchronous data BMD _i is read by the read clock RCK-R _i , and the code information DMPXD _i is output according to the code length information VWL-R _i input in the separation circuit 34 _i .

Then, the separated code information DMPXD _i is inputted to the variable length decoding unit 32 _i, the variable length decoding unit 32 _i, with used for the separation of said code information DMPXD _i code length information VWL-R _i In the encoding, one decoded data sequence that is in the reverse order of the input data sequence order input to the variable length encoding circuit is output for each input of the code information DMPXD _i .

In this manner, the decoded data string sequence (including all n occurrence probability distributions) sequentially output from each variable length decoding circuit 3 _i is given to the corresponding input of the connection switching circuit 7. Since the switching instruction signal SHIFT-R as described above is supplied to the switching control input of the connection switching circuit 7, the decoded data string for each occurrence probability distribution is sequentially output to each of the switching outputs. .

As is clear from the above, the buffer memory 5 _i
Asynchronous data input to is also equalized, which is useful for shortening the absolute delay time as in the case of encoding, improves the real-time property of reception, and lowers the cost of reception.

The switching control in the connection switching circuit 6 of the above-described embodiment may be different from that described above as long as the order of the switching order is maintained for each repetition. Further, the input to the variable-length coding circuit may be generated in the order of the switching order of the input data sequence so that the variable-length coding circuit does not perform the coding process for the entire occurrence probability distribution. . Of course, in this case, the n tables as described above may not be provided in the variable length coding circuit.

〔The invention's effect〕

As described above, according to the present invention, the generation frequency of the output data output from the variable length coding circuit is equalized and the occupying speed of the buffer memory is also equalized, so that the absolute delay time can be shortened. Thus, the circuit scale of the buffer memory can be reduced and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the invention described in claims 2 and 3, FIG. 2 is a diagram showing an embodiment of the invention described in claims 1 and 2, and FIG. 3 is a switching control signal and connection. FIG. 4 is a diagram showing an operation of the switching circuit, FIG. 4 is a diagram showing an example of variable length code conversion, FIG. 5 is a diagram showing an example of multiplexing operation, FIG. 6 is a diagram showing an example of occupying a buffer memory, and FIG. FIG. 8 is a diagram showing an embodiment of the invention described in claims 1 and 3, FIG. 8 is a diagram showing a conventional buffer memory load balancing type parallel variable length coding circuit, and FIG. 9 is a conventional buffer memory load balancing type. It is a figure which shows a parallel variable length decoding circuit. In FIGS. 1 and 2, 1 is a data input means (connection switching circuit 6), 2 _i is a variable length coding circuit, 3 _i is a variable length decoding circuit, 4 _i and 5 _i are buffer memories, and 8 is It is a data output means (connection switching circuit 7).

Claims (3)

(57) [Claims] 1. A plurality of data strings having different occurrence probability distributions are input, and the plurality of input data strings are subjected to a corresponding occurrence probability distribution, and a variable length coder is provided for each predetermined data string in a predetermined cycle period. It switches every time it is input to the variable length encoder,
The input data string is subjected to variable length coding in parallel in each variable length encoder corresponding to the occurrence probability distribution of the data string and transmitted, and the plurality of transmitted variable length encoded data A sequence is received, and the encoded data sequence is input to the variable length decoder according to the corresponding occurrence probability distribution, and is switched to the variable length decoder for each predetermined data sequence at each elapse of the predetermined cycle period. A communication method, wherein variable length decoding corresponding to the occurrence probability distribution of the data string is performed in parallel on the input data string in each variable length decoder. 2. An occurrence probability distribution for signals having n different occurrence probability distributions, wherein each of the parallel input data strings having a predetermined data length is input at a predetermined cycle period and at each input data string. Data input means for respectively outputting one data output that is sequentially different from the n data outputs that are parallel to each other, and connected to the data output for each of the n data outputs,
A variable-length coding circuit that performs variable-length coding corresponding to an input data string identification signal of the data string on the data string output to the data output and outputs asynchronous data and a write clock synchronized with the asynchronous data, A buffer memory connected to the output of each of the variable length coding circuits and writing the asynchronous data in response to the write clock is provided, and the reading of the buffer memory is performed by a read clock supplied thereto. Characteristic parallel variable length coding circuit. 3. Each occurrence probability distribution for a signal having n occurrence probability distributions, wherein each of the parallel input data strings having a predetermined data length is provided every predetermined period period and each input data string. Of the n variable-length coding circuits are sequentially input in parallel to different variable-length coding circuits, and the variable in the occurrence probability distribution corresponding to the input data string is changed in each input variable-length coding circuit. A buffer memory for writing each received asynchronous data from the input in response to a write clock for each data input of the parallel asynchronous data transmitted by long encoding, and connected to the output of the buffer memory, In response to the received asynchronous data string identification information corresponding to the received asynchronous data read from the buffer memory, the corresponding received asynchronous data is subjected to variable length decoding and input data at the time of encoding. A plurality of variable-length decoding circuits that sequentially generate a decoded data sequence that is in the reverse order of the columns and a corresponding input to each output of the plurality of variable-length decoding circuits are connected and output to each of the outputs. A parallel variable length decoding circuit, comprising: a data output means for sequentially outputting the decoded data strings of the same occurrence probability distribution of the decoded data strings that are received to the same occurrence probability distribution output.