JP2684793B2 - Information processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an information processing device for processing data. More specifically, the present invention relates to the configuration of an information processing apparatus suitable for processing audio data and video data (hereinafter referred to as AV data).

2. Description of the Related Art In recent years, as computers have become more multimedia, computers have been required to have a configuration suitable for AV data processing.

A compact disc interactive system (hereinafter referred to as a CD-I system) as an example of the above-described conventional information processing apparatus will be described below with reference to the drawings. The configuration of the CD-I system is basically the same as that of a conventional computer, and is one of the purposes for processing AV data.

FIG. 5 is a block diagram showing the basic part of the CD-I system published in the document (COMPUTER DESIGN Jan, 1988). For the explanation of the figure, refer to the above-mentioned literature article.

FIG. 6 is a block diagram showing a portion related to the present invention extracted from FIG.

In FIG. 6, 601 to 604 are arithmetic means, and in this example, 601 is a CPU, 602 is an ADPCM decoder (AP), 603 is a DMA controller (DMAC), and 604 is a memory composed of DRAM or the like. Reference numerals 605 to 608 are bus arbitration means for controlling the right of use of the system bus corresponding to the arithmetic means 601 to 604 respectively, and 609 is a bus for exchanging information with each other in order for the bus arbitration means 605 to 608 to advance the bus arbitration. The arbitration control line 610 is a system bus. In this figure, the address bus is omitted and only the 8-bit wide data bus is shown. In an actual CD-I system, the width of the data bus is 16 bits. Also, the memory is an image memory access controller (50 in FIG. 5).
It is connected to the system bus via 9), and the bus arbitration means is included in this. A data buffer 611 is used by the AP 602 for buffering data.

The operation of the information processing apparatus configured as above will be described below.

First, the system control program executed by the CPU 601 is stored in the memory 604. The CPU 601 specifies the address of the memory 604, reads the instruction and executes it repeatedly to advance the program. In the process, if there is a process of decoding the data on the memory 604 and outputting it as voice, the CPU 601 writes the address of the data to be output to the corresponding register of the AP 602, and then instructs the AP 602 to start the process. AP602 is the system bus to the second bus arbitration means 606.
Request 610 usage rights. The second bus arbitration unit 606 performs adjustment according to the procedure determined by the other bus arbitration units 605 and 607, obtains the right to use the system bus 610, and notifies the AP 602 that the right to use is obtained. After transferring the data to be decoded from the memory 604 to the buffer 611, the AP 602 gives an instruction to the second bus arbitration means 606 to let go of the right to use the system bus 610, and ends the series of operations. Memory 604
If you need to transfer data within the same procedure,
The DMAC 603 obtains the right to use the system bus, and the memory 604
Read and write the data in.

However, in the above-mentioned configuration, since the usage rights of all system buses are switched at the same time, audio data and video data are simultaneously transferred like an AV system.
There were the following problems, such as when transferring in synchronization.

(1) A data buffer is required in order to transfer audio data and video data separately and play them back simultaneously.

(2) Alternatively, in order to realize the simultaneous transfer, it is necessary to separately provide a bus dedicated to each data.

The present invention has been made in view of the above problems, and an object thereof is to provide an information processing apparatus suitable for processing AV data without requiring a data buffer and providing a bus dedicated to each data.

Means for Solving the Problems In order to achieve the above object, the information processing apparatus of the present invention is
A plurality of arithmetic means, a system bus composed of a plurality of information transmission lines, and a bus width arbitration means for allocating to each arithmetic means the number of information transmission lines commensurate with the data transfer rate required by each arithmetic means. , And a plurality of data width converting means for converting the input / output data of each of the arithmetic means into an assigned data width.

According to the present invention, according to the above configuration, the bus width arbitration means controls the right to use the system bus for each information transmission line, not for each time unit, that is, not for time division, according to the request of the arithmetic means, and the required number The information transmission line of is assigned to each computing means. Further, the data width conversion means has a data width (eg, 16-bit width) assigned to the input / output data (eg, 16-bit width) which is input / output with a data width specific to the arithmetic means.
9 bits). Then, within the allowable range of the bus width, the data transfers required by the plurality of arithmetic means are simultaneously executed.

Embodiment Hereinafter, an information processing apparatus according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an information processing apparatus in one embodiment of the present invention. 1 to 4 are calculation means, where 1 is a CPU, 2 is an ADPCM decoder (AP), 3
Is a DMA controller (DMAC), and 4 is a memory. 5-
8 is a data width conversion means assigned to each of the computing means 1 to 4, 9 to 12 are bus width arbitration means for each of the computing means 1 to 4, and 13 is each bus width arbitration means 9 to 12 for advancing bus width arbitration. Bus width arbitration control line, 14 for exchanging information with each other in order to
Is a system bus. Here, the address bus is omitted and only a data bus having an 8-bit width is shown. 15-18
Is a data width control line for notifying the data width converting means 5-8 of the bus width acquired by the bus width arbitrating means 9-12.

FIG. 2 is a block diagram showing an example in which each data width converting means 5-8 and each bus width arbitrating means 9-12 in FIG. 1 are constructed by using a microprocessor. 201 is a microprocessor, 202 is a program ROM, 203 is a first I / O latch circuit, 204 is a second I / O latch circuit, 205 is a memory, 206 is a bus width arbitration control line I / F, 207 is an internal It is a system bus. In FIG. 2, since the data width converting means and the bus width arbitrating means are realized by one system, the data width control lines 15 to 18 shown in FIG. 1 do not exist.

FIG. 3 is a pad diagram showing an example of a procedure for realizing the function of the data width conversion means, and FIG. 4 is a pad diagram showing an example of a procedure for each bus width arbitration means controlling system bus allocation. Yes, each function is independent, but realized by using a microprocessor as shown in Fig. 1
It can also be realized as one system. In that case,
The microprocessor advances the two procedures in parallel in a time-sharing manner.

The operation of the information processing apparatus configured as described above will be described below with reference to the drawings.

First, the system control program executed by CPU1 is
It is stored in the memory 4. The CPU 1 specifies the address of the memory 4, reads the instruction and executes it repeatedly to advance the program. In the process, if there is voice output processing, CPU1 writes the address of the data to be output as voice (hereinafter referred to as voice data) in the corresponding register of AP2, and then executes voice output to AP2. Give instructions. The AP2 obtains the required number of transmission lines from the required data transfer amount, and requests the second bus width arbitration means 10 to use, for example, four system buses 14. Second bus arbitration means 10
Uses other bus arbitration means 9, 11 and 12 and bus width arbitration control line 13 to make adjustments according to the determined procedure, and then obtains the right to use four system buses and obtains the right to use AP2. The bus width acquired by the second data width conversion means 6 using the data width control line 16 (4 in this example).
Book) AP2 reads the audio data from the memory 4, executes processing such as a decoder, and outputs it as audio. At this time, the voice data recorded in the memory 4 with an 8-bit width is converted into a 4-bit width by the fourth data width converting means 8 and placed on the system bus 14. The AP2 receives the data reconverted to the 8-bit width by the second data width converting means 6, processes it such as decoding, and outputs it as voice. After the audio output is completed, the AP 2 gives an instruction to the second bus arbitration means 10 to let go of the right to use the system bus 14 and ends the series of operations. In parallel with the above series of processing, CP
When U1 needs to transfer (copy) one part of memory 4 to another part using DMAC3, CPU1 sets start address of transfer source, start address of transfer destination, transfer amount, etc. in DMAC3. , Instruct transfer start. DAMC3 requests the right to use the system bus from the third bus width arbitration means 11. The third bus width arbitration means 11 is another bus arbitration means 9, 10, 1.
2) and bus width arbitration control line 13 are used to make adjustments according to the determined procedure, and the DMAC3 is notified that the remaining four usage rights of the system bus have been acquired and the data has been acquired. The width control line 17 is used to inform the third data width conversion means 7 of the acquired bus width (4 in this example). The DMAC 3 reads data from the memory 4 and sequentially proceeds to write to other addresses in the memory 4 until the designated transfer amount is reached. At this time, the data read from the memory 4 is once converted into a 4-bit width by the fourth data width conversion means 8 and transferred using the four system buses, and the third data width is converted into the third data width.
It is re-converted to 8-bit width by the data width conversion means of DMAC3
Is read in. When writing to another address in the memory 4, the reverse procedure is followed.

Next, each data width conversion means 5-8 and bus width arbitration means 9
An example of the internal operations (1) to (12) will be described with reference to the drawings. The entire block shown in FIG. 2 is hereinafter referred to as a subsystem for convenience of description. The microprocessor 201 controls the operation of the entire subsystem. The operation procedure of the microprocessor 201 is recorded in the program ROM 202. First I / O latch circuit 2
03 puts 8-bit width data from each arithmetic means on the internal system bus 207, and transfers data on the internal system bus 207 to each arithmetic means with 8-bit width. The second I / O latch circuit 204 puts data having a width of 8 bits or less from each bus width arbitration means on the internal system bus 207, and transfers data on the internal system bus 207 to each arithmetic means having a width of 8 bits or less. To transfer. When the data width is 8 bits or less, the remaining lines of the internal system bus have no meaning and are fixed to "L", for example. When the microprocessor 201 converts the width of data (for example, converts 8-bit width data into two 4-bit width data), the data is stored in the memory 205.
Hold temporarily. Further, the microprocessor 201 exchanges information with other subsystems via the bus width arbitration control line I / F 206 in order to arbitrate the bus width with each other.

Next, the procedure for the subsystem to function as the data width arbitration means will be described with reference to FIG. The program shown in FIG. 3 (hereinafter referred to as program A) is a step
As indicated by 302, it continues to run while there is a data transfer request. Step 303 is the determination of whether or not the bus width is specified,
If not, the 8-bit width bidirectional data transfer shown in steps 304 and 305 is executed. If the bus width is specified, the specified data width is read in step 306. Here, the designated data width is designated by each of the bus width arbitration means 9 to 12, but in the case of this example, the function of the bus width arbitration means 9 to 12 is the same one microprocessor shown in FIG. Since it is realized by another program executed above (hereinafter referred to as program B), the actual reading is performed through a predetermined area on the memory 205 in FIG. Step 307 shows a loop executed while data is received. If it is determined in step 308 that the data is from the system bus to each of the computing means 1 to 4, as shown in steps 311, 312, It is converted into an 8-bit width and transferred to each of the arithmetic means 1 to 4. If there is reverse data, step
As indicated by 309 and 310, 8-bit width data is converted into a designated data width and transferred to the system bus.

Next, with reference to FIG. 4, a procedure for the subsystem to perform the functions of the bus width arbitration means 9 to 12 will be described. Steps
402 indicates that program B continues to run while the system is running. Step 403 determines whether or not there is a bus request. If not, it is determined in step 404 whether the bus is currently used. If it is being used, the process directly returns to step 402 to continue the execution. If it is not used, it is judged in step 405 whether or not the bus is secured, and if it is secured, it is released in step 406,
If not, return to step 402. When there is a bus request in step 403, first, in step 407, the process waits in step 408 while the other party to be connected is busy. If the connection can be established, it is determined in step 409 whether or not a bus having the required number of lines can be secured.
In step 411, the bus is secured, and each computing means is notified of it. Then, steps 404, 405, and 406 are executed. If the bus cannot be secured in step 409, steps 412 and 413
Keep waiting until it becomes possible, as shown in step 4. If it becomes possible, perform arbitration work in step 414 and then execute step 4
Execute 10,411,404,405,406.

As described above, according to the present embodiment, the plurality of calculation means 1 to
4 and a data bus 14 including a plurality of information transmission lines,
Bus width arbitration means 9 to 12 for allocating the number of information transmission lines corresponding to the data transfer rates required by the respective arithmetic means 1 to 4 to the respective arithmetic means 1 to 4, and the input / output data of the respective arithmetic means 1 to 4. A plurality of data width converting means 5-8 for converting each of the data widths into the respective assigned data widths, a bus width arbitration line 13 for exchanging information necessary for the arbitration work by each bus width arbitration means 9-12, and each bus width. By providing the data width control lines 15 to 18 for notifying the data width converting means 5 to 8 of the bus width acquired by the arbitration means 9 to 12, the system bus 14 is provided.
Within the allowable range of 1, the data transfer required by the plurality of arithmetic units 1 to 4 can be simultaneously executed in parallel. as a result,
The data buffer can be omitted or its capacity can be reduced as compared with the case where the entire system bus 14 is switched in a time division manner to execute the data transfer.

As described above, according to the present invention, the bus width arbitration means allocates the required number of information transmission lines to each arithmetic means in accordance with the request of the arithmetic means, and the data width conversion means causes the arithmetic means to enter. Since the output data is returned to the assigned data width, a plurality of arithmetic means can access the system bus at the same time, which improves the efficiency of use of the system bus and allocates a number suitable for the data transfer rate required by the arithmetic means. Therefore, a data buffer required for time division transfer is not required, or the required buffer capacity can be reduced.

Therefore, since the right to use the system bus is controlled for each information transmission line, it is possible to efficiently realize an AV system or the like that requires simultaneous transfer of audio data and video data in synchronization.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an example in which each data width conversion means and each bus width arbitration means of FIG. 1 are constructed by using a microprocessor. FIG. 3 is a pad diagram showing an example of a procedure for realizing the function of the data width conversion means, and FIG. 4 is a pad diagram showing an example of a procedure for each bus width arbitration means controlling system bus allocation, FIG. 5 is a block diagram showing a basic portion of a conventional CD-I system, and FIG. 6 is a block diagram of an information processing apparatus showing a portion related to the present invention extracted from FIG. 1 ... 1st arithmetic means (CPU), 2 ... 2nd arithmetic means (AP), 3 ... 3rd arithmetic means (DMAC), 4 ... 4th arithmetic means (memory), 5 ... ... first data width conversion means,
6 ... second data width converting means, 7 ... third data width converting means, 8 ... fourth data width converting means, 9 ... first
Bus width arbitration means, 10 ... Second bus width arbitration means, 11 ...
… Third bus width arbitration means, 12 …… Fourth bus width arbitration means, 13 …… Bus width arbitration control line, 14 …… System bus, 15
...... First data width control line, 16 ...... Second data width control line, 17 ...... Third data width control line, 18 ...... Fourth data width control line, 201 ...... Microprocessor, 202 ...... Program ROM, 203 ...... First I / O latch circuit, 204 ...... Second
I / O latch circuit, 205 ... Memory, 206 ... Bus width arbitration control line I / F.

Claims (1)

(57) [Claims] 1. A plurality of arithmetic means, a system bus composed of a plurality of information transmission lines, and a number of information transmission lines commensurate with a data transfer rate required by each arithmetic means are assigned to each arithmetic means. The bus width arbitration means includes a bus width arbitration means and a plurality of data width conversion means for converting the input / output data input / output with a specific data width into assigned data widths. When a data transfer request is received from the arithmetic means, an information transmission line that is not used for data transfer between other arithmetic devices is assigned to the data transfer requested by the arithmetic means to effectively utilize the system bus. Processing equipment.