JP2684455B2 - Method for producing thin silicon-on-insulator layer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a silicon-on-insulator structure, and particularly to the manufacture of such a structure using a novel etch stop comprising a silicon-germanium alloy. .

Background Description At the present stage of very large scale integrated circuits (VLSI), the size of transistors and semiconductor devices has been reduced to less than 1 micrometer, and many new problems have to be addressed. Greater isolation is generally required between devices. Since complementary MOS (CMOS) is applied, this isolation must prevent latch-up. At the same time, this increased isolation should not be provided at the expense of possible chip space.

It is clear that semiconductor crystal formation (SOI) technology on insulating substrates is a particularly promising approach to tackling this problem. A substrate for forming a semiconductor crystal on an insulating substrate is used for manufacturing a device having high speed, latch-up resistance, and large radiation transmissivity. The method of ion-implanting oxygen into single crystal silicon to form an insulating layer inside (SIMOX) is currently the most well-studied SOI system for replacing silicon with sapphire. A common example of this technique is RJLine back, “SO
Buried Oxide Mark Standard Route for Buried Oxide to I-chip
s Route to SOI Chips) ", Blectornics Week, Oct.1,198
4, pp. 11-12.

As shown in this article, oxygen ions are implanted in the substrate silicon to form a buried oxide layer in the substrate silicon. The implant is then annealed for 2 hours so that the silicon portion overlying the buried oxide becomes single crystal silicon. Thereafter, various semiconductor devices are formed on the single crystal layer. The underlying buried oxide provides isolation between adjacent device and substrate portions.

Despite SIMOX being a promising technology, continuous dislocations generated by implantation into the active device area are
Limit material performance. In addition, poor quality buried oxide results in backside channel leakage.

Bond and etch back silicon-on-in as an alternative to SIMOX
sulator (BESOI)] is a cleaner oxide with less defects and charge trapping in buried oxides.
It has the advantages of a silicon interface.

This material is generated by oxidizing the seed and / or handle wafers, followed by the bonding of the two wafers. Active device areas are created on the seed wafer by folding and etching to the desired film thickness. Although this technique is suitable for manufacturing 600 nm SOI, the presence of etch stops is essential to achieve SOI wafers with preliminary thicknesses of 500 nm or less.

Boron regions heavily doped by diffusion or implantation into silicon have been reported to create an effective etch stop, and also for complementary types made from these materials.
MOS devices have also been reported. Silicon film technology uses similar techniques to produce these materials. The use of boron is inherently limited because it is a p-type dopant in silicon. Both implantation and diffusion of boron result in residual p-doping of the silicon film. Boron introduction by ion implantation and annealing also results in the generation of continuous dislocations in the device area. This limits the performance of devices made from these materials.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an improved method of manufacturing silicon on insulator (SOI).

Another object of the present invention is to provide a silicon-on-insulator method wherein the final silicon layer is substantially uniform and defect free.

Yet another object of the present invention is to provide an improved method of making silicon on insulator wherein etching of the final silicon layer leaves residual dopants and defects in the final silicon layer. Can be adjusted more accurately without.

Another object of the invention is to produce an SOI wafer with a preliminary thickness of 500 nm or less.

These and other objects of the invention are realized in a method of forming a thin silicon-on-insulator structure having a defect-free device region. A distorted etch stop layer is formed on the silicon substrate, and the etch stop layer comprises at least one of silicon-germanium alloy or silicon.
It consists of an alloy of four Group IV elements. After the silicon cap layer is formed on the strained etch stop layer, the silicon cap layer is bonded to a mechanical substrate having an insulating layer such that the insulating layer interposes the insulating layer therebetween. Finally, without removing the underlying portion of the silicon cap layer, the silicon substrate and the distorted etch stop layer are removed, and the portion under the silicon cap layer is removed on the mechanical substrate to form a thin semiconductor layer. Remain in.

An advantage of the present invention over the old method is that the etch stop is grown in the wafer using techniques such as molecular beam epitaxy or chemical vapor deposition (CVD), thereby minimizing defect incorporation. is there.

Although an alternative method of producing an etch stop layer is by germanium ion implantation, an implantation step is not necessary. Moreover, because germanium is not an electrically active dopant in silicon, no residual p'or n'doping remains after subsequent steps.

A method of manufacturing SOI according to the present invention comprises the steps of: selecting one or more silicon substrates; forming an etch stop layer on at least one of the one or more silicon substrates; The etching stop layer is composed of an alloy of silicon and at least one other group IV element as a sole dopant (for example, an alloy of silicon and tin, an alloy of silicon and lead, an alloy of silicon and germanium, etc.). Forming a silicon cap layer on the layer, bonding the silicon cap layer to a mechanical substrate having an insulating layer such that the insulating layer is interposed therebetween, and one or more of the above. Removing at least one of the above silicon substrates and the etching stop layer,
Thereby, the silicon cap layer is left on the mechanical substrate to form a semiconductor thin film.

The etch stop layer here is formed by depositing a layer of an alloy of silicon and another Group IV element.

In a preferred embodiment of the method according to the invention, the step of bonding a silicon cap layer to a mechanical substrate comprises the step of forming a layer of silicon dioxide on the exposed surface of the silicon cap layer and the exposed surface of the mechanical substrate. Further comprising the steps of forming a layer of silicon dioxide, contacting both layers of said silicon dioxide, and heating both layers of said silicon dioxide to form a bond between both layers. Is.

Furthermore, the method according to the invention, in an interesting aspect, comprises: selecting at least a first and a second silicon substrate, forming a first etching stop layer on the first silicon substrate; The etching stop layer is made of an alloy of Group IV element other than silicon, and a step of forming a first silicon cap layer on the first etching stop layer, and a machine having the first silicon cap layer and an insulating layer. A dielectric substrate such that the insulating layer is interposed therebetween, forming an additional etch stop layer on the second silicon substrate, and the additional etch stop layer is silicon-germanium. Forming an additional silicon cap layer on the additional etch stop layer, the second silicon substrate being in front of the mechanical substrate. Bonding to a surface facing the first silicon substrate, and removing the first and second silicon substrates and the strained first and second etch stop layers, thereby providing the first and second silicon caps. Leaving layers on both sides of the mechanical substrate to form a semiconductor thin film.

The method according to the invention also provides, in another interesting aspect, the step of selecting one or more silicon substrates and a first etching stop on at least one of the one or more silicon substrates. A layer is formed, the etching stop layer is made of doped silicon, a gap layer is formed on the first etching stop layer, and a second etching stop layer is formed on the gap layer. The second etching stop layer is made of a silicon-germanium alloy, and a silicon cap layer is formed on the second etching stop layer; and the silicon cap layer is formed on a mechanical substrate having an insulating layer. Bonding an insulating layer intervening therebetween, and at least one of the one or more silicon substrates. Removing one and the first and second etch stop layers, thereby leaving the silicon cap layer on the mechanical substrate to form a semiconductor thin film.

Other objects, features and advantages of the present invention will be apparent to those skilled in the art from the details of the preferred embodiments set forth below and listed in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS A more complete appreciation of the invention, as well as a better understanding thereof, and many of its attendant advantages, will be readily obtained by reference to the following details when considered in connection with the accompanying drawings. right.

FIG. 1 is an explanatory diagram of a seed wafer.

FIG. 2 is an illustration of a handle wafer.

FIG. 3 is an illustration of a seed and handle wafer bonded together.

4 is an illustration of the structure of FIG. 3 after lapping and polishing.

FIG. 5 is an illustration of the structure of FIG. 4 after selectively etching the silicon-germanium alloy layer.

 FIG. 6 is an illustration of the SOI structure of the preferred embodiment.

 FIG. 7 is an explanatory diagram of the second embodiment of the present invention.

FIG. 8 shows the SO obtained as a result of the second embodiment of the present invention.
It is explanatory drawing of I structure.

9 and 10 are explanatory views of a seed and a handle wafer according to the third embodiment of the present invention.

FIG. 11 is an illustration of the seed and handle wafer of the third embodiment after being bonded together.

FIG. 12 is an explanatory diagram of the SOI structure obtained as a result of the third specific example.

FIG. 13 is an explanatory diagram of a seed wafer of a fourth specific example of the present invention.

Description of the Preferred Embodiments The solution to the problems mentioned in the background of the invention is to provide a growth-like solution as an etch stop in an assembly of thin film silicon using "bonding and etchback of silicon on insulator (BESOI) technology". Strained Si _1-x Ge _x alloy layer (anas−
grown Si _1-x Ge _x alloy strained layer).

In this process, a strained layer silicon-magnesium alloy is grown on a silicon substrate followed by a variable thickness silicon cap. Since this cap is the area where the device will be assembled, subsequently bonded, thinned, and etched back, it is important that the cap be defect-free and not impure.

Referring now to the drawings and in particular to FIG. 1, a silicon seed wafer with an incorporated etch stop is manufactured as follows. First, the p- or n-doped silicon wafer 20 is cleaned using standard cleaning operations. The cleaned wafer 20 is then placed in a system in which epitaxial silicon or germanium can be grown. Both molecular beam epitaxy (MBE) and chemical vapor deposition (CVD) are currently viable methods of epitaxial growth. Easily degas and place the wafer in the growth chamber, then
The silicon oxide is removed in situ by heating to 700 to 1100 ° C, more preferably 750 to 950 ° C, and most preferably 800 to 900 ° C. Oxide can be removed by heating in silicon flux or bombardment of rare gas ions.

Silicon buffer layer 22 is then grown on wafer 20.
Although not required for the present invention, buffer layer 22 helps to obtain a smooth silicon surface without pitting or holes. This buffer layer 22 grows at a temperature of 650 ° C. to a thickness of 100Å to 1 μm. The preferred thickness for the buffer layer 22 is 300 to 500Å. Etching stop layer 24
Are then grown on the buffer layer 22. Etching stop layer
24 can be grown in a seed wafer by techniques such as molecular beam epitaxy or chemical vapor deposition. These growth techniques are well-developed and yield sharp Silicon / Alloy interfaces. The etching stop layer 24 is a Si _1-x Ge _x alloy (x = 0.1 to 0.
5) may be. More preferably x = 0.2
0.4. In the preferred embodiment, the etch stop layer 24 is a Si _0.7 Ge _0.3 alloy and is grown on the buffer layer 22 at 400 to 900 ° C, more preferably 500 to 800 ° C. The thickness of the etching stop layer 24 is 100 to 5000Å
Between. A more preferable thickness is 200 to 700 ° C. The etching stop layer 24 may be composed of an alloy of silicon and another group IV element such as tin and lead.

The silicon cap layer 26 then has a thickness of 200Å or 1μ
Grow on m-thick silicon germanium alloy. The silicon cap layer is more preferably grown at 500 to 800 ° C. The doping type and doping concentration of this epitaxial cap layer 26 are determined by the device being built. In this invention, the silicon cap layer 26 is
Can grow to as small as 10Å. However, with modern technology, 1/4 to 1/2 μm is the practical limit. Following deposition, the seed wafer of Figure 1 is cooled to room temperature and removed from the growth system.

The handle wafer shown in FIG. 2 is made by thermally oxidizing the surface of the silicon wafer 20 to produce a SOI insulating layer 32 of SiO ₂ . A on wafer 30 (100)
The surface provides a good interface to SiO ² and good anisotropic etch properties. Here, “anisotropic etching” means etching (anisotropic etching) that proceeds in different directions at different rates in the material to be etched. Examples of anisotropic etches are, for example, US Pat. No. 4606113, column 1, lines 54-56, and US Pat.
It can be found at 0, col. 9, line 11 to col. 10, line 44. The seed wafer epitaxial layer 26 is also oxidized to produce an insulating layer thereon. The seed wafer and handle wafer are then layered on top of each other, as shown in FIG. 3, so that insulating layers 28 and 32 contact and produce insulating layer 29. On the other hand, even if either the seed wafer of FIG. 1 or the handle wafer of FIG. 2 is oxidized, the insulating layer 29 of FIG. 3 is produced. Insulating layer (SiO ₂ layer) 28 and
32 is the thickness of the handle wafer and the silicon cap layer 26
It can vary depending on the thickness required to achieve the separation between. This will depend on the final device assembled from the SOI device.

Either the surface seed or the handle wafer is intangible. The seed and substrate wafers were then exposed to approximately 70% in an oxidizing atmosphere of either wet or dry oxygen.
Bonding is accomplished by annealing the contacting wafers at temperatures above 0 ° C. 700 to 1 in steam
Binding at 000 ° C will result in a strong binding pair. An alternative bonding technique is US Pat. No. 3,332,137 to Kenny.
And U.S. Pat. No. 3,953 to Antipas
It is described in 9,045.

The Si region 20 of the bonded pair is now unnecessary. Its first use was for the formation and maintenance of epitaxial layer 26. The excess Si region 20 is removed by one of various methods. For example, it is removed mechanically by rubbing and / or chemical polishing followed by etching in a hydrogen fluoride-nitric acid-acetic acid (HNA) solution. The use of HNA is described in the book “Semiconductor Silicon 1973” (Electrochemical Society, Princeton, New Jersey (NJ),
Huff and Burgess Edition], "Controlled Preferential Etchin Technology".
g Technolo-gy) ”, discussed by Muraoka et al., page 326. Thus, most of the excess Si region 20 is on the silicon-germanium alloy etch stop layer 24. The silicon is removed leaving about 1 to 2 μm of silicon, and the cap layer 26 and bulk region 30 are separated by an insulating layer 29, as shown in Figure 4. If the buffer layer 22 is not used, one after etching and polishing. To 2 μm of Si layer 20. After polishing, the wafer of Figure 4 is cleaned and placed in a selective etchant buffer layer 22 as shown in Figure 4.
(It is no 1 2 [mu] m) residual silicon containing the selective etchant, such as potassium hydroxide 100 g, using a made of K ₂ Cr ₂ O ₇ 4g and propanol 100ml in water 400 ml, the temperature control rotary etching system 25 It is removed by etching at ° C.

For example, undoped silicon layer 20 and buffer layer 22 have been shown to etch at a rate of 17 to 20 nm / min.
Growth-like Si _0.7 Ge _0.3 alloys have better selectivity than 17: 1 at 1 nm /
It was shown to etch at a rate of minutes. Therefore,
When the etching reaches the surface of the distorted alloy layer 24, it shows a significant etching rate. It is a 60 nm distorted alloy layer 24
Therefore, it takes about 1 hour to break through the etching stop region 24. Therefore, during that time interval, the wafer must be selectively etched before it can be etched down to cap layer 26.

Next, the structure of FIG. 5 has a silicon-germanium alloy layer 24.
Suffer a second etch that attacks and selectively removes. For example, the second etch may consist of ammonia in the ratio 1: 1: 4, hydrogen peroxide and water.

Thereafter, the SOI structure of FIG. 6 remains for further processing to form various semiconductor devices.

The etch rates shown and the selectivity of this etch stop / etch solution system are effective for thinning processes that require the removal of 2 μm silicon and a uniform thickness of 20 nm. To further elaborate on the various etches that can be used in the present invention, instead of other bonding methods and other mechanical substrates, Abernaze
U.S. Pat. No. 4,601,779 (19) issued to them et al.
July 22, 1986) is hereby incorporated by reference.

In the second embodiment shown in FIG. 7, SOI wafers can be stacked to produce three-dimensional integrated circuits with increased density. The first seed wafer is
It includes a buffer layer 42, a silicon-germanium etch stop layer 44, and then a Si region 40 on which a silicon cap layer 46 is grown. The second seed wafer has a buffer layer 52, a silicon-germanium etch stop layer 54, and then a silicon cap layer 56 grown thereon.
Includes Si region 50. The substrate wafer includes a silicon wafer 60, which is oxidized to form SiO ₂ on both sides of the surface.
Insulating regions 61 and 63 are formed. The first seed wafer is bonded to the insulating region 61 of the substrate wafer and the second seed wafer is bonded to the insulating region 63 of the substrate wafer. The process used to manufacture the device is the same as that used in the preferred embodiment. The only difference is the formation of the second seed wafer and subsequent bonding to the second oxidized region of the substrate wafer.
After the bonding step described above is complete, the structure of FIG. 7 is then etched to remove layers 40, 42, 44, 50, 52, 54 as described above with respect to FIGS. 1-6 of the preferred embodiment, and The structure of FIG. 8 is left for further processing.

9 to 12 show a third embodiment. In these figures, 70 is a p- or n-doped silicon substrate,
72 is a silicon-germanium alloy etching stop layer, 74 is a silicon cap layer, 76 is an insulating layer, and 80 is a silicon substrate, and 81 and 82 are insulating layers. In this embodiment, the silicon-germanium etch stop layer 72 is formed by burying germanium ions in the silicon substrate 70. The buried ions may be tin or lead to form a silicon-tin or silicon-lead alloy. The amount of germanium ions used should be sufficient to obtain the alloy in the proportions as described in the first embodiment, and the germanium ion-energy should give the desired epitaxial layer thickness. Should be selected for the appropriate penetration depth required. The processing steps shown in Figures 10 to 12 are similar to those of the first embodiment as shown and described in Figures 1 to 6. That is, the seed wafer (Fig. 9) and the handle wafer (Fig. 10)
Are stacked on top of each other, as shown in FIG. 11, so that the insulating layers 76 and 82 on their surfaces come into contact to yield the insulating layer 81. After that, excess Si region 70 is removed by etching or the like, and further polishing and selective etching are performed, and finally, the SOI substrate shown in FIG. 12 is manufactured. The detailed description of these processing steps is the same as in the case of the first embodiment (FIGS. 1 to 6), and will not be described in further detail here.

FIG. 13 shows a fourth embodiment. In the figure, 90 is a silicon substrate, 92 is a first etching stop layer, and 93
Is a gap layer, 94 is a second etching stop layer, 95 is a silicon cap layer, and 96 is an insulating layer (oxide layer). The seed wafer shown in this figure forms a first etching stop layer 92 of a boron-doped silicon layer on a silicon substrate 90, and a second layer of a silicon-germanium alloy on it through a gap layer 93. The structure is such that the etching stop layer 94 is formed and the silicon cap layer 95 is further formed, but it is processed according to the case of the other embodiments described above. In this fourth embodiment, a combination of two separate etch stop layers could be grown in the silicon substrate. For example, boron could be buried in the silicon substrate 90 to form a first etch stop layer 92, and then a second etch stop layer 94 of silicon-germanium alloy defined by burying germanium ions. Boron ions will be buried with sufficient energy to form the first etch stop layer 92 below the silicon-germanium etch stop layer 94. Boron and germanium ions may be buried before or after the oxide layer 96 is formed. Alternatively, the separate etch stop layers 92 and 94 may be aligned grown by molecular beam epitaxy (MBE) or chemical vapor deposition (CVD) with a gap 93 separating the two etch stop layers. It may be grown epitaxially.

Alternatively, one etch stop layer may be grown epitaxially and the other etch stop layer may be buried, or vice versa.

The use of two etch stop layers is due to the boron etch stop layer 92, in other words the silicon layer 90.
And the etching rate of the etching stop layer 92 provides a surprisingly high selectivity. Also, by using the interstitial layer 93 and the silicon-germanium etch stop layer 94, any boron tail will be minimized. After processing the structure of FIG. 13, the silicon layer 90 and the etch stop layer 92 are
nathey), U.S. Pat. No. 4,601,779, followed by removal and final fabrication into an SOI substrate. Layers 93 and 94 would be removed as shown and described in the first embodiment of the invention.

So far, the silicon-germanium alloy has been used to bond and etch back silicon on insulator.
-And-etchback silicon-on-insulator (wafer)
ers) production method.

The process described in the preferred embodiment, the silicone film can be grown thin enough that desired by using an etching stop Si _1-x Ge _x. The etch stop grows in the material, which allows the growth of defect-free device regions, since the etch stop need not be buried.

Since germanium is not an electrically active dopant in silicon, device performance is not limited by the presence of carrier dispersion centers from ionized dopants. Therefore. Complementary devices are assembled without compensation. In addition, the back channel (ba
The ck channel) can be radiation hardened in a simple manner by the existing technology of space and defense technology.

Another application of this technique also includes the fabrication of silicon films for use as X-ray masks.

Many modifications and variations of the present invention are possible in light of the above teachings. Therefore, within the scope of the appended claims, the invention can be understood to be practiced without the specific description herein.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Kubu, Francis J. Dee. C., Washington, USA. 20375-5000, Naval Research Laboratory, Code 6813 (56) References JP 58-200525 (JP, A) JP 1-136328 (JP, A)

Claims (19)

(57) [Claims] 1. Selecting one or more silicon substrates, forming an etch stop layer on at least one of the one or more silicon substrates, said etching stop layer comprising: Forming a silicon cap layer on the etching stop layer, the silicon cap layer comprising an alloy of silicon and at least one other group IV element, the silicon cap layer being provided on a mechanical substrate having an insulating layer; Interveningly connecting the two,
And removing at least one of the one or more silicon substrates and the etch stop layer, thereby leaving the silicon cap layer on the mechanical substrate to form a semiconductor thin film. A method of forming a semiconductor thin layer on which a semiconductor device can be subsequently formed. 2. Selecting one or more silicon substrates and forming an etch stop layer on at least one of the one or more silicon substrates.
The etching stop layer is made of an alloy of silicon and tin, and a step of forming a silicon cap layer on the etching stop layer, the silicon cap layer is provided on a mechanical substrate having an insulating layer between the insulating layer and the insulating layer. Binding to intervene in
And removing at least one of the one or more silicon substrates and the etch stop layer, thereby leaving the silicon cap layer on the mechanical substrate to form a semiconductor thin film. A method of forming a semiconductor thin layer on which a semiconductor device can be subsequently formed. 3. Selecting one or more silicon substrates and forming an etch stop layer on at least one of the one or more silicon substrates.
The etching stop layer is made of an alloy of silicon and lead, and a step of forming a silicon cap layer on the etching stop layer; and a step of forming the silicon cap layer on a mechanical substrate having an insulating layer. Connecting so as to intervene between them,
And removing at least one of the one or more silicon substrates and the etch stop layer, thereby leaving the silicon cap layer on the mechanical substrate to form a semiconductor thin film. A method of forming a semiconductor thin layer on which a semiconductor device can be subsequently formed. 4. The method of claim 1, wherein the etching stop layer comprises a silicon-germanium alloy. 5. The method of claim 4, wherein the silicon-germanium alloy has the composition: Si _1-x Ge _x (x = 0.1-0.5). 6. The method of claim 1 wherein the step of forming the etch stop layer comprises depositing a layer of an alloy of silicon and another Group IV element. 7. The method of claim 6 wherein said alloy comprises a silicon-germanium alloy. 8. Choosing one or more silicon substrates, forming an etch stop layer on at least one of the one or more silicon substrates, said etch stop layer comprising: A layer of an alloy of silicon and tin is deposited on the one or more silicon substrates, the step of forming a silicon cap layer on the etching stop layer, and the silicon cap. Bonding the layer to a mechanical substrate having an insulating layer such that the insulating layer is interposed between the two.
And removing at least one of the one or more silicon substrates and the etch stop layer, thereby leaving the silicon cap layer on the mechanical substrate to form a semiconductor thin film. A method of forming a semiconductor thin layer on which a semiconductor device can be subsequently formed. 9. Selecting one or more silicon substrates and forming an etch stop layer on at least one of the one or more silicon substrates.
The etching stop layer is formed by depositing an alloy layer of silicon and lead on the one or more silicon substrates, and forming a silicon cap layer on the etching stop layer. Bonding the silicon cap layer to a mechanical substrate having an insulating layer such that the insulating layer is interposed therebetween.
And removing at least one of the one or more silicon substrates and the etch stop layer, thereby leaving the silicon cap layer on the mechanical substrate to form a semiconductor thin film. A method of forming a semiconductor thin layer on which a semiconductor device can be subsequently formed. 10. The step of bonding a silicon cap layer to a mechanical substrate forms a layer of silicon dioxide on the exposed surface of the silicon cap layer, and a layer of silicon dioxide on the exposed surface of the mechanical substrate. The method of claim 1 further comprising the steps of forming, contacting both layers of said silicon dioxide, and heating both layers to form a bond between said two layers of silicon dioxide. . 11. The step of bonding a silicon cap layer to a mechanical substrate comprises forming a layer of silicon dioxide on the exposed surface of the silicon cap layer; and contacting the layer of silicon dioxide with the mechanical substrate. The method of claim 1 comprising the steps of: and heating the layer of silicon dioxide and the mechanical substrate to form a bond therebetween. 12. The step of bonding a silicon cap layer to a mechanical substrate forms a layer of silicon dioxide on an exposed surface of the mechanical substrate; and contacting the layer of silicon dioxide with the silicon cap layer. The method of claim 1 comprising the steps of: heating the layer of silicon dioxide and the silicon cap layer to form a bond therebetween. 13. The step of removing at least one of the one or more silicon substrates and the etch stop layer mechanically removes a portion of at least one of the one or more silicon substrates. Selectively removing at least one remaining portion of the one or more silicon substrates and a portion of the etching stop layer with a selective etchant; Etching the balance with a second etchant that selectively removes the etch stop layer. 14. Selecting at least first and second silicon substrates, forming a first etching stop layer, said first etching stop layer being different from silicon on said first silicon substrate. A step of forming a first silicon cap layer on the first etching stop layer, which is made of an alloy of a group IV element; and a step of forming the first silicon cap layer on a mechanical substrate having an insulating layer. Interposing an intervening bond, and forming an additional etch stop layer on the second silicon substrate, wherein the additional etch stop layer comprises a silicon-germanium alloy and the additional etch stop layer comprises: A second silicon cap layer is formed on the etching stop layer, and between the silicon cap layer of the second silicon substrate and the mechanical substrate having an insulating layer. Bonding a silicon cap layer of the second silicon substrate to a surface of the mechanical substrate facing the first silicon substrate such that the insulating layer is interposed; and the first and second silicon substrates. And removing the distorted first and second etch stop layers, thereby leaving the first and second silicon cap layers on both sides of the mechanical substrate to form a semiconductor thin film. A method for forming a semiconductor thin layer on which a device can be subsequently formed. 15. The step of forming the etching stop layer comprises implanting a group IV element ion other than silicon into the silicon layer to form a buried silicon-group IV element alloy layer. The method of claim 1. 16. The method of claim 15, wherein the ions comprise tin ions such that the buried layer comprises a silicon-tin alloy. 17. The ion comprises lead ions such that the buried layer comprises a silicon-lead alloy.
The described method. 18. The method of claim 15, wherein the ions comprise germanium ions such that the buried layer comprises a silicon-germanium alloy. 19. Selecting one or more silicon substrates, forming a first etch stop layer on at least one of the one or more silicon substrates, and etching. The stop layer is made of doped silicon, and a step of forming a gap layer on the first etching stop layer, a step of forming a second etching stop layer on the gap layer, and a step of forming the second etching stop layer. Is formed of a silicon-germanium alloy, and a step of forming a silicon cap layer on the second etching stop layer, the silicon cap layer being interposed between a mechanical substrate having an insulating layer and the insulating layer therebetween. To combine like this,
And removing at least one of the one or more silicon substrates and the first and second etch stop layers, thereby leaving the silicon cap layer on the mechanical substrate to form a semiconductor thin film. A method of forming a semiconductor thin layer on which a semiconductor device can be subsequently formed.