JP2683023B2 - Data recording device - Google Patents

Description

The present invention relates to a data recording device, and more particularly to a data recording device for recording digital signals having different bit rates.

[Conventional technology]

In recent years, the speed of digital transmission technology has been increased, and it has become possible to transmit digital signals at a high bit rate of 100 Mbps or more. Also, various transmitters and transmission media for performing transmission at such a high bit rate have been disclosed. Further, data recorders for recording these high bit rate digital signals are being developed.

[Problems to be solved by the invention]

By the way, data transmission at such a high bit rate has a wide range of uses, and various transmission bit rates are set. For example, even when the main information to be transmitted is limited to so-called high-definition television signals, various transmission bit rates are assumed depending on the band compression method, the handling of voice signals, and the amount of other information to be transmitted.

In the case of recording digital signals having these various transmission bit rates, it has been customary to have a data recording device dedicated to each bit rate. Also, even if the same mechanism is used to record data of different bit rates, it is necessary to separately prepare a clock frequency, a recording format, etc. at the time of recording. Therefore, the apparatus itself has a plurality of systems of signal processing units, and in particular when recording various digital signals, one apparatus becomes large in size, which is not preferable.

In view of the above background, it is an object of the present invention to provide a data recording device that can be shared in most parts of a signal processing unit and accordingly is small and can record digital signals of various transmission bit rates. There is.

[Means for solving the problem]

For such a purpose, according to the data recording apparatus of the present invention, the input means capable of inputting a plurality of kinds of digital signals having different bit rates, and the data different for each kind in the digital signal inputted by the input means. Forming means for forming a fixed length data block for each of the plurality of types of digital signals by adding a certain amount of subcodes, and the fixed length data block formed by the forming means on a recording medium. The recording means is configured to record on sequentially formed tracks.

[Action]

By configuring as described above, the size of the above-mentioned proprietary data area is changed only in accordance with the transmission bit rate of the input digital signal, and the main digital signal processing is hardly changed and various transmission is performed. It has become possible to record bit rate digital signals.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a recording data format of a data recorder as one embodiment of the present invention, FIG. 2 (A),
FIG. 3B is a diagram for explaining a recording pattern by the data recorder of the present embodiment, and FIGS. 3A and 3B are diagrams showing configurations of a recording system and a reproducing system of the data recorder of the present embodiment. .

FIG. 3A is a block diagram showing the configuration of the recording system of the data recorder of this embodiment, in which 1 is an input terminal of a digital signal to be recorded. The data recorder of this embodiment assumes three types of bit rates of the input digital signals, 139.264 Mbps, 135.168 Mbps and 120.6 Mbps, and can input the digital signals of these three types of bit rates.

The operation unit 2 is configured so that the user can designate a digital signal to be input to the input terminal 1, and supplies control data including data relating to the designation to the system controller 3. The clock generator 4 has three values of 17.408MHz, 16.896MHz, 15.075MHz when the input data to terminal 1 is 8 bits.
Generates different types of clocks. The selector 5 selects and outputs one of the three types of clocks according to the output of the system controller 3 based on the input designation by the operation unit 2,
It is supplied to the memory control circuit 6. The output signal of the selector 5 determines the cycle of writing data to the RAM 7.
As is well known, the memory control circuit 6 supplies a write address and a write enable signal to the RAM 7 using the output clock of the selector 5 as a write clock. In this way, the data indicating the input digital signal is written into the RAM 7.

As shown in FIG. 2A, the digital data recorder (DDR) of this embodiment includes three adjacent heads Ha, Hb, and Hc.
A magnetic tape 51 is attached to a rotating drum 50 having three heads Hd, He, and Hf which are adjacent to each other and rotate with a phase difference of 180 °.
Is wound over an angular range of 180 ° or more, and recording is performed on a magnetic tape by a total of 6 heads.

The heads Ha, Hb, and Hc are configured to rotate as a predetermined distance shift in the rotation axis direction, and the shift amount is set according to the recording track pitch. The same applies to the heads Hd, He, Hf.

FIG. 2 (B) shows a recording pattern on the magnetic tape, where ta, tb, tc, td, te, and tf are rotating heads Ha, Hb, Hc, respectively.
It is a track formed by Hd, He, and Hf, and an arrow x indicates the trace direction of each head.

Now, assuming that the head rotation speed is 4000 rpm and a digital signal of 139.264 Mbps is to be recorded, the recording data amount required for one track is as follows.

Therefore, 170 data groups of 256 words should be recorded.

FIG. 1 shows a data format for one track of DDR of this embodiment, and this format is the same when recording any of the above-mentioned three kinds of digital signals. As shown in the figure, in the DDR of this embodiment, C2 parity (inner code) is added (128 × 4) words and C1 parity (outer code) is added (3 × 90) words to (128 × 86) word data, and this data is added. The four blocks form a data block for one track. Therefore, the data capacity for one track is (256 x 172)
It becomes a byte.

Here, since (256 × 170) bytes are sufficient for recording a digital signal of 139.264 Mbps, the (256 × 2) bytes in the shaded area in the figure are used as subcodes.

Next, when recording a digital signal of 135.168 Mbps, the amount of data that needs to be calculated and recorded in one track is (256 × 165) bytes, and (256 × 7) bytes are used as subcodes, During the block, the area occupied by the data representing the digital signal becomes smaller. Further 120.6Mbp
When recording a digital signal of s, the amount of data that needs to be recorded in one track is less than (256 x 148) bytes, so the data indicating the digital signal is arranged up to the middle of the 152nd sync block. At least (256 x 24)
Bytes are used as subcode.

In this way, regardless of the bit rate of the digital signal to be recorded, the recording bit rate is changed by switching the size of the area occupied by the data indicating the digital signal (hereinafter referred to as main data) within the data block. It is not necessary, and the recording data format can be shared.

Therefore, the read clock of the same frequency can be used from the RAM 7 regardless of the input signal. Frequency divider 8
Indicates the write clock output from the selector 5 (4000n / 6
0) The frequency is divided so as to become Hz (n is an integer) and supplied to the PLL 10 and the drum servo circuit 11 at the subsequent stage. The drum servo circuit 11 controls the rotation of the drum 50 using the output of the drum phase detector 13 and the output of the frequency divider 8. Now, if n is 1, the frequency division ratio of the frequency divider 8 is (17.408 × 10 ⁶ × 60/4000 =) 1 / 261,135.168M when a digital signal of 139.264 Mbps is input.
When inputting a digital signal of bps (16.896 × 10 ⁶ × 60/4000
=) 1 / 253,440, and similarly, when inputting a 120.6 Mbps digital signal, it becomes 1 / 226,125. The frequency division ratio of the frequency divider 8 is determined by the data obtained from the frequency division ratio setting circuit 9 based on the data relating to the designated input output from the system controller 3. For example, this division ratio setting circuit 9
Is a lookup table and outputs preset data of a counter in the frequency divider 8.

When the recorded data as shown in Fig. 1 is read serially from RAM7, the required clock frequency is (40
(00 × 6 × 256 × 172/60) 17.603 MHz, which is obtained by multiplying the (4000 n / 60) Hz clock output from the frequency divider 8 by the PLL 10.

The number of words of main data in each data block of the RAM 7 is written from a sub-code adding circuit 12 at a predetermined position in the sub-code area. The subcode adding circuit 12 is controlled by designated input data from the system controller 3.

The data read from the RAM 7 is distributed to three recording systems in data block units, and error correction encoders (ECC, EN) 15a, 15 for adding the above-mentioned C1, C2 parity and Sync, ID.
b, 15c, and further to each head via digital modulators 16a, 16b, 16c. Heads Ha and Hd, Head Hb as shown
, He, and heads Hc and Hf are recording heads of the same system.

Next, the reproducing system will be described with reference to FIG.
In FIG. 3B, the same components as those in FIG. 3A are designated by the same reference numerals. The reproduced signals of the three systems reproduced by the respective heads are demodulated by digital demodulators 21a, 21b, and 21c, then subjected to error correction by C1, C2 parity by error correction decoders 22a, 22b, and 22c, and serially. It is written to RAM27.

In the RAM 7, as described above, the data indicating the number of words of the main data arranged at the predetermined position in each data block is extracted by the subcode extraction circuit 29, and the data is sent to the system controller 23 and the memory control circuit 28. Supplied,
The system controller 23 determines the type of digital signal recorded by the data indicating the number of words of the main data, and controls the selector 5 and the frequency division ratio setting circuit 9. As a result, the selector 5 supplies a clock corresponding to the original bit rate of the recorded digital signal to the memory control circuit 28 as a read clock. This clock is frequency-divided by the frequency divider 8 at the frequency division ratio set by the frequency division ratio setting circuit 9 so as to become (4000n / 60) Hz, and is supplied to the drum servo circuit and the PLL circuit 10.

The output of the PLL circuit 10 is supplied to the memory control circuit 28 as a 17.603 MHz write clock. RAM 27 is the memory control circuit 2.
8 controls the write / read timing and address.
The reproduced digital signal is output from the output terminal 30 according to the bit rate of the original digital signal.

According to the DDR of the embodiment as described above, in the recording system, the RAM
Each bit of the signal processing system and servo system from 7 to the head performs exactly the same processing regardless of which bit rate signal is input, so different bit rates are possible without increasing the size of the device compared to the conventional DDR. It has become possible to record all digital signals of multiple types. The same applies to the reproduction system, which does not increase the scale of the apparatus.

Also, by arranging and recording the number of data in each data block in the subcode area, the address where the main data and subcode written in the RAM 27 as a buffer memory are immediately known at the time of reproduction. be able to. Further, the original bit rate of the recorded digital signal can be determined, and the original digital signal can be automatically restored. Further, since the data indicating the number of the main data is subjected to error correction by C1, C2 parity, highly reliable reproduction can be automatically performed.

In this specification, a multi-channel data recorder is taken as an example, and a high-definition video signal is taken as an example of a digital signal to be recorded, but the present invention is also applied to a data recorder for recording another digital signal on a single-channel data recorder. Of course, it can be applied.

Further, in the present specification, only the case where the bit rate of the digital signal to be handled is an integral multiple of the number of revolutions of the head has been described, but the bit rate of the digital signal to be recorded is not limited to this. If the bit rate of the digital signal to be recorded is not an integer multiple of the number of head rotations, it is necessary to switch the number of main data for each track, but even in this case, by recording the number of main data in the data block, Can handle.

〔The invention's effect〕

As described above, according to the present invention, the signal processing unit can be commonly used when any bit rate digital signal is input, and a plurality of types of digital signals having different bit rates can be recorded without increasing the size of the device. A data recording device can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a recording data format by a data recording device as an embodiment of the present invention, FIG. 2 (A) is a diagram showing a head structure of the device according to FIG. 1, and FIG. 2 (B). 1 is a diagram showing a recording pattern on a magnetic tape by the device shown in FIG. 1, FIG. 3 (A) is a diagram showing a schematic configuration of a recording system by the device shown in FIG. 1, and FIG. 3 (B) is a first diagram. It is a figure which shows schematic structure of the reproduction | regeneration system of the apparatus which concerns on a figure. Ha, Hb, Hc, Hd, He, Hf are rotating heads, ta, tb, tc, td, te, respectively.
Is a track, 1 is an input terminal, 7 is a RAM, 12 is a subcode adding circuit, and 15a, 15b, and 15c are error correction encoders.

 ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-58-117066 (JP, A) JP-A-56-111957 (JP, A) JP-A-60-128722 (JP, A) JP-A-63- 4461 (JP, A) JP 61-246965 (JP, A) JP 59-3765 (JP, A)

Claims (1)

(57) [Claims] 1. An input unit capable of inputting a plurality of types of digital signals having different bit rates, and a subcode having a different data amount for each type is added to the digital signal input by the input unit,
Forming means for forming a fixed length data block for each of the plurality of types of digital signals, and recording means for recording the fixed length data block formed by the forming means on tracks sequentially formed on a recording medium. A data recording device comprising: