JP2679994B2 - Vector processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]   The present invention is a vector register composed of 2 banks of RAM.
High-speed operation of computer, especially super computer
For vector processing equipment suitable for realizing high-speed machine cycles
I do. [Conventional technology]   In general, to improve the performance of supercomputers
Multiple pipeline arithmetic units in the vector processor
And multiple vector registers are provided, and instructions with no causality
Parallelization of vector data processing between
Each vector data is transferred from the vector register at high speed.
Vector from pipeline operator to ipline operator
Transfer to register, that is, machine cycle
Is known to be the most effective.   FIG. 7 illustrates the outline of the conventional vector processing device.
It is. The vector processor is a fast random access
Vector of VR0 to VR31 configured with process memory (RAM)
The vector register 1 and the output vector
Pipeline operation of data signal 5 by instruction
Switch matrix logic to select and transfer to the device 6
Selector (SEL) 3 and pipeline of 0-3
The output result path 8 of the arithmetic unit 6 is output to the VR0 to VR31
Switch matrix logic selected for cut register 1
Selector (DIST) 2 and VR0 to VR31
Note MS (memory device) 9 for vector data through DIST2
Vector load pipeline 10 and VR0
~ SEL3 the operation result vector data stored in VR31
Output to the main memory (MS) 9 via
It consists of the ipline 11.   Vector data can be loaded from MS9 by a vector load instruction.
Instructed through vector load pipeline 10
It is assigned to the number of vector register 1 and
The vector data supplied at the clock speed of
Addressed and written to RAM in vector element order
It is. Next, the vector data is vectorized by the operation command.
From the register to the operation pipeline 6 as an operand
Read in vector element order. Then calculate by the instruction
The number of vector register 1 that stores the result is assigned
And the vector register indicated by that number is configured.
Written to RAM. Furthermore, the vector operation is the same
It is necessary to repeatedly calculate
High-speed RAM is used for the tor register 1, machine cycle
Operand reading at the clock speed of
It is a structure that can be delivered. This is a vector
If the calculation is performed directly with the MS9, the
The rise time is slow when reading data from large-capacity RAM.
Since it occupies a large amount of the vector calculation processing time,
Iterative processing of vector data of vector operation
Vector Regis as a temporary storage buffer with the advantage
This is the reason why Furthermore, the vector shown in Fig. 7
The torque processor is used for the purpose of improving the machine cycle.
3D mounting structure and DIST to reduce the mounting delay time.
2. Physical logic and RAM such as vector register 1 and SEL3
Divide as much as the constraints allow, and divide the divided logic into semiconductor chips.
And the semiconductor chip is made of ceramic
A method to shorten the signal transmission distance by mounting it on the board of
ing. Vector processing device having such a mounting structure
From Nikkei Electronics December 16, 1985 page 195
Same as page 209 Nikkei Electronics November 19, 1984
No. 237-272. In addition,
The 52521 publication has a vector register for high-speed vectorization.
Disclosed is a vector processing device that executes a le arithmetic operation. Sa
The repetitive arithmetic processing characteristic of vector arithmetic
Is a vector register that stores the vector operation result
Often supplies operands in the processing of the next instruction
No. Therefore, for vector registers with the same logical number,
Read operand data and write operation result
To enable the chaining process to be performed simultaneously,
The RAM that composes the cut-out register has two independent addresses.
Use a bank array that allows
Holds all the even elements of the Tor data, the other bank
It is designed to hold all odd elements of the vector data.
And write to each bank at the clock speed of the machine cycle.
Specially designed vector processing device that enables loading and reading
Japanese Laid-Open Patent Publication No. 61-52121 discloses it.   On the other hand, in the conventional technology of the semiconductor field,
E, Journal of Solid State Sark
T.S.C. 21, 4 (1986), pages 501-504.
(IEEE, JOURNAL OF SOLID STATE CIRCUITS, SC-2
1, 4 (1986), discussed in PP501-504
Address access time such as sub-nanosecond (1ns or less
Ultra-high-speed RAM (below) has also been realized. Also ultra-fast RAM
Random logic is mixed in the semiconductor chip.
To achieve ultra-high-speed operation in a physically closed system
Methods are also generally known. Also, Japanese Patent Laid-Open No. 59-77574
Fast using non-banked vector registers
Is disclosed. [Problems to be solved by the invention]   By the way, in order to realize a super high speed machine cycle,
Physically improved the vector register of 2-bank RAM configuration
It is a module of a closed system and is used in a vector processing device.
You. When implementing the vector processing device, basically
Twice higher to double the capacity of the processing unit
Achieve a fast machine cycle and
Write to and read from vector register at lock speed
It can be understood from the conventional example that the following is realized. However
Improving machine cycles is a physically closed system,
For example, in a semiconductor chip, module, package package
Electrical characteristics that form those substances in the environment
Is limited to the range. That is, the three-dimensional real shown in the conventional example
Mounting structure, a module that mounts a semiconductor chip on a ceramic substrate.
Module as vector processing device module
And vector ultra-fast RAM accessed in sub-nanosecond
When considering effective use as a register,
In the prior art, connectors and pins for mounting connection are electrically connected.
Of the impedance caused by the passage of the signal
Mismatch-induced electrical impairments vary by subnanoseconds
Insufficient logical amplitude for machine cycle
And the problem of malfunction due to noise.
You.   The present invention is effective inside a physically closed system module.
Toll transfer pitch is set to double the machine cycle speed
Signal is passed between the
Machine cycle clocks where dynamic failure is likely to occur
Even if you transfer vector data at a speed,
A vector processing device with the same computing power as
provide. [Means for solving the problem]   The above purpose is the main memory and a plurality of operations for operating the data.
An arithmetic unit module having a controller, the main memory and the
Data is written from the arithmetic unit, and the arithmetic unit operates.
The data to be calculated or the data stored in the main memory is read
A vector register module with RAM to be found
In a vector processing device composed of
The RAM of the register module is the basic machine cycle.
Write and read at twice the clock speed
Odd element RAM bank and even element RAM
The vector register module consists of a bank,
The base input to the vector register module
This machine cycle and the 1/2 cycle phase shift
The two data flows that were
The first pulse output as one data stream at double speed
H conversion circuit and the basic machine cycle and 1/2 phase
Using the shifted basic machine cycle,
The data flow from the switch converter circuit at double speed
Note Odd element RAM bank or even element RAM bank
Address and time to write to the link
Write control circuit for controlling the
Curu and 1/2 phase shifted basic machine cycle
The odd element RAM banks and the even element RAM banks.
From the ment RAM bank, double the basic machine cycle
To read as one data stream of
Readout control circuit for controlling dress and timing
And the odd element RAM bank and
Double speed 1 read from even element RAM bank
Two data streams in the basic machine cycle and mutually
In the two data flows with 1/2 cycle phase shift
And output from the vector register module
2 pitch conversion circuit, wherein the RAM van
, The write control circuit, and the read control
The circuit is constructed in one semiconductor chip, and the first
The H conversion circuit and the second pitch conversion circuit are respectively
It is configured with one semiconductor chip. [Action]   Two vector registers can be independently addressed
It is composed of a bank array that can generate write addresses.
Generate write control signal and read address
Read control signal is 1 / at machine cycle clock speed
By having a phase difference of 2 periods,
Machine cycle for write address and read address
Can be supplied at a clock speed twice as fast as That
Makes vector register twice as fast as machine cycle
It is possible to write and read at clock speed. Also
Machine cycle read from the vector register
Vector data that switches at 2x speed
Trick logic has two machine elements with even and odd elements
Machine cycle clocks that switch at the clock speed of the icicle
That the output changes the 1/2 cycle phase at the clock speed
Output from the module including the vector register
Switch at double speed of machine cycle by passing pin of tool
The electrical safety compared to directly outputting vector data
Does not spoil the stability. Further write to the vector register
Vector data that switches at twice the machine cycle speed
A switch mat provided at the entrance of the vector register
Since it is synthesized by Rix logic, vector register
Electrical on input including pin passing to module containing
Vector data where stability switches at twice the machine cycle speed
Is no less spoiled than typing. 〔Example〕   The overall system configuration of the present invention is schematically shown in FIG.
You. Figure 1 shows the vector register 101 of VR0-VR31 and the
Switch Matrix Logic (DIST) 102 and Switchmat
Rix logic (SEL) 103 and pipeline arithmetic unit 106
And the vector road pipeline 110 and the vector strike
It is divided into an pipeline 111 and an MS (main memory) 109.
Vector register 101 is an even number of vector data
A bank RAM 125 holding elements and B holding odd elements
Write to bank RAM 126 and two bank RAMs
A WA counter 121 that generates a dress
The RA counter 122 that generates the dress and each count
Address generated by the pitch control circuit 127
A bank that distributes at twice the machine cycle pitch
Selector for RAM125 and selector for B-bank RAM126 as well.
Data output from each bank
Pitch control circuit 127 enables double speed machine cycle
Vector selector.
It can hold 128 elements. Vector regis
Data from the write control circuit 112 to the write control signal 113.
Read control signal 116 from the read control circuit 115.
Machine cycle for each vector register 101
Output by changing the 1/2 cycle phase of the clock speed of
And each vector register is instructed by an instruction during operation.
The transistors 101 can be controlled in parallel. In addition,
The vector register 101 will be described later in detail.   DIST102 selects the even element of vector data.
Lectar 118 and selector 119 for selecting odd elements are pipes
Calculation result output paths 108, 108-0, 108 of the line calculator 106
Vector data from -1 and vector load pipeline
Select the vector data stored in MS109 from the
Is configured to. Also selector 118 and selector 1
19 changes the 1/2 cycle phase of the machine cycle clock speed
Each selector will operate in the converted state.
Although not shown in FIG. 1, the vector register 10
Only 1 number, in detail 32 pieces are prepared in parallel operation
It is possible. During operation, the write control circuit 11
2 and the vector register selection signal 114 output from
The pitch indicated by the instruction is selected by the pitch control circuit 120.
Selector 118 and selector 119 corresponding to the toll register 101
Is the machine cycle clock speed and 1/2 cycle phase
Before even and odd elements of vector data with changed
Select half a cycle and OR the output of each selector
The written data is the write data of the vector register 101.
It is output to the path 104. SEL103 is the vector register 101
Driven at double speed of 32 machine cycles output from
The read data path 105
It operates with the relationship that the 1/2 cycle phase of the speed is changed.
Select the even element of the read vector data
Selects the selector 129 and the odd element of the vector data
A selector 130. In addition, selector 129 and selector 13
The group of 0 is not shown in FIG.
Output paths 107, 107-0, 107-1 to the calculator 106 and MS109
Vector space used to store the vector data of
It is also prepared for each tor pipeline 111
Each can operate in parallel. Read by instruction during operation
Vector register selection output from output control circuit 115
Corresponds to the vector register 101 indicated by the instruction with signal 117
Read data path 105 pipeline from instruction
Output to arithmetic unit 106 and vector store pipeline 111
The set of selector 129 and selector 130 corresponding to the path is
Selects the even element of the data
Select an odd element of the
It is driven at the clock rate of the thin cycle. Even number
The element is output to the path 107-0 and the odd element is output to 107-1.
In addition, each functional module such as pipeline arithmetic unit 106
Path of even and odd elements of vector data,
Taking the ipline calculator 3 as an example, the even element input bus 107
-0, odd element input path 107-1, even element output path 108
-0, odd number element output path 108-1 is provided, and each is even
Element paths and odd element paths are machine cycle clock speeds
Are driven by the
It is related to the phase difference of 1/2 cycle of the clock speed of Kuru.   The overall processing outline of the vector processing device shown in FIG.
A vector processing device shown in FIG.
It is the same as No. 114274, so its explanation is omitted. Further vector
The detailed configuration of the register 101 is shown in FIG. 2 and the operation is shown in FIG.
Then, the vector processing device DIST102 shown in FIG.
Vector module consisting of the torque register 101 and SEL103
Figure 3 shows the configuration and operation of the data system of the module (VR module).
6 and will be described later.   FIG. 4 is an implementation configuration of the vector processing device shown in FIG.
It shows the outline of. VR module 201 in Fig. 4
Is DIST102, vector register 101 of VR0-31, SEL103
It is logically composed of DIST10
2, SEL103 is a random logic semiconductor chip, vector
Register 101 is a combination of ultra high speed RAM and random logic
It is composed of a semiconductor chip having a different structure. In addition, VR module
Write control circuit 112 and read control circuit 11
Although 5 is also included, it is not shown in FIG.
Furthermore, the four pipeline arithmetic units 106 are also arithmetic unit modules.
It is composed of multiple semiconductor chips inside the
The computing module 202 and VR module 201 are connected pins.
It is implemented on the vector processing card 200. In addition, Baek
Toll road pipeline 110, vector store pipeline
In 111 and MS109 are mounted on other vector processing cards
However, it is not shown in FIG. 4th
For the vector data path in the figure, the machine cycle
Write data path driven at double clock speed
104 and the read data path 105 are the ones in the VR module 201.
Although the relationship is reasonably closed, the machine cycle
Calculation result output paths driven at lock speed 108, 108-
0, 108-1 and vector data input paths 107, 107-
For 0 and 107-1, the connection pin has passed twice and the vector has passed.
The wiring on the processing card 200 will be transmitted. this
The vector processing device shown in FIG. 1 is shown in FIG.
Double the machine cycle speed by implementing
Vector data signals driven at
Small spatial extent of physically closed space in the module
Limited to location. In addition, the vector data between each module
Input and output of data is 1/2 at clock speed of machine cycle
The related signals with the periodic phase difference will be switched.
And the clock speed is twice as fast as the conventional machine cycle.
One connection pin does not need to be switched every time, impedance
Electrical stability at the connecting pins that results in
You. Vector register   FIG. 2 shows 32 vector registers 101 of VR0 to VR31.
Details of one vector register 101-0
Shown in Also, the operation of the vector register 101-0 in FIG.
FIG. 5 is a timing chart for explanation. (1) Clock   It is input to the vector register 101-0 and is T in FIG.
The 01 clock is T0 clock, which is twice as fast as the machine cycle.
Lock and T1 clock are machine cycle clocks
Each of them has a 1/2 phase difference. (2) Pitch control circuit 127   The pitch control circuit 127 is driven by the T1 clock.
Driven by the clock of the up-flop PIKOE 127-0 and T0
Flip-flop PIKOL127-1 and the two flips
EOR gate 127-2 for exclusive ORing the outputs of flops
And the pitch signal 127-3 output from the EOR gate 127-2.
And flip-flop RDPTCH1 driven by T01 clock
It is composed of 27-4. Input from PIKO signal 144,
A signal with a double cycle of the machine cycle synchronized with the lock
1/2 of machine cycle with flip-flop PIKOL 127-1
Flip-flop PIKOE127-0 with periodic phase difference
By taking the exclusive OR with
Set to "1" at the T0 clock in synchronization with the T01 clock shown in 3.
A signal that becomes "1" at the T1 clock is output. (3) WA counter 121   WA counter 121, which generates the write address of RAM,
Flip-flop WINC121-0 driven by T0 clock
And +1 circuit 121-1 and 6-bit driven by T0 clock
Address register WAC121-2. Also WA
The counter 121 has an address register WAC12 (not shown).
It has a structure that clears 1-2. During operation,
Write control like the signal of WINS121-0 shown in Fig. 5.
The write control signal 113 output from the circuit 112
Address data is counted up and address register WA
WA counter address data 121 set in C121-2
Is output as -3. (4) RA counter 122   The RA counter 122 that generates the RAM read address is
Flip-flop RINC122-0 driven by T1 clock
, +1 circuit 122-1 and 6-bit driven by T1 clock
Address register RAC122-2. Also
Although not shown, the RA counter 122 is an address register RAC.
It has a structure that clears 122-2. in action
Reads like the signal of RINC122-0 shown in FIG.
By the read control signal 116 output from the control circuit 115
The address data is counted up and the address register
RA counter address data set in RAC 122-1
It is output as 122-3. (5) Selector 123   Selector for selecting address data of A bank RAM125
The operation of 123 is the PITCH signal EOR127-3 as shown in FIG.
WA counter address data 121-3 is selected when is "1"
However, when the pitch signal EOR127-3 is “0”, the RA counter is added.
Select the response data 122-3. Furthermore, the output of selector 123
Force is bit A driven by T01 clock
It is input to the register AAD131 and the A bank RAM address
A data signal 131-0 is input to the A bank RAM 125. (6) Selector 124   Selector for selecting address data of B bank RAM126
The operation of the pitch signal EOR127- is as shown in FIG.
WA counter address data 121-3 is selected when 3 is "0".
When the pitch signal EOR127-3 is “1”, the RA counter
Select the dress data 122-3. Further selector 124
The output is a 6-bit B bank address driven by the T01 clock.
B bank RAM address input to the dress register BAD132
Data signal 132-0 is input to B bank RAM 126
You. (7) Write data   The write data is input from the write data path 104.
Input to register WTDATA133 driven by T01 clock
Is done. In addition, DI path 1 which is the output of register WTDATA133
Input to A bank RAM 125 and B bank RAM 126 through 33-0
Is done. (8) WE control circuit   The WE control circuit is provided in each of the vector registers 101
And the write control circuit 112
Control each vector register 101 to operate in parallel.
It is controlled. WE control circuit is driven by T0 clock
It is driven by the flip-flop WEF134 and the T1 clock.
Flip-flop WES135, selector 136, selector
Connector 137 and a bank of A bank RAM driven by T01 clock.
Mode flip-flop WTMDA138 and B bank RA
M write mode flip-flop WTMDB139 and T01
Delay the rising edge of the clock and set the RAM write
Of the RAMWE
Write to adjust the pulse width and write hold time
The pulse generator 140 and its respective write mode and light
AND pulse AND the output pulse of pulse generator 140
It consists of 141, 142. Shown in Figure 5 during operation
When the pitch signal EOR127-3 is “1”, the selector
136 selects the output of flip-flop WEF134 and pitches
When the signal is “0”, the selector 137 turns the flip-flop WES
Select 135 outputs. That is, during operation all vector data
Writing to the A bank RAM 125 which is held in the even elements of the data
Write control signal 113-0 is output to the
Writing to B bank RAM 126 that holds odd elements of data
Then, the write control signal 113-1 is output to. (9) Read data   During operation, the selector 128 sets the A bank address register A
When AD131 is read address data, A bank RAM125
Data output 125-0 of B bank address register BAD
When 132 is read address data, B bank RAM 126
Of the pitch control circuit 127 to select the data output 126-0.
The output signal 127-5 of the flip-flop RDPTCH127-4 swings.
Divided. Furthermore, the output of the selector 128 is the T01 clock
Read through data register RDDATA143 driven by
And output to the data path 105. (10) Register RAM   Two ultra high-speed RAMs with the same address and data value
It is arranged so that it represents the Toru data element. All vector de
A bank RAM 125 that holds the even elements of the data
Address register AAD131 output 131-0 for addressing
Is In addition, B that holds an odd number of vector data elements
The bank RAM126 is the output of the B bank address register BAD132.
Addressed with force 132-0.   Next, the entire vector register 101-0 shown in FIG.
The outline of the operation will be described with reference to FIG. Figure 5 is vector
Writing vector data to the register 101-0
Represents the chaining process in which read and read are performed simultaneously.
I do. The number of vector data elements is 6, and
E in order₀, E₁, E_Two, E_Three, E_Four, E_FiveAnd Write first
Is time t₀WA counter 121 flip-flop WINC121−
The clear signal W0 of the WA counter 121 is issued to 0. W0 is
The selector 123 selects the pitch signal EOR127-3 while it is "7".
So t₀−t₁Becomes the time width of
Input to the AAD131 register, and the output is t₁Time to t_TwoUp to time
The address AW0 is applied to the A bank RAM 125. Further
At time t₀Flip flow to write to bank RAM125
Write signal WT0 is input to WEF134 and selector 136
Since EOR127-3 is selected during "1", t₀−t₁Time span
Is input to the flip-flop WTMDA138. Further
At the output of the flip-flop WTMDA138, WT0 is₁Or
Time t_TwoValid until AND Write pulse with AND gate 141
AND with the output pulse of the generator 140, and₁−t_TwoBetween A
Applied as WE of bank RAM125. Write more
Cutle data e₀Is time t₁Input to register WTDATA133
And the output is t₁−t_TwoIt becomes effective in the time width of. I.e.
E, which is the first of the even elements of the Tor data₀Is time t₁−t_TwoBetween
Is written to the A bank RAM 125. Next, on the B bank side
However, W0 is selected by the selector 124 while EOR127-3 is “0”.
Selected, t₁−t_TwoIt becomes the time width of B bank address
Input to register BAD132 and output is t_TwoTime to t_Threetime
Is applied to the B bank RAM 126 as the address BW0.
Further time t₁As writing to B bank RAM126
The write signal WT1 is input to the program WES135,
Since the EOR127-3 is selected during “0” by the Kuta 137, t₁−t
_TwoInput to flip-flop WTMDB139.
It is. In addition, the output of flip-flop WTMDB139 is WT1
Is time t_TwoFrom time t_ThreeValid until AND gate 142
AND pulse generator 140 output pulse and AND time t_Two
−t_ThreeDuring this period, it is applied as WE of B bank RAM 126. further
Write vector data e₁Is time t_TwoRegister WTDATA13
Input to 3 and output is t_Two−t_ThreeIt becomes effective in the time width of. Yo
Is the beginning of the vector data odd element e₁Is time t_Two−
t_ThreeIs written in the B bank RAM 126 during the period. And so on
Vector data e_Two, E_Three, E_Four, E_FiveAgainst WA coun
To the flip-flop WNC121-0 of the data counter 121 WA counter 121
The count-up signals W1 and W2 of
Link RAM 125 addresses AW1 and AW2 and B bank RAM 126 address
Dresses BW1 and BW2. Also e_Two, E_Three, E_Four, E_FiveWrite
WE for WT2, WT3, WT4, WT5_Two, E_Three, E_Four, E_Five
E_nAnd WT2, WT3, WT4, WT5 are WTn, e_nThe Regis
The time input to WTDATA133 is t_nIs expressed as
Flip-flop WEF134 (n = 2, 4) and flip-flop
The time to input to rop WES135 (n = 3, 5) is t_n-1 and
If you do e_Two, E_Three, E_Four, E_FiveCan be written.   On the other hand, vector data e₀, E₁, E_Two, E_Three, E_Four, E_FiveReading
Time is t₁RA counter 122 flip-flop RINC1
The clear signal R0 of the RA counter 122 is issued to 22-0.
The R0 is selected by the selector 123 while EOR127-3 is "0".
Time t₁−t_TwoIs valid during
Input to the AAD131 register, and the output is t_TwoFrom t_ThreeAdd up to time
It becomes a response AR0 and is applied to the A bank RAM125. further
When the output of the flip-flop RDPTCH127-4 is “0”,
Lector 128 selects data output 125-0 of A bank RAM 125
So t_Two−t_ThreeIs being applied to A bank RAM125 for
Vector data e corresponding to the address AR0₀Is output
Input to register RDDATA143, t_ThreeTime to t_Fourtime
During this period, the data is output to the read data path 105. Then B van
The R0 is the selector 124 and the EOR127-3 is
Since it is selected during “1”, time t_Two−t_ThreeIs valid for
Input to B bank address register BAD132 and output is t_ThreeTime
From t_FourAddress BR0 until time B bank RAM126
Is applied to Further flip-flop RDPTCH127-4
When the output of "1" is "1", the selector 128 is
Since data output 126-0 is selected, t_Three−t_FourTime B van
Vector corresponding to address BR0 applied to RAM 126
Torudata e₁Is output and input to the register RDDATA143.
And t_FourTime to t_FiveAppears on read data path 105 for a period of time
Is forced. Similarly, vector data e_Two, E_Three, E_Four, E_FiveTo
RA counter 122 flip-flop RINC1 to read
22-0 Count up signals R1 and R2 of RA counter 122
Addresses AR1 and AR2 of A bank RAM125 respectively
And addresses B1 and BR2 of B bank RAM126, as shown in FIG.
Read through the data register RDDATA143 as shown in
It is output to the data path 105. Therefore, the
The cuttle register 101-0 is a machine speed double speed machine cycle.
Switch allows vector data to be written and read at the same time
Noh. VR module   Figure 3 is a schematic diagram of the data structure of the VR module.
You. The tie of FIG. 6 is used to explain the operation of FIG.
It is a mining chart. Figure 3 shows DIST102, vector
The VR model shown in Fig. 4 that consists of the transistor 101 and SEL103.
It is Jules. DIST102 is as described above, but details
The pitch control circuit 120 is connected to the vector register 101-0.
It is similar to the switch control circuit and is driven by the T1 clock.
Driven by flip-flop DPIKOE120-0 and T0 clock
Flip-flop DPIKOL120-1 and the two flip-flops
EOR gate 120 for exclusive ORing the outputs of the lip flops
-2, the pitch signal 120- which is the output of the EOR gate 120-2
3 and the operation is similar to that of the pitch control circuit 127.
You. Also, in detail, select even elements of vector data.
The register 118 input is a register driven by the T0 clock.
Data 145, 146 and the odd elements of the vector data
The register that is driven by the T1 clock is also input to the selector 119.
Stars 147 and 148 are provided. For more details,
The output of the pair of connectors 118 and 119 is an OR gate 149.
On the other hand, SEL103 also selects even elements of vector data in detail.
The register driven by the T0 clock is output to the selector 129.
Star 150 and select odd elements of the vector data
Register 1 driven by T1 clock at the output of selector 130
51 is provided. Particularly in FIG. 3, the explanation of FIG.
Due to the relation, the arithmetic result of the pipeline arithmetic unit 106 of DIST102 is even
Set the register of element output path 108-0 to DA3F145,
As a result, set the odd-numbered element output path 108-1 register to DA3S147.
And even-numbered element path to pipeline arithmetic unit 3106 of SEL103
Set the register of 107-0 to SA3F150, the odd element path 107-1
Register as SA3S151, and other registers and paths
This is not shown in detail. Shown in Figure 3 above
The vector register for the VR module 201 with a different configuration
Vector data e explained in the section of operation of data 101-1₀,
e₁, E_Two, E_Three, E_Four, E_FiveBetween the pipeline arithmetic unit 106
Timing chart showing how chaining is being performed
FIG. 6 is a chart. Figure 6 shows the pipeline arithmetic unit 10
Even element e which is the first vector data from 6₀Has pass 108
-0 to t₀It is input to the register DA3F145 at time and e₀Is t₀
−t_TwoIs valid for the time and is input to the selector 118. Also
The selector 118 is a register when the pitch signal 120-3 is "1".
Select the DA3F145 output.₀Is t₀−t₁In the time span of
It becomes valid and is output to the OR gate 149. Meanwhile, the vector
E, which is the first of the odd elements of the data₁From bus 108-1 to t₁
It is input to the register DA3S147 at time and e₁Is t₁−t_Threetime of
It becomes valid and is input to the selector 119. Further selector 1
19 also when the pitch signal 120-3 is "0", register DA3S147
Select the output, e₁Is t₁−t_TwoValid in the time range of
Output to the OR gate 149. And so on_Two, E_Three,
e_Four, E_FiveThe same procedure is repeated for the machine cycle.
The vector data sent to the VR module 201 at
The even and odd elements of the data are double the speed of the machine cycle.
Switch to the vector data sequence that is switched by the switch.
It is input to the register WTDATA133 of the register 101. In addition,
Actor 118 and selector 119 are not shown or described in FIG.
However, the instruction selects VR0 of vector register 101.
It is assumed that a tuple is used. Then vector data
e₀, E₁, E_Two, E_Three, E_Four, E_FiveAre stored in the vector register 101.
It is held and read, but the details are the vector
It is shown in the section for explaining the operation of the register 101-0.   By the way, the vector output from the register RDDATA143
Data e₀, E₁, E_Two, E_Three, E_Four, E_Five2 of the machine cycle
Although it is switching at a double speed pitch, the cash register of SEL103
The SA3F150 and SA3S151 are T0 clock and T1 clock respectively.
Since it is driven by the clock, the vector as shown in Fig. 6
The data is a vector of even elements that is switched at the machine cycle pitch.
Path 107 as the vector data of the toll data and the odd element
-1 from 0 and 107-1 at machine cycle clock speed
/ 2 Period Output with a phase difference. Therefore, in FIG.
According to the logical configuration of DIST102 and SEL103 shown in the figure,
Then, the vector register 101-0 shown in FIG.
Small spatial extent of physically closed space in module 201
Use in place and switch at double speed pitch of machine cycle
Limit the vector data signal to the VR module 201.
Can be. Also, the electrical stability inside the VR module can be obtained.
One book for each vector register in a small space
Can be embedded data path and one read data path
With this, the amount of hardware in the VR module can also be reduced. further
Signal input from VR module 201 to vector processing card
Output also has a 1/2 cycle phase difference at the machine cycle clock speed
Because of the presence of electrical noise due to simultaneous switching of signals
On the other hand, there is an advantage that stability can be obtained. 〔The invention's effect〕   According to the present invention, the switching speed is twice as fast as the machine cycle.
Confine the cuttle data signal to a physically restricted location
There is an effect that can be. The vector register of the present invention
Data processing is twice as fast as a machine cycle
You.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the overall system configuration of the present invention, FIG. 2 is a diagram showing the detailed configuration of the vector register of FIG. 1, and FIG. 3 is a data system configuration of a VR module. Showing the figure,
FIG. 4 is a diagram showing the mounting structure of the vector processing device, FIG. 5 is a timing chart for explaining the operation of the vector register, FIG. 6 is a timing chart for explaining the data system operation of the VR module, and FIG. 7 is a conventional example. FIG. 101 to 101-0 ... vector register, 102 ... DIST, 103
…… SEL, 106 …… Pipeline arithmetic unit, 109 …… MS, 110
…… Vector load pipeline, 111 …… Vector store pipeline, 112 …… Write control circuit, 115 ……
Read-out control circuit, 118-119 ... Selector, 120 ... Pitch control circuit, 121-121-3 ... WA counter, 122-122
-3 ... RA counter, 123-124 ... selector, 125 ...
A bank RAM, 126 ...... B bank RAM, 127-127-4 ...
Pitch control circuit, 128 selector, 131 A bank address register AAD, 132 B bank address register
BAD, 133 ... data register WTDATA, 134 to 142 ... WE control circuit, 143 ... data register RDDATA, 200 ... vector processing card, 201 ... VR module, 202 ... computing module.

Claims (1)

(57) [Claims] A main memory, a calculator module having a plurality of calculators for calculating data, data written from the main memory and the calculator, and data stored in the main memory or calculated by the calculator Is read
In a vector processing device including a vector register module having a RAM, the RAM of the vector register module can be written and read at a clock speed twice as fast as a basic machine cycle. The vector register module is composed of a RAM bank, and the vector register module outputs two data flows which are input to the vector register module and which are out of phase with each other by ½ cycle in the basic machine cycle, at a speed twice that of the basic machine cycle. Using the first pitch conversion circuit for outputting as one data flow and the basic machine cycle and the basic machine cycle with the 1/2 phase shifted, one double speed data from the first pitch conversion circuit Of the odd element RAM bank or even From the odd element RAM bank and the even element RAM bank, using a write control circuit for controlling a write address and timing for writing to the element RAM bank, and using the basic machine cycle and the basic machine cycle shifted by 1/2 phase, A read control circuit for controlling a read address and a timing for reading as one data stream of the double speed of the basic machine cycle; and a double speed of 1 read from the odd element RAM bank and the even element RAM bank. And a second pitch conversion circuit for outputting from the vector register module as two data streams in the basic machine cycle and having phase shifts of 1/2 cycle with respect to each other. RAM bank, write system A circuit and the read control circuit are formed in one semiconductor chip, and the first pitch conversion circuit and the second pitch conversion circuit are respectively formed in one semiconductor chip. .