JP2671827B2 - Hermetically sealed semiconductor device - Google Patents

Hermetically sealed semiconductor device

Info

Publication number
JP2671827B2
JP2671827B2 JP6265593A JP26559394A JP2671827B2 JP 2671827 B2 JP2671827 B2 JP 2671827B2 JP 6265593 A JP6265593 A JP 6265593A JP 26559394 A JP26559394 A JP 26559394A JP 2671827 B2 JP2671827 B2 JP 2671827B2
Authority
JP
Japan
Prior art keywords
wiring
wiring board
semiconductor device
opening
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP6265593A
Other languages
Japanese (ja)
Other versions
JPH08125065A (en
Inventor
正則 竹内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP6265593A priority Critical patent/JP2671827B2/en
Publication of JPH08125065A publication Critical patent/JPH08125065A/en
Application granted granted Critical
Publication of JP2671827B2 publication Critical patent/JP2671827B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、気密封止型半導体装置
に係わり、特に半導体チップの大きさ（サイズ）が異る
場合でも使用するパッケージを共通化して低廉化を図り
うる気密封止型半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hermetically sealed semiconductor device, and in particular, a hermetically sealed semiconductor device which can be used at a low cost by using a common package even when semiconductor chips have different sizes. The present invention relates to a semiconductor device.

【０００２】[0002]

【従来の技術】通常、半導体チップをパッケージのキャ
ビティに収容する気密封止型半導体装置は、搭載する半
導体チップのサイズ毎に専用のパッケージを用意する必
要があった。この種のパッケージの共通化を図る手段の
一例が、特開昭５７−１１２０５７号公報に記載されて
いる。同公報記載の半導体装置を本発明に対応させて平
面図およびその線Ｇ−Ｇ′における断面図を示した図４
（ａ）を参照すると、この半導体装置は、プレス加工さ
れたグリーンシート片を積層したパッケージ２９の矩形
状キャビティ内に半導体チップ１を搭載して構成され
る。半導体チップ１はキャビティの底面のステージパタ
ーン上にろう付けされているＭｏ製の支持板２１の上面
にろう付けされて搭載されている。2. Description of the Related Art Normally, in a hermetically sealed semiconductor device in which a semiconductor chip is housed in a cavity of a package, it is necessary to prepare a dedicated package for each size of the mounted semiconductor chip. Japanese Patent Laid-Open No. 57-112057 discloses an example of means for making this type of package common. FIG. 4 is a plan view showing the semiconductor device disclosed in the publication and a cross-sectional view taken along the line GG ′ in accordance with the present invention.
Referring to (a), this semiconductor device is configured by mounting the semiconductor chip 1 in a rectangular cavity of a package 29 in which pressed green sheet pieces are stacked. The semiconductor chip 1 is brazed and mounted on the upper surface of a Mo-made support plate 21 which is brazed on the stage pattern on the bottom surface of the cavity.

【０００３】さらに、半導体チップ１を囲んでろう付け
層２２を介して支持板２１上に接着されたセラミック製
の枠状の配線中継部材２３がキャビティ内に配設される
とともに、配線中継部材２３および支持板２１にはスル
ーホール２４および２５が設けられろう付け層２２を介
してパッケージの接地用リードピン（不図示）に接続さ
れている。Further, a ceramic frame-shaped wiring relay member 23, which surrounds the semiconductor chip 1 and is bonded to the support plate 21 via a brazing layer 22, is provided in the cavity, and at the same time, the wiring relay member 23. Also, through holes 24 and 25 are provided in the support plate 21 and are connected to the grounding lead pin (not shown) of the package through the brazing layer 22.

【０００４】この構成においては、スルーホール２４お
よび２５のパス長は短くなり半導体チップ１の特性を不
要に低下させず、また、配線中継部材２３は半導体チッ
プ１のサイズ毎に予め用意されるものであり、配線の中
継点としての役目をし、ワイヤの長さは従来の専用パッ
ケージを用いた場合と同程度に短かいので雑音の悪影響
を受けないようにしている。In this structure, the path lengths of the through holes 24 and 25 are shortened so that the characteristics of the semiconductor chip 1 are not unnecessarily deteriorated, and the wiring relay member 23 is prepared in advance for each size of the semiconductor chip 1. Therefore, it serves as a relay point of the wiring, and the length of the wire is as short as that in the case of using the conventional dedicated package, so that it is prevented from being adversely affected by noise.

【０００５】上述した一例の変形例の平面図およびその
切断線Ｈ−Ｈ′における断面図を示した図４（ｂ）を参
照すると、この半導体装置は、支持板２１自体が配線中
継部材の役目を兼ねたものである。すなわち、支持板２
１の上面の周囲部にはボンディングパッド２６が複数披
着形成されている。半導体チップ１はセラミック製の支
持板２１の中央部に搭載される。信号用ワイヤ８は半導
体チップ１上のパッド２と支持板２１上のパッド２６と
パッケージ内の開孔部段上のパッド２７とを接続する。
アース用ワイヤ２８は半導体チップ１のパッドと支持板
２１上のパッドとスルーホール１２を介して所定のリー
ドピン９に続続される。Referring to FIG. 4 (b) showing a plan view of the above-described modified example and a sectional view taken along the section line H-H ', in this semiconductor device, the support plate 21 itself serves as a wiring relay member. It also serves as. That is, the support plate 2
A plurality of bonding pads 26 are formed on the periphery of the upper surface of 1. The semiconductor chip 1 is mounted on the central portion of a ceramic support plate 21. The signal wire 8 connects the pad 2 on the semiconductor chip 1, the pad 26 on the support plate 21, and the pad 27 on the stage of the opening in the package.
The ground wire 28 is connected to a predetermined lead pin 9 through the pad of the semiconductor chip 1, the pad on the support plate 21, and the through hole 12.

【０００６】この例の場合は、中継部材２３が不要であ
り部品点数が少なくてすむ。In the case of this example, the relay member 23 is unnecessary and the number of parts can be reduced.

【０００７】また、この種の従来の半導体装置において
は、電源線に雑音除去用の積層セラミックコンデンサを
接続する場合は、パッケージ外部に設けられた電極に半
田接合する構成が一般的であった。In addition, in the conventional semiconductor device of this type, when a noise eliminating multilayer ceramic capacitor is connected to a power supply line, it is generally configured to be soldered to an electrode provided outside the package.

【０００８】[0008]

【発明が解決しようとする課題】多種類の異なる大きさ
の半導体チップを１つのパッケージに搭載する場合、従
来技術の一例で述べたように、半導体チップより大き
く、かつキャビティ底面より小さい配線中継部材が必要
である。またその変形例の場合は中継部材を省略してい
るが、それに代る配線用電極を配設するための支持板の
大きさが必要となる。この為、パッケージが共通化前よ
り大型化し、半導体装置の小型化と矛盾するだけでな
く、共通化前よりもパッケージが高価になる。When mounting various types of semiconductor chips of different sizes in one package, a wiring relay member larger than the semiconductor chip and smaller than the bottom surface of the cavity is used as described in the example of the prior art. is required. Further, in the case of the modified example, the relay member is omitted, but the size of the support plate for disposing the wiring electrode instead of the relay member is required. For this reason, the package becomes larger than that before commonization, which conflicts with the miniaturization of the semiconductor device, and the package becomes more expensive than before commonization.

【０００９】また通常、積層セラミックコンデンサがパ
ッケージ外部に搭載されている半導体装置の場合、この
コンデンサに接触したり、脱落しないように組立工程上
の取扱いに注意を要し、コンデンサを搭載していない半
導体装置に比べて作業性が悪くなっていた。加えて、コ
ンデンサは電源及びグランドのノイズ低減の観点から、
できるだけ半導体チップ近傍に配設した方が効果的であ
ることが知られており、この意味から半導体チップを収
容するキャビティ内にコンデンサを配設することが望ま
しい。Also, in the case of a semiconductor device in which a monolithic ceramic capacitor is mounted on the outside of the package, it is usually necessary to take care in the assembly process so as not to contact or drop the capacitor, and the capacitor is not mounted. Workability was worse than that of semiconductor devices. In addition, the capacitor is
It is known that it is more effective to dispose the semiconductor chip in the vicinity of the semiconductor chip as much as possible, and in this sense, it is desirable to dispose the capacitor in the cavity that accommodates the semiconductor chip.

【００１０】しかしながら、従来技術ではキャビティを
広げ、全体としてパッケージを大きくする必要があり、
半導体装置の小型化にとって不利となるだけでなく、共
通化前よりもパッケージ単価が高価になる。However, in the prior art, it is necessary to widen the cavity and enlarge the package as a whole,
Not only is it disadvantageous in reducing the size of the semiconductor device, but the unit price of the package is higher than that before the standardization.

【００１１】また、共通化によって収容される全ての半
導体チップがコンデンサを必要とするとは限らず、これ
も共通化を制限していた。Further, not all semiconductor chips accommodated by the common use need capacitors, and this also limits the common use.

【００１２】上述した理由から、大きくサイズの異なる
半導体チップの搭載は、コスト的にもパッケージサイズ
的にも不利であり、大きくサイズの異なる半導体チップ
を搭載するパッケージが開発されず、パッケージの共通
化によるパッケージの底廉化が図れなかった。また、積
層セラミックコンデンサをキャビティ内に搭載すること
による作業性の向上も図れなかった。For the reasons described above, mounting semiconductor chips of large and different sizes is disadvantageous in terms of cost and package size, and packages for mounting semiconductor chips of large and different sizes have not been developed. It was not possible to reduce the price of the package. Further, the workability could not be improved by mounting the monolithic ceramic capacitor in the cavity.

【００１３】本発明の目的は、上述した課題に鑑みなさ
れたものであり、大きくサイズの異なる半導体チップを
搭載できる気密封止型半導体のパッケージおよびこのパ
ッケージに半導体チップを搭載した気密封止型半導体装
置およびパッケージ内に積層セラミックコンデンサを搭
載した気密封止型半導体装置を提供することにある。The object of the present invention is made in view of the above-mentioned problems, and a hermetically sealed semiconductor package in which semiconductor chips of different sizes can be mounted and a hermetically sealed semiconductor in which the semiconductor chip is mounted in this package. An object of the present invention is to provide a hermetically sealed semiconductor device in which a laminated ceramic capacitor is mounted in the device and the package.

【００１４】[0014]

【課題を解決するための手段】本発明の気密封止型半導
体装置の特徴は、大きさの異なる半導体チップがそれぞ
れ共通に搭載されうる底部表面積と深さとをもち第１の
電極群が周縁部に配設された第１開孔部と、この開孔部
の前記周縁部を囲みかつ前記第１開孔部よりも大きい第
２開孔部とをもち、前記第１および前記第２開孔部間に
配線基板上面が前記第２開口部底面と略同一平面上に位
置するようにかつ前記配線基板の外周部を接着して支持
する段差部が設けられたキャビティを有する気密封止型
半導体装置において、前記配線基板が前記底部表面積よ
りも大きい少なくとも３層からなる多層配線基板であっ
てその下面に配設された第２の電極群および前記半導体
チップの素子形成面に形成された電極群のそれぞれを互
いに電気的に接続するように搭載され、かつ前記半導体
チップの下面が前記第１開孔部底部に接着されるととも
に、前記第２の電極群に接続される配線と前記多層配線
層のうちの内部層の 配線と前記多層配線基板上面に配設
された第３の電極群とがそれぞれスルーホールを介して
接続され、これら第３の電極群が金属細線によって前記
段差部よりも外側でかつ略同一平面上にある前記第１の
電極群に段差をつけずにそれぞれ接続されることにあ
る。The hermetically sealed semiconductor device of the present invention is characterized in that it has a bottom surface area and a depth at which semiconductor chips of different sizes can be mounted in common, and the first electrode group has a peripheral portion. a first opening disposed, surrounds the periphery of the opening and has a second opening larger than the first opening, said first and said second opening Between departments
The top surface of the wiring board should be substantially flush with the bottom surface of the second opening.
And the outer peripheral part of the wiring board is adhered and supported
In a hermetically sealed semiconductor device having a cavity provided with a step portion , the wiring substrate is larger than the bottom surface area.
It is a multilayer wiring board consisting of at least 3 layers
Second electrode group disposed on the lower surface of the lever and the semiconductor
Each of the electrode groups formed on the element formation surface of the chip is
The semiconductor is mounted so that it is electrically connected to the
When the lower surface of the chip is adhered to the bottom of the first opening,
A wiring connected to the second electrode group and the multilayer wiring
Arranged on the inner layer wiring of the layers and the upper surface of the multilayer wiring board
Through the through holes, respectively.
The third electrode group is connected by a thin metal wire.
The first outside of the step portion and substantially on the same plane
The purpose is to connect the electrode groups without making a step .

【００１５】また、前記多層配線基板は、前記半導体チ
ップの電源配線および接地配線間に挿入される積層セラ
ミックコンデンサ接続用の第４の電極群を前記上面に備
えることができる。Further, the multi-layer wiring board has the semiconductor chip.
Layered ceramic that is inserted between the power and ground wiring
A fourth electrode group for connecting the Mic capacitor is provided on the upper surface.
Can be obtained .

【００１６】さらに、前記多層配線基板の内部層の配線
層が、電源配線層および接地配線層のうち一方、または
両方の配線層を備えることもできる。Furthermore, the wiring of the inner layer of the multilayer wiring board
The layer may include one or both of a power wiring layer and a ground wiring layer.

【００１７】[0017]

【実施例】本発明の気密封止型半導体装置を図面を参照
しながら説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A hermetically sealed semiconductor device of the present invention will be described with reference to the drawings.

【００１８】図１（ａ）は本発明の第１の実施例を説明
するために封止用キャップを取り除いた気密封止型半導
体装置の平面図、同図（ｂ）は図１（ａ）図の線Ａ−
Ａ′における断面図および同図（ｃ）は図１（ｂ）の線
Ｂで囲まれた部分の拡大図である。FIG. 1A is a plan view of a hermetically sealed semiconductor device in which a sealing cap is removed to explain the first embodiment of the present invention, and FIG. 1B is FIG. 1A. Line A- in the figure
A sectional view taken along line A'and FIG. 1C are enlarged views of a portion surrounded by a line B in FIG. 1B.

【００１９】図１（ａ）〜（ｂ）を参照すると、この機
密封止型半導体装置は、サイズの異なる半導体チップ１
を個別に搭載出来る大きさの底部表面積と深さとをも
ち、第１のボンディング用電極７が周縁部に複数配設さ
れた第１開孔部１３と、この開孔部１３の周縁部を囲み
かつ第１開孔部１３よりも大きい第２開孔部１４とをも
ったキャビティを有し、底部表面積よりも大きい配線基
板５が半導体チップ１の素子形成面に半田３で接着され
て搭載され、かつ半導体チップ１の下面が底部に接着さ
れるとともに、配線基板５を樹脂６で接着して支持する
段差部１５が開孔部１３および１４間に設けられてい
る。Referring to FIGS. 1A and 1B, the security-sealed semiconductor device includes semiconductor chips 1 of different sizes.
A first opening portion 13 having a bottom surface area and a depth that can be individually mounted, and a plurality of first bonding electrodes 7 are provided in the peripheral portion, and the peripheral portion of the opening portion 13 is surrounded. A wiring board 5 having a cavity having a second opening portion 14 larger than the first opening portion 13 and having a surface area larger than the bottom surface area is mounted on the element formation surface of the semiconductor chip 1 by being bonded with solder 3. and the lower surface of the semiconductor chip 1 while being adhered to the bottom, the step portion 15 of the wiring board 5 is supported by bonding with resin 6 is provided between the opening portion 13 and 14.

【００２０】配線基板５の電気的接続は、この配線基板
５の下面に配設された接続用電極１０が半導体チップ１
の電極２とそれぞれダイボンディングされ、電極２に接
続される配線が半田３と接続用電極１０とを介して配線
パターン１１に接続される。The wiring electrically connecting the substrate 5, the semiconductor chip 1 is connected electrode 10 disposed under surface of the wiring board 5
The wires that are respectively die-bonded to the electrodes 2 and are connected to the electrodes 2 are connected to the wiring pattern 11 via the solder 3 and the connecting electrodes 10.

【００２１】さらにスルーホール１２を介して配線基板
上面に配設された接続用電極４に接続され、これら接続
用電極４が金属細線８によってボンディング用電極７に
それぞれ接続され、外部リード９に接続されている。Further, a wiring board is provided through the through holes 12.
Is connected to the connection electrode 4 disposed in the upper surface, these connecting electrodes 4 are respectively connected to the bonding electrode 7 by metal thin wires 8 are connected to the external lead 9.

【００２２】この機密封止型半導体装置は、以下の工程
を経て製造される。すなわち、This security sealed semiconductor device is manufactured through the following steps. That is,

【００２３】イ．半導体チップ１内部にあるパッド２上
に半田３を付け、半導体チップと対向する配線基板下面
に、パッド２と接合するための接続用電極１０及び配線
パターン１１を形成し、配線基板上面にパッケージの外
部リード９との接続用電極４を形成した配線基板５を乗
せ、かつ配線基板５と半導体チップ１とが半田３により
接着固定される。A. With the solder 3 on the pad 2 in the semiconductor chip 1, the semiconductor chip facing to the wiring substrate under surface, forming a connection electrode 10 and the wiring pattern 11 for connecting a pad 2, the package on the wiring board top surface The wiring board 5 on which the connection electrode 4 for connecting to the external lead 9 is formed is placed, and the wiring board 5 and the semiconductor chip 1 are bonded and fixed by the solder 3.

【００２４】ロ．半導体チップ１は、Ａｇペースト等の
熱硬化性樹脂６によってキャビティ底面に接着固定さ
れ、配線基板５はパッケージに配設されたボンディング
用電極７との平行が保たれるように、配線基板５の周縁
部がキャビティ内に設けられた段差部に接着固定され
る。B. The semiconductor chip 1 is adhered and fixed to the bottom surface of the cavity by a thermosetting resin 6 such as Ag paste, and the wiring board 5 is kept in parallel with the bonding electrodes 7 arranged in the package. The peripheral portion is adhesively fixed to the stepped portion provided in the cavity.

【００２５】ハ．配線基板５上面に設けられた接続電極
４とパッケージ側にあるボンディング用電極７とが金属
細線８により接続される。C. The connection electrode 4 provided on the upper surface of the wiring board 5 and the bonding electrode 7 on the package side are connected by a thin metal wire 8.

【００２６】ニ．パッケージに封止用キャップを取り付
け、気密封止する。D. A sealing cap is attached to the package and hermetically sealed.

【００２７】本実施例によれば、キャビティ内の半導体
チップ１の素子形成面に配線用基板５を搭載すること
で、従来は周辺部に接続電極群が配設された支持板（本
実施例における配線基板に相当）をキャビティ底面に搭
載するためにこの支持板に対応した広い面積のキャビテ
ィが必要であった場合に比べて、大きさの異なる複数種
類の半導体チップを直接底面に搭載することが出来るよ
うに半導体チップの大きさに対応した最小限の広さの底
面をもつキャビティと、その底面の大きさに合わせて配
線基板５の大きさも段差部１５で支持させることが可能
な最小限の大きさであればよいので、パッケージの共通
化によるパッケージの大型化を防ぐことができ、より一
層のパッケージの共通化が図れ、それによってより一層
のパッケージの低廉化も図れる。According to the present embodiment, by mounting the wiring substrate 5 on the element forming surface of the semiconductor chip 1 in the cavity, conventionally, the supporting plate having the connection electrode group arranged in the peripheral portion (the present embodiment (Corresponding to the wiring board in) is mounted on the bottom surface of the cavity, compared to the case where a cavity with a large area corresponding to this support plate is required to mount the semiconductor chips of different sizes directly on the bottom surface. Cavity having a minimum bottom surface corresponding to the size of the semiconductor chip so that the size of the wiring board 5 can be supported by the step portion 15 according to the size of the bottom surface. Since the size of the package can be any size, it is possible to prevent the size of the package from increasing due to the standardization of the package, and it is possible to further standardize the package, which further reduces the cost of the package. It attained as well.

【００２８】次に、本発明の第２の実施例を説明する。Next, a second embodiment of the present invention will be described.

【００２９】封止用キャップを取り除いた半導体装置の
平面図を示した図２（ａ）、図２（ａ）の線Ｃ−Ｃ′に
おける断面図を示した図２（ｂ）および図２（ｂ）の線
Ｄで囲まれた部分の拡大図を示した図２（ｃ）を参照す
ると、第１の実施例との相違点は、半導体チップ１と半
田３によって接続される配線基板５には、配線基板上面
に積層セラミックコンデンサ１６を接続するための積層
セラミックコンデンサ用電極１７を有していることであ
る。それ以外の構成要素は同一であるからここでの構成
の説明は省略する。2A showing a plan view of the semiconductor device from which the sealing cap has been removed, and FIGS. 2B and 2B showing a cross-sectional view taken along the line CC 'of FIG. 2A. Referring to FIG. 2C, which is an enlarged view of the portion surrounded by the line D in FIG. 2B), the difference from the first embodiment is that the wiring board 5 connected by the semiconductor chip 1 and the solder 3 is different. Is to have a laminated ceramic capacitor electrode 17 for connecting the laminated ceramic capacitor 16 on the upper surface of the wiring board . Since the other components are the same, the description of the configuration here is omitted.

【００３０】この積層セラミックコンデンサ用電極１７
上に積層セラミックコンデンサ１６を半導体チップ１の
搭載と同じ工程で半田３により接続する。すなわち、半
導体チップ１内部にある電極２上に半田３を付け、半導
体チップ１と対向する配線基板下面に、電極２と接合す
るための接続用電極１０と配線パターン１１とを形成
し、配線基板上面にパッケージの外部リード９との接続
用電極４と積層セラミックコンデンサ１６を搭載するた
めの積層セラミックコンデンサ用電極１７とを形成した
配線基板５を乗せ、かつ配線基板５と半導体チップ１お
よび積層セラミックコンデンサ１６とコンデンサ用電極
１７とが半田３により接着固定される。それ以後の工程
は第１の実施例と同様であるからここでの説明は省略す
る。This laminated ceramic capacitor electrode 17
The monolithic ceramic capacitor 16 is connected to the upper portion by the solder 3 in the same process as the mounting of the semiconductor chip 1. That is, with the solder 3 on the electrode 2 in the semiconductor chip 1, the semiconductor chip 1 opposite to the wiring substrate under surface, to form a a connecting electrode 10 for joining the electrode 2 and the wiring pattern 11, wiring Place the wiring substrate 5 formed with the multilayer ceramic capacitor electrode 17 for mounting a connecting electrode 4 and the multilayer ceramic capacitor 16 of the package outer lead 9 on the substrate top surface, and the wiring board 5 and the semiconductor chip 1 and The laminated ceramic capacitor 16 and the capacitor electrode 17 are bonded and fixed by the solder 3. Since the subsequent steps are the same as those in the first embodiment, the description thereof is omitted here.

【００３１】本実施例によれば、第１の実施例の効果に
加え、配線基板５上に積層セラミックコンデンサ１６を
搭載したり、配線基板５そのものにコンデンサの役割を
させることで、パッケージ外部にコンデンサを搭載する
場合より、電源線および接地線におけるより一層のノイ
ズの低減を行え、半導体装置の信頼性向上が図れるだけ
でなく、コンデンサがパッケージ内部に収容されるため
に、製造工程中の接触、脱落の恐れがなく、作業性の向
上が図れる。According to the present embodiment, in addition to the effects of the first embodiment, by mounting the laminated ceramic capacitor 16 on the wiring board 5 or making the wiring board 5 itself act as a capacitor, the package is externally mounted. Compared to the case where a capacitor is mounted, noise on the power supply line and ground line can be further reduced, and not only the reliability of the semiconductor device can be improved, but also because the capacitor is housed inside the package, there is no contact during the manufacturing process. There is no danger of falling off, and workability can be improved.

【００３２】次に、本発明の第３の実施例を説明する。Next, a third embodiment of the present invention will be described.

【００３３】封止用キャップを取り除いた半導体装置の
平面図を示した図３（ａ）、図３（ａ）の線Ｅ−Ｅ′に
おける断面図を示した図３（ｂ）および図３（ｂ）の線
Ｆで囲まれた部分の拡大図を示した図３（ｃ）を参照す
ると、本実施例と第１の実施例との相違点は、パッケー
ジ内に収容する配線基板５が電源配線層（電源層）１８
と接地配線層（接地層）１９とを含んだ多層配線基板２
０からなり、電源層１８と接地層１９とは、それぞれス
ルーホール１２により半導体チップ１の電源用電極およ
び接地用電極と多層配線基板２０上の電源用電極および
接地用電極とが接続されることである。それ以外の構成
要素および製造工程は第１の実施例と同様であるからこ
こでの構成および製造工程の説明は省略する。3A showing a plan view of the semiconductor device from which the sealing cap is removed, and FIGS. 3B and 3B showing a cross-sectional view taken along line EE 'of FIG. 3A. Please refer to FIG. 3 (c) showing an enlarged view of the portion surrounded by the line F of b).
Then , the difference between this embodiment and the first embodiment is that the wiring board 5 housed in the package is the power supply wiring layer (power supply layer) 18
Multilayer wiring board 2 including a ground wiring layer (ground layer) 19
0, and the power supply layer 18 and the ground layer 19 are connected to the power supply electrode and the ground electrode of the semiconductor chip 1 and the power supply electrode and the ground electrode on the multilayer wiring board 20 by through holes 12, respectively. Is. The other components and the manufacturing process are the same as those in the first embodiment, and the description of the structure and the manufacturing process is omitted here.

【００３４】本実施例によれば、第１および第２の実施
例における効果に加えて、配線基板５に電源層および接
地層を設け多層配線基板２０を用いることで、パッケー
ジの共通化による電気特性、特に導通抵抗およびインダ
クタンスの劣化を防止することができる。According to this embodiment, in addition to the effects of the first and second embodiments, the power supply layer and the ground layer are provided on the wiring board 5 and the multilayer wiring board 20 is used. It is possible to prevent deterioration of characteristics, particularly conduction resistance and inductance.

【００３５】[0035]

【発明の効果】以上説明したように本発明は、キャビテ
ィ内の半導体チップ上に配線基板を搭載することによ
り、大きさの異なる複数種類の半導体チップを搭載する
ことが出来るように最小限の広さの底面をもつキャビテ
ィと、その底面の大きさに合わせて配線基板の大きさも
段差部で支持させることが可能な最小限の大きさであれ
ばよいので、従来のように半導体チップと半導体チップ
より大きく、かつキャビティ底面より小さい配線中継部
材とを搭載できる大きさの支持板（配線基板）を必要と
せず、また中継部材に代る配線用電極を周辺部に配設す
るための余分な大きさをもたせた支持板も必要とせず、
キャビティが広くかつ全体としてパッケージが大きくな
る欠点も解決することが出来るので、共通化前よりも小
型のパッケージで、かつパッケージ単価が廉価になる。As described above, according to the present invention, by mounting the wiring substrate on the semiconductor chip in the cavity, it is possible to mount a plurality of types of semiconductor chips having different sizes to a minimum wide area. The size of the cavity having a bottom surface and the size of the wiring board in accordance with the size of the bottom surface need only be the minimum size that can be supported by the step portion. It does not require a support plate (wiring board) of a size larger than the cavity bottom and capable of mounting a wiring relay member, and an extra size for disposing a wiring electrode in the periphery instead of the relay member. There is no need for a support plate with
Since it is possible to solve the disadvantage that the cavity is wide and the package is large as a whole, the package is smaller than before the commonization and the unit price of the package is low.

【００３６】また、配線基板上に積層セラミックコンデ
ンサを搭載したり、配線基板そのものにコンデンサの役
割をさせることで、パッケージ外部にコンデンサを搭載
する場合より、電源線および接地線におけるより一層の
ノイズの低減を行え、半導体装置の信頼性向上が図れる
だけでなく、コンデンサがパッケージ内部に収容される
ために、製造工程中の接触、脱落の恐れがなく、作業性
の向上が図れる。Further, by mounting a monolithic ceramic capacitor on the wiring board, or by making the wiring board itself act as a capacitor, noise of the power supply line and the ground line can be further reduced as compared with the case where the capacitor is mounted outside the package. Not only can it be reduced and the reliability of the semiconductor device can be improved, but since the capacitor is housed inside the package, there is no risk of contact or drop during the manufacturing process, and workability can be improved.

【００３７】さらに配線基板に電源層および接地層を設
けることで、パッケージの共通化による電気特性、特に
導通抵抗およびインダクタンスの劣化を防止することが
できる。Further, by providing the power source layer and the ground layer on the wiring board, it is possible to prevent the deterioration of the electrical characteristics, particularly the conduction resistance and the inductance, due to the common use of the package.

【００３８】したがって、パッケージの共通化が図れる
のみならず、１品種当たりの製造数が増加することによ
るコスト低減、棚資産の低減が行える。また、半導体チ
ップ毎に単純形状の配線基板を設計・開発するだけでよ
く、電気的特性劣化が改善された、期間・コストが大幅
に縮小できる機密封止型半導体装置を提供できる。Therefore, not only the packages can be standardized, but also the cost and the shelf assets can be reduced due to the increase in the number of products manufactured per kind. Further, it is only necessary to design and develop a wiring board having a simple shape for each semiconductor chip, and it is possible to provide a security-sealed semiconductor device in which deterioration in electrical characteristics is improved and period and cost can be significantly reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】（ａ）本発明の第１の実施例を説明するための
封止用キャップを取り除いた半導体装置の平面図であ
る。 （ｂ）（ａ）図の線Ａ−Ａ′における断面図である。 （ｃ）（ｂ）図の線Ｂで囲んだ部分の拡大図である。FIG. 1A is a plan view of a semiconductor device from which a sealing cap has been removed for explaining a first embodiment of the present invention. (B) It is sectional drawing in line AA 'of (a) figure. It is an enlarged view of the part enclosed with the line B of (c) (b) figure.

【図２】（ａ）第２の実施例を説明するための封止用キ
ャップを取り除いた半導体装置の平面図である。 （ｂ）（ａ）図の線Ｃ−Ｃ′における断面図である。 （ｃ）（ｂ）図の線Ｄで囲んだ部分の拡大図である。FIG. 2A is a plan view of a semiconductor device from which a sealing cap has been removed for explaining a second embodiment. (B) It is sectional drawing in line CC 'of (a) figure. It is an enlarged view of the part enclosed with the line D of (c) and (b) figure.

【図３】（ａ）第３の実施例を説明するための封止用キ
ャップを取り除いた半導体装置の平面図である。 （ｂ）（ａ）図の線Ｅ−Ｅ′における断面図である。 （ｃ）（ｂ）図の線Ｆで囲んだ部分の拡大図である。FIG. 3A is a plan view of a semiconductor device from which a sealing cap has been removed for explaining a third embodiment. (B) It is sectional drawing in line EE 'of (a) figure. It is an enlarged view of the part enclosed with the line F of (c) and (b) figure.

【図４】（ａ）従来例を説明するための封止用キャップ
を取り除いた半導体装置の平面図および線Ｇ−Ｇ′にお
ける断面図である。 （ｂ）（ａ）図の変形例で、平面図および線Ｈ−Ｈ′に
おける断面図である。FIG. 4A is a plan view and a cross-sectional view taken along line GG ′ of the semiconductor device from which a sealing cap has been removed for explaining a conventional example. (B) It is a modification of Drawing (a), and is a top view and a sectional view in line HH '.

【符号の説明】[Explanation of symbols]

１ 半導体チップ ２ 半導体チップの電極 ３ 半田 ４，１０ 接続用電極 ５ 配線基板 ６ 熱硬化性樹脂 ７ ボンディング用電極 ８ 金属細線 ９ 外部リード １１ 配線パターン １２ スルーホール １３ 第１開孔部 １４ 第２開孔部 １５ 段差部 １６ 積層セラミックコンデンサ １７ 積層セラミックコンデンサ用電極 １８ 電源層 １９ 接地層 ２０ 多層配線基板 1 Semiconductor Chip 2 Semiconductor Chip Electrode 3 Solder 4,10 Connection Electrode 5 Wiring Board 6 Thermosetting Resin 7 Bonding Electrode 8 Metal Fine Wire 9 External Lead 11 Wiring Pattern 12 Through Hole 13 First Opening 14 Second Opening Hole 15 Step 16 Multilayer ceramic capacitor 17 Multilayer ceramic capacitor electrode 18 Power layer 19 Ground layer 20 Multilayer wiring board

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 大きさの異なる半導体チップがそれぞれ
共通に搭載されうる底部表面積と深さとをもち第１の電
極群が周縁部に配設された第１開孔部と、この開孔部の
前記周縁部を囲みかつ前記第１開孔部よりも大きい第２
開孔部とをもち、前記第１および前記第２開孔部間に配
線基板上面が前記第２開口部底面と略同一平面上に位置
するようにかつ前記配線基板の外周部を接着して支持す
る段差部が設けられたキャビティを有する気密封止型半
導体装置において、前記配線基板が前記底部表面積より
も大きい少なくとも３層からなる多層配線基板であって
その下面に配設された第２の電極群および前記半導体チ
ップの素子形成面に形成された電極群のそれぞれを互い
に電気的に接続するように搭載され、かつ前記半導体チ
ップの下面が前記第１開孔部底部に接着されるととも
に、前記第２の電極群に接続される配線と前記多層配線
層のうちの内部層の配線と前記多層配線基板上面に配設
された第３の電極群とがそれぞれスルーホールを介して
接続され、これら第３の電極群が金属細線によって前記
段差部よりも外側でかつ略同一平面上にある前記第１の
電極群に段差をつけずにそれぞれ接続されることを特徴
とする気密封止型半導体装置。1. A first opening having a bottom surface area and a depth on which semiconductor chips of different sizes can be mounted in common, and a first electrode group is provided at a peripheral portion, and a first opening of the opening. A second portion that surrounds the peripheral portion and is larger than the first opening portion
An opening portion and arranged between the first and second opening portions.
The top surface of the wire substrate is located on substantially the same plane as the bottom surface of the second opening.
And the outer peripheral portion of the wiring board is adhered and supported.
In a hermetically sealed semiconductor device having a cavity provided with a step portion , the wiring substrate is smaller than the bottom surface area.
Is a multi-layer wiring board consisting of at least three layers
The second electrode group disposed on the lower surface and the semiconductor chip
The electrode groups formed on the device formation surface of the
Is mounted so as to be electrically connected to
The lower surface of the cup is adhered to the bottom of the first opening.
A wiring connected to the second electrode group and the multilayer wiring
Arranged on the inner layer wiring of the layers and the upper surface of the multilayer wiring board
Through the through holes, respectively.
The third electrode group is connected by a thin metal wire.
The first outside of the step portion and substantially on the same plane
A hermetically sealed semiconductor device, wherein each electrode group is connected without a step . 【請求項２】 前記多層配線基板は、前記半導体チップ
の電源配線および接地配線間に挿入される積層セラミッ
クコンデンサ接続用の第４の電極群を前記上面に備える
請求項１記載の気密封止型半導体装置。2. The multilayer wiring board is the semiconductor chip.
The laminated ceramics that are inserted between the power and ground wiring of the
The hermetically sealed semiconductor device according to claim 1 , wherein a fourth electrode group for connecting a capacitor is provided on the upper surface . 【請求項３】 前記多層配線基板の内部層の配線層が、
電源配線層および接地配線層のうち一方、または両方の
配線層を備える請求項１記載の気密封止型半導体装置。 3. A wiring layer as an inner layer of the multilayer wiring board,
One or both of the power wiring layer and ground wiring layer
The hermetically sealed semiconductor device according to claim 1, further comprising a wiring layer .
JP6265593A 1994-10-28 1994-10-28 Hermetically sealed semiconductor device Expired - Lifetime JP2671827B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6265593A JP2671827B2 (en) 1994-10-28 1994-10-28 Hermetically sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6265593A JP2671827B2 (en) 1994-10-28 1994-10-28 Hermetically sealed semiconductor device

Publications (2)

Publication Number Publication Date
JPH08125065A JPH08125065A (en) 1996-05-17
JP2671827B2 true JP2671827B2 (en) 1997-11-05

Family

ID=17419282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6265593A Expired - Lifetime JP2671827B2 (en) 1994-10-28 1994-10-28 Hermetically sealed semiconductor device

Country Status (1)

Country Link
JP (1) JP2671827B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5798557A (en) * 1996-08-29 1998-08-25 Harris Corporation Lid wafer bond packaging and micromachining
KR100244708B1 (en) * 1996-12-10 2000-02-15 김영환 Semiconductor package

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0563033A (en) * 1991-08-29 1993-03-12 Shinko Electric Ind Co Ltd Semiconductor chip connection device

Also Published As

Publication number Publication date
JPH08125065A (en) 1996-05-17

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