JP2659608B2 - DA converter - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DA converter, and in particular, generates an analog signal for smoothly interpolating between discrete digital data.
About DA converter.

<Conventional technology> A conventional conversion theory of a DA converter using a digital filter is to replace discrete digital data with a sampling time ΔT interval with a predetermined function and add a function value of each digital data on a time axis. This is to interpolate. The function corresponding to the digital value D is defined as a function (called a unit interpolation function) for the unit data (= 1), and is obtained as a product of the unit interpolation function and D. or,
Actually, the data is compressed by the data value with the full scale (FS) set to 1, and then the digital data is interpolated by adding the function values on the time axis.

16 to 18 are examples of a unit interpolation function for unit data, FIG. 16 is an example in which the interpolation function is expressed by a quadratic function, FIG. 17 is an example in which the interpolation function is expressed by a cubic function, FIG. FIG. 18 shows an example in which the interpolation function is represented by sin (π · fs · t) / π · fs · t. Note that the cubic function F in FIG. 17 is given by the following equation: F (t) = 0−1.5 ≦ t <1 F (t) = − 2 (t + 1) ³ +3 (t + 1) ² −1 ≦
t <0 F (t) = 2t ³ −3t ² +1 0 ≦ t <1 F (t) = 0 1 ≦ t <1.5

FIG. 19 shows digital data D (1), D (0), D (-1), D when the unit interpolation function is the quadratic function waveform of FIG.
Function ((2)) IF (1), IF (0), 1F (-1), IF (-
FIG. 2 is a relationship diagram between 2) and an analog signal AS obtained by adding each function value on a time axis.

By the way, since the sum of the quadratic functions is a quadratic function, the sum of the cubic functions is a cubic function, and the sum of the sine waves is a sine wave, the interpolation output (analog signal) produced by the conventional method is the interpolation used. Inherits the unique properties of the function and creates a single, unique playback space. However, this means that data recorded in various spaces is modulated into a single unique space, and data recorded in a sound field space that is artistic and has various personalities like music. This means that the original sound field cannot be reproduced.

Also, digital data obtained by sampling a 20 KHz sine wave at 44.1 KHz is converted to the conventional method (unit interpolation function
Is converted to an analog signal by the cubic function shown in FIG.
As shown by a circle C in FIG. 20, an unnatural waveform is generated when viewed from the data group. This is because all digital data is interpolated with only a cubic function.
The intrinsic properties of the interpolation function have surfaced.

Further, when a digital data group whose value changes linearly is converted into an analog signal by a conventional method (the unit interpolation function is a cubic function in FIG. 17), the portion connected by a straight line as shown in FIG. 21 is sampled. The undulation is caused by a cubic function every time Ts, and an accurate analog signal cannot be obtained.

The problems in FIGS. 20 and 21 similarly occur when the unit interpolation function is a quadratic function in FIG.

On the other hand, if the unit interpolation function is a sine waveform shown in FIG. 18, the original analog signal can be accurately reproduced when the data changes like a continuous sine wave. However, when data changes impulsely, unnecessary vibration occurs. For this reason, for example, when a digital data group that changes linearly so that the data value wraps in the middle is converted into an analog signal by the conventional method (the unit interpolation function is a sine wave in FIG. 18),
As shown in FIG. 22, the portion connected by the conversion swells with a sine wave every sampling time Ts, and an accurate analog signal cannot be obtained.

From the above, the present applicant has proposed a direct interpolation DA converter (patent application date: June 11, 1990, name: DA converter).

FIG. 23 is a block diagram of such a proposed DA converter, in which discrete data D (N
+1), D (N),... D (0)... D (1-M), D (−
M), a digital data output unit 12 generates a gradient G (0) at a target data position of an interpolation function for interpolating between the digital data D (0) of interest and the digital data D (-1) one sampling time earlier. ) To calculate the slope,
Reference numeral 13 denotes interpolation between the digital data D (0) and the digital data D (1) one sampling time later in consideration of the digital data D (0) of interest and the digital data before and after the digital data D (0) and the gradient G (0). This is an interpolation function generator that determines an interpolation function F01 (t) to be performed.

The digital data output unit 11 includes a number of delay circuits Z (N +) for delaying digital data by one sampling time (Ts).
1), Z (N),... Z (0)... Z (1-M), Z (−
M), and these are connected in series.
Digital data is sequentially input to the delay circuit Z (N + 1) from a digital data generator (not shown) for each sampling time Ts, and the data stored in each delay circuit is shifted to the right every sampling time. Therefore, if the digital data of interest is D (0), some digital data D (-1) to D (-M) generated before the digital data and digital data D (0) generated after the digital data D (0) are generated. Some digital data D (1) to D
(N + 1) is output from each delay circuit.

The interpolation function generator 13 outputs the digital data D of interest.
Function determination for determining an interpolation function for interpolating between digital data D (0) and digital data D (1) after one sampling time in consideration of (0), the digital data before and after the digital data and gradient G (0). It has a unit 13a, a coefficient calculation unit 13b that determines coefficients of each order in the determined function, and a function generation unit 13c that generates the determined interpolation function using the calculated coefficients. Note that the digital data following the current digital data of interest becomes new digital data of interest at every sampling time, and a new interpolation function is generated at every sampling time from the interpolation function generator 13, and these interpolation functions are connected. Is output.

According to the DA converter of the direct interpolation method, the slope at the data position of interest of the interpolation function for interpolating between the digital data of interest and the digital data one sampling time ago is calculated, and the slope, the data of interest, and its surroundings are calculated. In consideration of the digital data, an interpolation function for interpolating between the target data and the digital data after one sampling time is determined, and the interpolation function between the respective digital data is connected to generate an analog signal. As a result, the interpolation function between the data can be changed according to the data change, and a reproduction space corresponding to the data change can be created. Further, interpolation can be performed smoothly between the digital data so as not to generate unnecessary vibration.

<Problems to be Solved by the Invention> However, in the direct-interpolation type DA converter, the digital output processing is performed and the interpolation output F ₀₁ between the sampling data is performed.
Since (t) is obtained, the obtained interpolated output is a digital code for every predetermined time, and a so-called step-like output waveform is obtained regardless of the apparent oversampling number A, and a true output waveform is obtained. To obtain an analog, a low-pass filter is indispensable. The existence of this low-pass filter
This causes phase distortion at a high frequency, which leads to a great deterioration in sound quality. Also, the presence of the low-pass filter slows the rise of the pulse-like signal and causes vibration at the fall,
When a music signal having many impulsive changes is input, the sound quality is changed.

As described above, an object of the present invention is to provide a DA converter of a direct interpolation system that does not require a low-pass filter.

<Means for Solving the Problems> According to the present invention, the present invention relates to some digital data generated before the digital data of interest and some digital data generated after the digital data of interest. A digital data output unit that outputs the digital data of interest, a slope calculation unit that calculates the slope of the interpolation function that interpolates between the digital data of interest and the digital data one sampling time earlier at the data position of interest, Each order t ¹ , t ² ,... Of the interpolation function (time is a variable) for interpolating between the digital data of interest based on the digital data before and after it and the slope and the digital data after one sampling time. The interpolation function determining unit that determines the coefficient of the multiplication, the multiplication type DA converter that multiplies each coefficient and the order, and the output of each multiplication type DA converter are added. It is achieved by the that adder.

<Operation> The slope of the interpolation function for interpolating between the digital data of interest and the digital data one sampling time ago is calculated at the data position of interest, and the slope and the digital data of interest and the digital data before and after it are calculated. The coefficient of each order t ¹ , t ₂ ,... Of the interpolation function (time is a variable) for interpolating between the digital data of interest and the digital data after one sampling time is determined based on the multiplication DA In the converter, digital data is converted into analog by multiplying each coefficient by the order t ¹ , t ² ,... And adding the output of each multiplication type DA converter. This eliminates the need for a low-pass filter.

<Embodiment> Overall Configuration of DA Converter of the Present Invention FIG. 1 is a configuration diagram of a DA converter according to the present invention.

In the figure, reference numeral 21 denotes discrete data D for each sampling time Ts.
(N + 1), D (N),... D (0)... D (1-M), D
(-M) is a digital data output unit. The digital data output unit 21 includes a number of delay circuits Z (N +) for delaying digital data by one sampling time (Ts).
1), Z (N),... Z (0)... Z (1-M), Z (−
M), and these are connected in series.
When the input data is parallel data, each delay circuit
It is composed of a latch circuit using LCK1 as a latch clock for each sampling, and in the case of serial data, it is composed of a shift register using WBCK as a bit clock for sending data. Digital data is sequentially input to the delay circuit Z (N + 1) every time the sampling time Ts (sampling frequency is fs) from a digital data generator (not shown), and the data stored in each delay circuit is output every one sampling time. Then, shift to the next stage. Therefore, if the digital data of interest is D (0), some digital data D (-1) to
D (-M) and some digital data D (1) to D (N + 1) generated after the digital data D (0) are output from each delay circuit.

Reference numeral 22 denotes an interpolation function determination unit, which determines a predefined function based on the digital data D (0) of interest and the digital data before and after it and the gradient G (0) of the interpolation function one sampling time ago. From inside, digital data D
(0) and digital data D after one sampling time
(1) Interpolation function for interpolating between F ₀₁ (t) = K _{(K + 2)} t ^{(N + 2)} + K _{(N + 1)} t ^{(N + 1)} + K _N t ^N +... + K ₁ t + D (0) (A-1) is selected, and a coefficient calculation method for each order t ¹ , t ² ,... is output. The selected interpolation function and coefficient calculation method are reset every Ts by the latch clock LCK1.

Reference numeral 23 denotes a coefficient calculation unit that uses the digital data D (0) of interest, the digital data before and after the digital data D (0), and the gradient G (0) based on the instructed coefficient calculation method to calculate the interpolation function F (0).
₀₁ Coefficients K ₁ , K ₂ ,... K of each order t ¹ , t ² ,... T ^{(N + 2)} of (t)
Determine _{(N + 2)} . The determined coefficient calculation method is reset every Ts by the latch clock LCK1.

Reference numeral 24 denotes a latch, which is a coefficient calculated by the coefficient calculator.
K ₁ , K ₂ ,... K _{(N + 2)} and a constant D (0) of the interpolation function are stored for Ts by the latch clock LCK2.
₁ , LK ₂ ,... LK _{(N + 2)} . Latch clock LCK2
Is Ts similarly to the latch clock LCK1, and is generated after the latch clock LCK1 by the time Td obtained by adding the operation time of the interpolation function determination unit 22, the operation time of the coefficient operation unit 23, and the margin time.

Numeral 25 denotes a slope calculator, which is the digital data D (0) of interest and the digital data D one sampling time ago.
The gradient G (0) at the target data position of the interpolation function that interpolates between (−1) is expressed by the following equation: G (0) = {dF ₀₁ (t) / dt} = (N + 2) · K _{(N + 2)} + ( N + 1) · K _{(N + 1)} + N · K _N +... + K ₁ (A-2)

Reference numeral 26 denotes a multiplication unit for multiplying the digital data and the analog signal. Each coefficient K ₁ , K ₂ ,..., K _{(N + 2)} and the corresponding order
Multiplying DA converter ML that multiplies t ¹ , t ² ,... t ^{(N + 2)}
_{(N + 2), ML (} N + 1), MLK N, and a · · · ML _1. At the time of multiplication, one of the coefficient and the order is converted to analog. The multiplication output is reset by the latch clock LCK2.

27 is the analog Vdo for the constant D (0) of the interpolation function F ₀₁ (t).
Analog converter to convert to, 28 are each multiplication type DA converter
ML _{(N + 2)} , ML _{(N + 1)} , MLK _N ,..., An adder for adding the output of ML ₁ and the output Vdo of the analog converter 27, and 29 is a latch clock L
This is a delay circuit that delays CK1 for a predetermined time Td.

If the digital data output to each multiplying DA converter of the multiplier 26 is Vdi and the analog voltage is Vai, the output of the adder 28 is It can be said that this is a true analog output for digital data. The digital data following the current digital data of interest becomes new digital data of interest every sampling time, and an analog output corresponding to a new interpolation function is obtained from the adder 28 every sampling time.

Hereinafter, configurations of the interpolation function determining unit 22, the coefficient calculating unit 23, and the multiplying DA converter will be described.

(A) Interpolation function determination unit (a-1) Function determination method Using digital data D (N + 1) to D (-M),
An interpolation function F ₀₁ (t) for interpolating between the current digital data D (0) of interest and the digital data D (1) after one sampling time is determined according to the following selection criteria 1) to 12).

1) When D (1) = D (0) = D (−1) (see FIG. 2A), F ₀₁ (t) = D (0) (0 ≦ t <1) (1) 2) D (1) ≠ D (0) = D (−1) = D (−2), D
(4) = D (3) = D (2) (see FIG. 2 (b)) F ₀₁ (t) is a cubic polynomial, and the slope at t = 0, t = 1 is 0 .

F ₀₁ (t) = 2 ｛D (0) -D (1)｝ t ³ +3 ｛D (1) -D (0)｝ t ² + D (0) (0 ≦ t <1) (2) 3) D (0) ≠ D (1) = D (3) = D (2) = D
(-1) = D (-2) (see FIG. 2 (c)) F ₀₁ (t) is a cubic polynomial, and the slope at t = 0 and t = 1 is 0.

F ₀₁ (t) = 2 ｛D (0) -D (1)｝ t ³ +3 ｛D (1) -D (0)｝ t ² + D (0) (0 ≦ t <1) (2) 4) D (3) = D (2) = D (1) ≠ D (0) = D
(-1) = D (-2) (see FIG. 2 (d)) _F01 is a cubic polynomial, and the slope at t = 0, t = 1 is 0.

F ₀₁ (t) = 2 ｛D (0) -D (1)｝ t ³ +3 ｛D (1) -D (0)｝ t ² + D (0) (0 ≦ t <1) (2) 5) {D (2) -D (1)} = {D (1) -D
(0)｝, D (0) = D (−1) = D (−2) (see FIG. 2 (e)) F ₀₁ (t) is a first-order polynomial, and F ₀₁ (t) = ｛ D (1) −D (0)｝ t + D (0) (0 ≦ t <1) (3) 6) D (3) = D (2) = D (1), ΔD (1) − D
(0)｝ = G (0) (see FIG. 2 (f)). Here, G (0) is the slope of the function F _-10 (t) for interpolating between the data one sampling time before the current time and the current data at the target data position. In addition, one sampling time ago,
F _-10 (t) is F ₀₁ (t), so that the gradient G (0) is F
_This is the slope of _-10 (t) at t = 1.

F ₀₁ (t) is a first-order polynomial, and F ₀₁ (t) = {D (1) −D (0)} t + D (0) (0 ≦ t <1) (3) 7) One sampling time The function F- ₀₁ (t) before Ts is selected, the gradient G (0) at t = 1 (= F- ₀₁ '(1)) is determined, and D (3) = D (2) = D ( In the case of 1) (see FIG. 2 (g)), F ₀₁ (t) is a cubic polynomial, and the slope at t = 1 is 0.

_{F 01 (t) = K3 ·} t 3 + K2 · t 2 + G (0) · t + D (0) (0 ≦ t <1) ·· (4) where, K3 = 2 {D (0 ) -D (1) ｝ + G (0) K2 = 3 ｛D (1) −D (0)｝ − 2G (0) 8) G (0) is determined and D (1) = ± FS (full scale) (second (See (h) of FIG.) F ₀₁ (t) is a cubic polynomial, and the slope at t = 1 is 0.

_{F 01 (t) = K3 ·} t 3 + K2 · t 2 + G (0) · t + D (0) (0 ≦ t <1) ·· (4) where, K3 = 2 {D (0 ) -D (1) ｝ + G (0) K2 = 3 ｛D (1) -D (0)｝-2G (0) 9) When D (0) = ± FS (full scale) G (0) = 0.

10) G (0) is determined, and D (N−) when D (N) = ± FS.
1) to D (1) are not ± FS (see FIG. 2 (i)) F ₀₁ (t) is an (N + 2) -th order polynomial, and the slope at t = N is 0. N = 2 in the F when ₀₁ seek (t) When _{F 01 (t) = K4 ·} t 4 + K3 · t 3 + K2 · t 2 + G (0) · t + D (0) (0 ≦ t <1) ·・ (5) However, K4 = {− 2 · D (2) + 4 · D (1) −2 · D (0) −G (0)} / 4 K3 = {7 · D (2) −16 · D (1) + 9 · D (0) + 5 · G (0)｝ / 4 K2 = {− 5 · D (2) + 16 · D (1) −11 · D (0) −8 · G (0)} / It becomes 4. The function F after one sampling time Ts
₁₂ (t), in other words, the function F ₀₁ (t) after one sampling time has elapsed (see FIG. 2 (j)) is determined by the condition of 8), and F ₀₁ (t) = K3 · t ³ + K2 · t ² + G (0) · t + D (0) (0 ≦ t <1) (4) where K3 = 2 ｛D (0) −D (1)｝ + G (0) K2 = 3 ｛D (1) −D (0)｝ − 2G (0)

In the case of N = 3 is, F ₀₁ (t) becomes a fifth order polynomial, the following formula _{F 01 (t) = K5 ·} t 5 + K4 · t 4 + K3 · t 3 + K2 · t 2 + G (0) TD (0) (0 ≦ t <1) (6) However, K5 = {− 13 · D (3) + 27 · D (2) −27 · D (1) + 13 · D (0) + 6 · G (0)} / 108 K4 = {28 · D (3) − 63 · D (2) + 72 · D (1) −37 · D (0) −18 · G (0)｝ / 36 K3 = ｛− 161 · D (3) + 405 · D (2) −567 · D
(1) + 323 · D (0) + 174 · G (0)｝ / 108 K2 = {10 · D (3) −27 · D (2) + 54 · D (1) −37 · D (0) −26 · G (0)｝ / 12 11) G (0) is determined, and D (N) to D (1) are ± FS
If not (see FIG. 2 (k)), F ₀₁ (t) is a (N + 1) -degree polynomial, and if N = 3, F ₀₁ (t) = K ⁴ · t ⁴ + K ³ · t ³ + K 2 · t ² + G (0) · t + D (0)) (0 ≦ t <1) (7) Where K4 = {2D (3) -9D (2) + 18D (1) -11D (0) -6G (0)} / 36 K3 = {-D (3) +6 D (2) -15D (1) + 10D (0) + 6G (0) / 6K2 = {4D (3) -27D (2) + 108D (1)- 85 · D (0) −66 · G (0)｝ / 36 12) In the case of the above function F ₀₁ (t), depending on the input data group, the absolute value of {F ₀₁ (t)｝ max is the full scale. Overrun and overflow may occur. In order to prevent such an overflow, the input data or all the obtained coefficients may be multiplied by a safety coefficient A ≦ FS / ｛F ₀₁ (t)｝ max.

(A-2) Configuration of Interpolation Function Determination Unit FIG. 3 is a configuration diagram of the function determination unit 22, where SBC is a subtractor and LG is a high level (“1”) when the subtraction result is 0 (zero).
Is a logic circuit that outputs a low-level (“0”) signal in other cases, and AG is an AND gate and an ORG OR gate. In the figure, when the output a is at a high level, the condition 1) is satisfied,
Select the interpolation function (F ₁₀ (t) = D (0)) shown in the equation (1). When the output b is at a high level, the condition of 5) or 6) is satisfied, and the equation shown in the equation (3) is satisfied. Select the first-order interpolation function F ₀₁ (t) = {D (1) -D (0)} t + D (0). When output c is at high level, 2), 3), 4), 7) , 8) is satisfied and the cubic interpolation function shown in equation (2) is selected. When output d is at a high level, condition 10) (where N =
If the output e is at a high level, the condition (10) is satisfied (where N =
If the condition (3) is satisfied and the fifth-order interpolation function shown in the expression (6) is selected, and the outputs a, b, c, d, and e are all at low level, the condition of 11) is satisfied and the expression (7) is satisfied. Is selected.

(B) Coefficient calculation unit FIGS. 4 to 8 are block diagrams of a coefficient calculation unit that determines coefficients in the respective orders t ¹ , t ² ,... Of the function determined by the interpolation function determination unit 22. A coefficient calculation unit is provided for each maximum order of the interpolation function, and a predetermined coefficient is selected by a coefficient selection unit described later.

(B-1) Coefficient operation part of linear function (Equation (3)) As shown in FIG. 4, the coefficient operation part of the linear function adds ± 1 multiplier MLP and the output of each multiplier to 1 Order coefficient K11 (=
Adder ADD that outputs {D (1) -D (0)}) and a
Is a low level and b is a high level. The gate circuit GTC outputs a primary coefficient K11 calculated when it is at a high level.

(B-2) Coefficient operation part of cubic function (Equation (2) or (4)) The coefficient operation part of the cubic function is 1, ± 2, as shown in FIG.
Six multipliers MLP for multiplying the input signal by ± 3, and a cubic coefficient K32 (= 2 ｛D (0) -D
(1) An adder ADD1 that outputs｝ + G (0)) and a multiplier output are added to add a secondary coefficient K22 (= 3 ｛D (1) −D)
An adder ADD2 that outputs (0) 出力 −2G (0)), and a gate circuit that outputs the tertiary and secondary coefficients K32 and K22 calculated when a and b are at low level and c is at high level. It consists of GTC1 and GTC2.

(B-3) Fourth-order function (Equation (5)) coefficient operation unit As shown in FIG. 6, the four-order function (Equation (5)) coefficient operation unit multiplies the input signal by a predetermined value. Multiplier MLP
And an adder ADD1 that adds the multiplier outputs and outputs a fourth order coefficient K43 = {− 2 · D (2) + 4 · D (1) −2 · D (0) −G (0)} / 4 An adder ADD2 that adds the multiplier outputs and outputs a cubic coefficient K33 = {7 · D (2) −16 · D (1) + 9 · D (0) + 5 · G (0)} / 4; An adder ADD3 that adds the multiplier outputs and outputs a secondary coefficient K23 = {− 5 · D (2) + 16 · D (1) −11 · D (0) −8 · G (0)} / 4 , A, b, c are at low level and d is at high level, the calculated fourth, third and second order coefficients K43,
Gate circuits GTC1, GTC2, GTC3 that output K33 and K23 respectively
It consists of.

(B-4) Coefficient operation part of quartic function (Equation (7)) As shown in FIG. 7, the coefficient operation part of quartic function (Equation (7)) multiplies the input signal by a predetermined value as shown in FIG. Multiplier MLP
And the multiplier output to add the fourth order coefficient K44 = {2 · D (3) −9 · D (2) + 18 · D (1) −11 · D (0) −6 · G (0)} / Adder ADD1 that outputs 36 and the output of the multiplier are added to add a third order coefficient K34 = ｛− D (3) + 6 · D (2) −15 · D (1) + 10 · D (0) + 6 · G ( 0) The adder ADD3 that outputs｝ / 6 and the output of the multiplier are added to add a quadratic coefficient K24 = ｛4 · D (3) −27 · D (2) + 108 · D (1) −85 · D ( 0) −66 · G (0)｝ / 36, and the calculated fourth-, third-, and second-order coefficients K44 when a, b, c, d, and e are all low level. , K34, K24
Are output from the gate circuits GTC1, GTC2, and GTC3.

(B-5) Coefficient operation part of quintic function (Equation (6)) As shown in FIG. 8, the coefficient operation part of quintic function (Equation (6)) multiplies the input signal by a predetermined value. Multiplier MLP
And the multiplier output to add the fifth order coefficient K55 = {− 13 · D (3) + 27 · D (2) −27 · D (1) + 13 · D (0) + 6 · G (0)} / 108 And an adder ADD1 which outputs the following equation and a multiplier coefficient K45 = ４28 係数 D (3) -63 ・ D (2) +72 ・ D (1) -37 ・ D (0) -18 ・The adder ADD2 that outputs G (0)｝ / 36 and the output of the multiplier are added to add a third order coefficient K35 = ｛− 161 · D (3) + 405 · D (2) −567 · D
(1) Adder ADD3 that outputs + 323 · D (0) + 174 · G (0)｝ / 108 and the output of the multiplier to add a secondary coefficient K25 = {10 · D (3) −27 · D ( 2) Adder ADD4 that outputs + 54 · D (1) −37 · D (0) −26 · G (0)｝ / 12 and a, b, c, and d are low level and e
Are high level, gate circuits GTC1, GTC2, which output the calculated fifth-order, fourth-order, third-order, and second-order coefficients K55 to K25, respectively.
It is composed of GTC3 and GTC4.

(B-6) Coefficient Selection Unit The coefficient selection unit 23a has coefficient selection circuits 23a-1, 23a-2,... 23a-5 for each order as shown in FIG. , The first, second, third, fourth, and fifth order coefficients of the interpolation function determined by the interpolation function determination unit 22 are selected and output to the latch unit 24 at the next stage.

(C) Multiplication unit (c-1) Embodiment of multiplication unit FIG. 10 is a configuration diagram of the multiplication unit 26.
^{(N + 2)} , t ^{(N + 1)} , t ^N ,..., T An analog order signal generator that periodically generates an analog signal in one sampling period, 26b multiplies digital data by an analog signal Digital multipliers K _{(N + 2)} , K
_{(N + 1)} , K _N , ... K ₁ and corresponding order t ^{(N + 2)} , t ^{(N + 1)} , t ^N ,
.... Multiplying DA converter M _{(N + 2)} , M
_{(N + 1), M N} , and a · · · M _1. 24 'is the order t
^{(N + 2)} , t ^{(N + 1)} , t ^N , ... Coefficient of t K _{(N + 2)} , K _{(N + 1)} , K _N ,
····· Latch section that holds K ₁ (digital).

Each multiplication type DA converter M _{(N + 2)} , M _{(N + 1)} , M _(N) , ... M
₍₁₎ has a digital input terminal and a reference input terminal, an output generated by a digital input is controlled by a reference input signal Vrf, and an output Vm of the output is generated when Vrf = 1. It is given by the formula Vm = Vrf · Vd (B-1).

The digital coefficients K _{(N + 2)} , K _{(N + 1)} , K _N ,..., K ₁ are respectively applied to the corresponding digital input terminals of the multiplying DA converter, and when Vrf = 1, V K _{(N + 2 )} , VK _{(N + 1)} , VK _N , ... VK ₁
Is output.

The order t output from the analog order signal generator 26a
^{(N + 2)} , t ^{(N + 1)} , t ^N , ... t analog signal Vt ^{(N + 2)} , Vt
^{(N + 1)} , Vt ^N , ... Vt is applied to the reference input terminal, and each multiplying DA converter M _{(N + 2)} , M _{(N + 1)} , M _(N) , ... M ₍₁₎
From _{VK (N + 2) · Vt} (N + 2), VK (N + 1) · Vt (N + 1), VK N · Vt N, ··· VK 1 · V t (B-2) is output Is done.

(C-2) an embodiment Figure 11 of the analog order signal generator is an example of an analog order signal generator of degree t ^N, periodically generating an analog signal of order t ^N for each sampling period Ts It is supposed to. Note that the order t ^{(N + 2)} , t
Analog signals can be generated with the same configuration for ^{(N + 1)} ,.

The counter 31 clears the count value by the launch clock LCK2 generated at the sampling period, and
・ Bit clock signal of fs (fs is sampling frequency)
BCK is counted and an address signal As for the ROM 32 is generated.

Time to ROM32 1 / (a · fs) Interval digitized degree t digital value a number of ^N in the address signal output from the counter 31 from being continuously stored in the address order
As there is an analog signal waveform storage if sequentially reads the digital data output from the order t ^N instructing obtained.

The digital data output from the ROM 32 is a bit clock BC delayed by the delay circuit 33 until all outputs are stabilized.
It is latched by the latch circuit 34 by K '. Thereafter, the latched data is input to a DA converter 35, where the data is converted into a step-like voltage waveform, then converted into a smooth continuous analog signal by a low-pass filter 36, and finally output through a buffer amplifier 37 for sending out. Is done. Note that the phase distortion of the low-pass filter 36 is not a problem since the analog order signal only needs to have a required waveform as a result. In other words,
The digital data stored in the ROM 32 may be corrected by the low-pass filter 36 for the “rounded” waveform.

(C-3) Another Embodiment of Analog Order Signal Generating Unit FIG. 12 shows an analog order for generating analog signals of orders t ^{(N + 2)} , t ^{(N + 1)} , t ^N ,. This is another embodiment of the signal generator 26a, and is an (N + 2) -stage integrating / amplifying circuit IA (N +
2), ··, IA2, is constituted by IA1, orders from the integration and amplification circuit of each stage ^{t (N + 2), t} (N + 1), t N, the analog signal V in · · · · t
^{t (N + 2), Vt} (N + 1), Vt N, ···· Vt is to be outputted. Each integration / amplification circuit consists of an integration circuit INT and an amplification circuit A
MP, the integrator INT is composed of an operational amplifier OPAmp and a resistor
In R ₁ and a capacitor C and a latch clock LCK2 each occurrence is a switch S for discharging the capacitor, the amplifier circuit AMP is an operational amplifier OPAmp a resistor R ₂ and the output adjusting resistor R ₃ ~R _{(N + 4)}
It is composed of Vc is a DC power supply.

(C-4) Another embodiment of the multiplying unit FIG. 13 is another block diagram of the multiplying unit 26.
Digital value Dt ^{(N + 2)} , Dt ^{(N + 1)} , Dt ^N , ... Dt in one sampling period of ^{(N + 2)} , t ^{(N + 1)} , t ^N , ... t Is a digital order data generator that periodically generates
^{(N + 2)} , t ^{(N + 1)} , t ^N , ... t Digital coefficient data K of t
_{(N + 2), K (} N + 1), K N, the · · · · K ₁ DA converter for analog conversion, 26e in multiplying DA converter unit, order data D
t ^{(N + 2)} , Dt ^{(N + 1)} , Dt ^N , ... Multiplying DA converter M _{(N + 2)} , M _{(N + 1)} , M which multiplies Dt and the corresponding analog coefficient signal
_(N) ,... M ₍₁₎ . 24 'is the coefficient of each order
_{K (N + 2), K} (N + 1), a latch portion for holding K _N, the · · · · K _1.

The order data Dt ^{(N + 2)} , Dt ^{(N + 1)} , Dt ^N , ... Dt is the corresponding multiplying DA converter M _{(N + 2)} , M _{(N + 1)} , M _{(N) 1} ...
- applied to the digital input terminal of the M _(1), respectively Vt ^{(N + 2)} when ^{Vrf = 1, Vt (N +} 1), Vt N, and outputs the · · · · Vt.

Coefficient K _{(N + 2)} , K _{(N + 1)} , K _N , ... K ₁ DA converter output VK
_{(N + 2)} , VK _{(N + 1)} , VK _N ,... VK ₁ is applied to the reference input terminal, and VK _{(N + 2)} · Vt ^{(N + 2)} , VK _{(N + 1)} · Vt ^{(N + 1)} , VK _N · Vt ^N ,... VK ₁ · Vt are output.

(C-5) Configuration Fig. 14 of the digital order data generating unit is the embodiment of a digital order data generator of t ^N, is the digital data of degree t ^N to periodically occur every sampling period Ts ing. The configuration of the digital order data generator is the same as that of the analog order signal generator shown in FIG.
Note that digital data can be generated with the same configuration for the orders t ^{(N + 2)} , t ^{(N + 1)} ,.

(C-6) Another Embodiment of Multiplying DA Converter FIG. 15 shows still another embodiment of the multiplying DA converter. Reference numeral 24 'denotes each order t ^{(N + 2)} , t ^{(N + 1)} , t ^N, the digital coefficient · · · · t data _{K (N + 2), K} (N + 1), K N, latch unit for storing ···· K _1, 41 is a digital coefficient data K _{(N + 2)} , K _{(N + 1)} ,
K _N, DA converter for converting · · · · K ₁ analog, 42 each D
An integration unit 43 for integrating the A-converted output is an output buffer capable of level adjustment.

Digital coefficient data K _{(N + 2)} , K _{(N + 1)} , K _N , ... D of K ₁
A converter _{41 (N + 2), 41} (N + 1), 41 N, the output of ... 41 _1,
Each of (N + 2) stages, (N + 1) stages, N stages, ...
One-stage integration circuit INT is connected, and the corresponding output buffer 4
3 _{(N + 2)} , 43 _{(N + 1)} , 43 _N , ... 43 From ₁ to VK _{(N + 2)} Vt ^{(N + 2)} , VK _{(N + 1)} Vt ^{(N + 1 )} , VK _N · Vt ^N ,... VK ₁ · Vt are output. Incidentally, the integration circuit INT is a switch S which discharges the capacitor to the operational amplifier OPAmp a resistor R ₁ and capacitor C and a latch clock LCK2 each generation.

In the output buffer 43, among 43 ₁ to 43 _{(N + 2)} , an odd number 43 is an inversion buffer, and an even number 43 is a non-inversion buffer.

<Effects of the Invention> As described above, according to the present invention, the slope at the target data position of the interpolation function for interpolating between the digital data of interest and the digital data one sampling time ago is calculated, and the slope and the digital of interest are calculated. Each order t ¹ , t ² ,... Of an interpolation function (time is a variable) for interpolating between the digital data of interest and the digital data after one sampling time based on the data and the digital data before and after the data. Is determined, and each coefficient and the order t ¹ , t ² ,
····················································································································································································································································· デ ジ タ ル · An interpolation type DA converter can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a DA converter according to the present invention, FIGS. 2 (a) to (k) are explanatory diagrams of an interpolation function determining method, FIG. 3 is a block diagram of a function determining unit, and FIGS. Fig. 9 is a block diagram of a coefficient calculation unit, Fig. 9 is a block diagram of a coefficient selection unit, Fig. 10 is an embodiment of a multiplying DA converter, Fig. 11 is an embodiment of an analog order signal generation unit, Fig. 12 Is another embodiment of the analog order signal generator, FIG. 13 is another embodiment of the multiplying DA converter, FIG. 14 is an embodiment of the digital order data generator, and FIG. 15 is another embodiment of the multiplying DA converter 16 to 18 are waveform diagrams showing an interpolation function in the conventional system, FIG. 19 is a waveform diagram for explaining the conventional system, FIG. 20 to FIG. FIG. 23 is a block diagram of the proposed direct-interpolation DA converter. 21 ... Digital data output unit 22 ... Interpolation function determination unit 23 ... Coefficient calculation unit, 24 ... Latch unit 25 ... Slope check unit 26 ... Multiplication unit of multiplication type DA converter configuration 28 ... Adder

Claims (3)

(57) [Claims] A digital-to-analog converter for converting digital data into an analog signal by interpolating between digital data generated at a predetermined sampling time interval by an interpolation function and sequentially storing digital data generated at a predetermined sampling time interval. A digital data output unit that outputs one digital data as digital data of interest, outputs the digital data of interest, some digital data generated before the digital data of interest, and some digital data generated after the digital data of interest; Determining a higher-order interpolation function using a time t for interpolating between the digital data of interest stored in the digital data output unit and the digital data after one sampling time as a variable,
And an interpolation function determining unit for sequentially determining an interpolation function using digital data next to the current digital data of interest as new digital data of interest every sampling time; and an interpolation function output from the interpolation function determining unit for each sampling. each order t ^1, t ^2, order t ^1, t ² and the corresponding coefficient of ..., -
A plurality of multiplying DA converters for multiplying, an adder for adding the output of each multiplying DA converter and the conversion of the constant of the interpolation function to analog, and outputting the result. A slope calculator for calculating the slope, wherein the slope calculator calculates a slope at the current digital data position of interest of the interpolation function determined by the interpolation function determiner one sampling time ago; An interpolation function for interpolating between the current digital data of interest and the digital data after one sampling time is determined based on the digital data of interest, the digital data before and after the digital data of interest, and the calculated slope. Using the digital data following the data as new digital data of interest, the slope calculator calculates the slope and determines the interpolation function Determines the interpolation function, the multiplication type DA converters 1 each order t ¹ of the interpolation function that is output from the interpolation function determining unit for each sampling, t ^2, order t ^1, t ² corresponding to the coefficient of ..., ..Multiply by each adder
A DA converter characterized by adding the output of a DA converter output and a constant of an interpolation function converted to analog, and outputting the result. 2. The DA converter has an analog order signal generator for generating an analog signal in one sampling period of each order t ¹ , t ² ,..., And each of the multiplying DA converters has a digital coefficient and an analog order. 2. The DA converter according to claim 1, wherein the DA converter multiplies the signal. 3. The DA converter has an analog converter for converting each coefficient into analog, and a digital order generator for digitally generating n values of each order t ¹ , t ² ,... In one sampling period. 2. The DA converter according to claim 1, wherein each of said multiplying DA converters multiplies an analog coefficient by a digital order.