JP2647047B2 - Flip chip mounting method for semiconductor element and adhesive used in this mounting method - Google Patents
Flip chip mounting method for semiconductor element and adhesive used in this mounting methodInfo
- Publication number
- JP2647047B2 JP2647047B2 JP7041541A JP4154195A JP2647047B2 JP 2647047 B2 JP2647047 B2 JP 2647047B2 JP 7041541 A JP7041541 A JP 7041541A JP 4154195 A JP4154195 A JP 4154195A JP 2647047 B2 JP2647047 B2 JP 2647047B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- adhesive
- semiconductor element
- central portion
- mounting method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2733—Manufacturing methods by local deposition of the material of the layer connector in solid form
- H01L2224/27334—Manufacturing methods by local deposition of the material of the layer connector in solid form using preformed layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Adhesives Or Adhesive Processes (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子の実装方法
おびこの実装方法に用いられる接着剤に関し、特に、半
導体素子のフリップチップ実装方法およびこの実装方法
に用いられる接着剤に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor device and an adhesive used for the mounting method, and more particularly to a method for mounting a semiconductor device on a flip chip and an adhesive used for the mounting method.
【０００２】[0002]
【従来の技術】従来、半導体素子のフリップチップ実装
方法では、半導体素子に設けられたバンプと、基板に設
けられた基板パッドとを電気的に接続させる。そして半
導体素子と基板間に液状接着剤等により機械的に接続
し、半導体素子を基板に実装する。2. Description of the Related Art Conventionally, in a flip chip mounting method for a semiconductor element, a bump provided on the semiconductor element is electrically connected to a substrate pad provided on a substrate. Then, the semiconductor element and the substrate are mechanically connected with a liquid adhesive or the like, and the semiconductor element is mounted on the substrate.
【０００３】この種のフリップチップ実装方法は、半導
体素子にボンディングワイヤ等の端子を形成させる実装
方法と比較して端子を必要としないため、半導体素子実
装後の実装構造における基板上の半導体素子の実装密度
が高いという効果を奏する。[0003] This type of flip-chip mounting method does not require any terminals as compared with a mounting method in which terminals such as bonding wires are formed on a semiconductor element. This has the effect of increasing the mounting density.
【０００４】図４は、従来の半導体素子のフリップチッ
プ実装方法を示す工程図である。FIG. 4 is a process chart showing a conventional flip-chip mounting method for a semiconductor device.
【０００５】まず図４工程（ａ）において、ガラスエポ
キシ樹脂からなる基板１を基板パッド２側を上にして配
置する。基板パッド２は基板１上の配線に電気的に接続
される。続いて工程（ｂ）において、この基板パッド２
上にはんだペーストを印刷するかはんだメッキを付け
る。そして、工程（ｃ）において、金からなるバンプ５
が形成された半導体素子４を、バンプ５とはんだ６とが
接触するようにして重ね合わせ、工程（ｄ）において、
外部より熱を加えることにより、基板パッド２とバンプ
５とをはんだ付けする。この工程により、基板１と半導
体素子４とを仮接続するとともに電気的に接続する。こ
のような工程は、例えば特開昭５９−３５４３９号公報
に記載されている。First, in step (a) of FIG. 4, a substrate 1 made of glass epoxy resin is arranged with the substrate pad 2 side facing upward. The substrate pads 2 are electrically connected to wiring on the substrate 1. Subsequently, in step (b), the substrate pad 2
Print solder paste or apply solder plating on top. Then, in the step (c), the bump 5 made of gold is used.
Are stacked such that the bumps 5 and the solders 6 are in contact with each other. In the step (d),
The board pad 2 and the bump 5 are soldered by applying heat from the outside. In this step, the substrate 1 and the semiconductor element 4 are temporarily connected and electrically connected. Such a process is described in, for example, JP-A-59-35439.
【０００６】さらに、工程（ｅ）において、半導体素子
４上のバンプ５が形成されていない部分より、エポキシ
樹脂からなる液状の封止樹脂７を基板１と半導体素子４
との間に注入する。その後、外部より熱を加ることによ
り、この封止樹脂７を固着させ、基板１と半導体素子４
とを機械的に接続する。Further, in the step (e), a liquid sealing resin 7 made of epoxy resin is applied to the substrate 1 and the semiconductor element 4 from a portion of the semiconductor element 4 where the bumps 5 are not formed.
Inject between. Thereafter, the sealing resin 7 is fixed by applying heat from the outside, and the substrate 1 and the semiconductor element 4 are fixed.
Are connected mechanically.
【０００７】[0007]
【発明が解決しようとする課題】従来の半導体素子のフ
リップチップ実装方法では、液状の封止樹脂を基板と半
導体素子との間に注入することにより基板と半導体素子
とを接続するため、封止樹脂の注入時に樹脂に空気が混
入し、樹脂の固着時には気泡が形成される。この気泡は
接着力を弱くするので、、半導体素子の基板への実装
後、基板がはがれやすくなるという問題が生じる。In the conventional flip-chip mounting method for a semiconductor element, a liquid sealing resin is injected between the substrate and the semiconductor element to connect the substrate and the semiconductor element. Air is mixed into the resin when the resin is injected, and bubbles are formed when the resin is fixed. Since the bubbles weaken the adhesive force, there is a problem that the substrate is easily peeled after the semiconductor element is mounted on the substrate.
【０００８】また、基板がガラスエポキシ樹脂から構成
される場合、耐熱性が弱いため、基板と半導体素子との
はんだ付けの際の加熱により、基板が変形するという課
題が生じる。Further, when the substrate is made of glass epoxy resin, heat resistance is weak, so that there is a problem that the substrate is deformed by heating at the time of soldering the substrate and the semiconductor element.
【０００９】さらに、封止樹脂が液状のため、所定量の
樹脂を注入することが難しく、また、注入時に液漏れ等
により作業現場が汚れるという課題が生じる。Furthermore, since the sealing resin is liquid, it is difficult to inject a predetermined amount of the resin, and there is a problem that the work site becomes dirty due to liquid leakage or the like during the injection.
【００１０】本発明の目的は、上述した課題を解決し、
実装工程を簡略化し、量産性に富む半導体素子のフリッ
プチップ実装方法を提供することにある。An object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a flip-chip mounting method of a semiconductor element which simplifies a mounting process and has high productivity.
【００１１】[0011]
【課題を解決するための手段】上述した目的を達成する
ために、本発明では、半導体素子に形成されたバンプと
基板上に形成された基板パッドとを接続することにより
半導体素子を基板上に実装する半導体素子のフリップチ
ップ実装方法において、中央部が隆起した固形接着剤を
基板に圧着する第１のステップと、固形接着剤を半導体
素子に圧着する第２のステップと、バンプと基板パッド
とを電気的に接続する第３のステップと、固形接着剤に
熱を加えることにより基板と半導体素子とを固着する第
４のステップとを備える。In order to achieve the above-mentioned object, according to the present invention, a semiconductor device is mounted on a substrate by connecting bumps formed on the semiconductor device and substrate pads formed on the substrate. In a flip chip mounting method of a semiconductor element to be mounted, a first step of pressing a solid adhesive whose central portion is raised to a substrate, a second step of pressing a solid adhesive to the semiconductor element, a bump and a board pad. And a fourth step of fixing the substrate and the semiconductor element by applying heat to the solid adhesive.
【００１２】そして、この固形接着剤は、基板と接触す
る第１の面の中央部が、半導体素子と接触する第２の面
の中央部よりも隆起しており、その組成はエポキシ系樹
脂からなる。In the solid adhesive, the center of the first surface in contact with the substrate is higher than the center of the second surface in contact with the semiconductor element. Become.
【００１３】[0013]
【作用】上記構成の採用により、本発明は、固形接着剤
を用い、さらにこの接着剤の中央部を隆起させて形成さ
せたため、接着剤の基板および半導体素子との圧着時に
接着剤の中央部と基板および半導体素子の中央部とがま
ず接触する。続いて、この接着剤の中央部から遠ざかる
方向に向かって接着剤と基板および半導体素子とが接触
するため、空気は内部に残らず、外側に除去される。With the above construction, the present invention uses a solid adhesive, and furthermore, the central part of the adhesive is raised so that the central part of the adhesive is pressed when the adhesive is pressed against the substrate and the semiconductor element. And the substrate and the central portion of the semiconductor element first contact. Subsequently, since the adhesive contacts the substrate and the semiconductor element in a direction away from the center of the adhesive, air is removed to the outside without remaining inside.
【００１４】また、粘性を有する固形接着剤に基板およ
び半導体素子を圧着するため、基板基板パッドとバンプ
との接続にはんだによる仮接続を必要としない。Further, since the substrate and the semiconductor element are pressure-bonded to the viscous solid adhesive, the connection between the substrate substrate pad and the bump does not require temporary connection by solder.
【００１５】さらにまた、接着剤が固形のため、使用す
ることが容易であり、かつ液状接着剤を使用しその注入
時の液漏れ等により作業現場が汚れるということもな
い。Furthermore, since the adhesive is solid, it is easy to use, and the work site is not stained by the use of a liquid adhesive due to liquid leakage at the time of injection.
【００１６】[0016]
【実施例】次に本発明について図面を参照して詳細に説
明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings.
【００１７】図１は、本発明の一実施例を示す半導体素
子のフリップチップ実装方法を説明するための図であ
る。FIG. 1 is a view for explaining a flip-chip mounting method of a semiconductor device according to an embodiment of the present invention.
【００１８】まず、図１工程（ａ）において、ガラスエ
ポキシ樹脂からなる基板１上には、基板上の配線に電気
的に接続される基板パッド２が設けられている。また、
後で詳述するフィルム状接着剤３をこの基板１の上方よ
り圧着する。この圧着により、接着剤３と基板２とが固
定される。First, in step (a) of FIG. 1, a substrate pad 2 electrically connected to wiring on the substrate is provided on a substrate 1 made of glass epoxy resin. Also,
A film adhesive 3 to be described in detail later is pressed from above the substrate 1. By this pressure bonding, the adhesive 3 and the substrate 2 are fixed.
【００１９】続いて同工程（ｂ）において、金からなる
バンプ５が形成された半導体素子４を、接着剤３を介し
て基板１に重ね合わせるようにして半導体素子４を接着
剤３に圧着する。このとき、接着剤３と半導体素子４と
が圧着されるとともに、基板パッド２とバンプ５とが接
触し、電気的に接続される。Subsequently, in the same step (b), the semiconductor element 4 on which the bumps 5 made of gold are formed is superposed on the substrate 1 via the adhesive 3 and the semiconductor element 4 is pressed to the adhesive 3. . At this time, the adhesive 3 and the semiconductor element 4 are pressed, and the substrate pads 2 and the bumps 5 come into contact with each other to be electrically connected.
【００２０】最後に同工程（Ｃ）において、外部より熱
を加えることにより、接着剤３が溶融、固着し、基板１
と半導体素子４とが強固に接続される。Finally, in the same step (C), the adhesive 3 is melted and fixed by applying heat from the outside, so that the substrate 1
And the semiconductor element 4 are firmly connected.
【００２１】次に、図２を用い、フィルム状接着剤３に
ついて詳述する。Next, the film adhesive 3 will be described in detail with reference to FIG.
【００２２】同図において、接着剤３には、中央部が最
大の厚みを有するように隆起３２および３３が形成され
ている。In the figure, bumps 32 and 33 are formed on the adhesive 3 so that the central portion has the maximum thickness.
【００２３】そのため、前述した図１工程（ａ）に示し
た基板１と接着剤３との圧着接続において、まず、接着
剤３の中央部が基板１の中央部と圧着する。そして、そ
の後の基板１と接着剤３との圧着は、基板１のおよび接
着剤３の中央部から外側の方向に向かって圧着されてい
く。また、図１工程（ｂ）の半導体素子４と接着剤３と
の圧着接続においても同様に、まず接着剤３および半導
体素子４の中央部とが圧着し、その後、半導体素子４お
よび接着剤３の中央部から外側の方向に向かって圧着さ
れていく。Therefore, in the above-mentioned press-fit connection between the substrate 1 and the adhesive 3 shown in the step (a) of FIG. 1, first, the central portion of the adhesive 3 is pressed against the central portion of the substrate 1. Then, in the subsequent pressure bonding of the substrate 1 and the adhesive 3, the substrate 1 and the adhesive 3 are pressed from the center of the adhesive 3 toward the outside. Similarly, in the press-fit connection between the semiconductor element 4 and the adhesive 3 in the step (b) of FIG. From the center to the outside.
【００２４】このような圧着工程において、接着剤３は
固形であり、またフィルム状で、さらに基板１あるいは
半導体素子４との圧着がその中央部から外側に向かって
なされるため、接着剤３の圧着にともない、空気は基板
１あるいは半導体素子４の外側に押し出される。このよ
うに、接着剤３と基板１あるいは半導体素子４とは隙間
なく圧着されるので、図１工程（ｃ）における加熱によ
り気泡が形成されるということはない。In such a pressure bonding step, the adhesive 3 is solid and in the form of a film, and the pressure bonding with the substrate 1 or the semiconductor element 4 is performed from the center to the outside, so that the adhesive 3 With the pressure bonding, air is pushed out of the substrate 1 or the semiconductor element 4. As described above, since the adhesive 3 and the substrate 1 or the semiconductor element 4 are pressure-bonded without any gap, bubbles are not formed by the heating in the step (c) of FIG.
【００２５】再び図２に戻って、隆起３２および３３の
うち、基板１と圧着する側の隆起３２の方が、半導体素
子４と圧着する側の隆起３３よりもその隆起の大きさが
大きい。このことは、基板１と半導体素子４との表面の
荒さ、すなわち起伏が、基板１の方が大きいためであ
る。基板１の方が表面の起伏が大きいため、半導体素子
４と比較して、空気がたまりやすい。したがって、前述
したような基板１と接着剤３との圧着時に空気を基板１
より押し出すためには、隆起３２の隆起を大きくした方
がよい。一方半導体素子４と圧着する隆起３３において
は、半導体素子３の表面の起伏が基板１と比較して小さ
いため、その隆起を小さくしても良い。ところで、隆起
３３の隆起も隆起３２と同様に大きくすると確実に空気
を半導体素子４より押し出すことができるが、フィルム
状接着剤３を製造する際、隆起が小さいほどその製造上
のバラツキを押さえることができるため、半導体素子４
と圧着する隆起３３の隆起は小さく形成させることが望
ましい。Returning to FIG. 2 again, of the ridges 32 and 33, the ridge 32 on the side pressed against the substrate 1 has a larger size than the ridge 33 on the side pressed against the semiconductor element 4. This is because the surface roughness of the substrate 1 and the semiconductor element 4, that is, the undulation is larger in the substrate 1. Since the surface of the substrate 1 has larger undulations, the air tends to collect more than the semiconductor element 4. Therefore, air is applied to the substrate 1 when the substrate 1 and the adhesive 3 are pressed as described above.
In order to extrude more, it is better to make the protrusion 32 larger. On the other hand, in the ridge 33 that is pressed against the semiconductor element 4, the undulation on the surface of the semiconductor element 3 is smaller than that of the substrate 1, and thus the ridge may be reduced. By the way, if the height of the protrusion 33 is made large as in the case of the protrusion 32, air can be reliably pushed out from the semiconductor element 4. However, when manufacturing the film adhesive 3, the smaller the height of the protrusion is, the more the manufacturing variation is suppressed. The semiconductor element 4
It is desirable that the ridge of the ridge 33 to be pressed is formed small.
【００２６】また、接着剤３は、本実施例ではエポキシ
系樹脂より構成されるが、熱が加えられたときに、低温
で溶融、固着すれば特に本実施例ではその組成を限定し
ない。Although the adhesive 3 is made of an epoxy resin in this embodiment, its composition is not particularly limited in this embodiment as long as it is melted and fixed at a low temperature when heat is applied.
【００２７】図３は、本発明の第２の実施例を示す半導
体素子のフリップチップ実装方法を説明するための図で
ある。FIG. 3 is a view for explaining a flip-chip mounting method of a semiconductor device according to a second embodiment of the present invention.
【００２８】まず、図３工程（ａ）において、接着剤３
の上方よりバンプ５が形成された半導体素子４を圧着す
ると、接着剤３と半導体素子４とが固定される。続いて
同工程（ｂ）において、基板パッド２が形成された基板
１を、接着剤３を介して半導体素子４に重ね合わせるよ
うにして基板１を接着剤３に圧着する。このとき、接着
剤３と基板１とが固定されるとともに、基板パッド２と
バンプ５とが接触し、電気的に接続される。最後に同工
程（Ｃ）において、外部より熱を加えることにより、接
着剤３が溶融、固着し、基板１と半導体素子とが機械的
に接続される。First, in step (a) of FIG.
When the semiconductor element 4 on which the bumps 5 are formed is pressed from above, the adhesive 3 and the semiconductor element 4 are fixed. Subsequently, in the same step (b), the substrate 1 on which the substrate pads 2 are formed is pressure-bonded to the adhesive 3 such that the substrate 1 is overlaid on the semiconductor element 4 via the adhesive 3. At this time, the adhesive 3 and the substrate 1 are fixed, and the substrate pads 2 and the bumps 5 come into contact with each other and are electrically connected. Finally, in the same step (C), by applying heat from the outside, the adhesive 3 is melted and fixed, and the substrate 1 and the semiconductor element are mechanically connected.
【００２９】この第２の実施例は、図１に示した第１の
実施例と比較して、接着剤３を半導体素子４に先に圧着
する点で相違する。このことは、本発明が、作業工程の
順番を問わないこと、すなわち、接着剤３を基板１ある
いは半導体素子４のどちらか先に圧着させても良いこと
を意味している。したがって、本発明は、作業現場にお
いて作業工程に選択性の幅をもたせることができる。The second embodiment is different from the first embodiment shown in FIG. 1 in that the adhesive 3 is pressed on the semiconductor element 4 first. This means that the present invention does not care about the order of the working steps, that is, the adhesive 3 may be pressed against either the substrate 1 or the semiconductor element 4. Therefore, the present invention can provide the work process with a range of selectivity at the work site.
【００３０】[0030]
【発明の効果】以上説明したように、本発明による半導
体素子のフリップチップ実装方法は、フィルム状の接着
剤を用い、さらに、この接着剤の中央部を隆起させて形
成させたため、接着剤の基板および半導体素子との圧着
時に空気が混入せず、半導体素子の実装後にその基板と
の接続部分に気泡が形成されることもない。したがっ
て、実装後の半導体素子は、基板からはがれにくい。As described above, the flip-chip mounting method for a semiconductor device according to the present invention uses a film-like adhesive, and furthermore, the center of the adhesive is raised to form the adhesive. No air is mixed when the substrate and the semiconductor element are pressed, and no air bubbles are formed at the connection portion with the substrate after the semiconductor element is mounted. Therefore, the semiconductor element after mounting is hard to peel off from the substrate.
【００３１】またガラスエポキシ樹脂等の耐熱性に弱い
素材から構成されている基板に半導体素子を実装させる
際にも、フィルム状接着剤に基板および半導体素子を圧
着することにより基板パッドとバンプとを電気接続させ
るため、はんだによる仮接続および電気的接続をを行わ
なくとも、フィルム状接着剤を介して基板およびパッド
と半導体素子およびバンプとが固定される。したがっ
て、はんだ工程を削減でき、はんだ溶融時の加熱によ
り、基板が変形するということがなく、さらに実装工程
を簡略化させることもできる。接着剤の溶融時の加熱
は、はんだ溶融時の加熱と比べて低温度であるので、基
板が変形することはない。Also, when mounting a semiconductor element on a substrate made of a material having low heat resistance such as glass epoxy resin, the substrate and the semiconductor element are pressed against a film adhesive so that the substrate pads and the bumps are separated from each other. In order to make the electrical connection, the substrate and the pad, the semiconductor element, and the bump are fixed via the film adhesive without performing the temporary connection and the electrical connection by the solder. Therefore, the number of soldering steps can be reduced, and the substrate is not deformed by heating when the solder is melted, and the mounting step can be further simplified. Since the heating during the melting of the adhesive is lower than the heating during the melting of the solder, the substrate is not deformed.
【００３２】さらにまた、フィルム状接着剤が固形のた
め、所定量の接着剤の使用も容易であり、かつ、液状接
着剤を使用しその注入時の液漏れ等により作業現場が汚
れるということもない。Further, since the film adhesive is solid, it is easy to use a predetermined amount of adhesive, and it is also possible to use a liquid adhesive and contaminate the work site due to liquid leakage at the time of injection. Absent.
【図１】本発明の一実施例を示す半導体素子のフリップ
チップ実装方法の実装工程を説明する工程図。FIG. 1 is a process diagram illustrating a mounting process of a flip-chip mounting method of a semiconductor device according to an embodiment of the present invention.
【図２】図１に示したフィルム状接着剤の詳細を説明す
る正面図。FIG. 2 is a front view illustrating details of the film adhesive shown in FIG. 1;
【図３】本発明の第２の実施例を示す半導体素子のフリ
ップチップ実装方法の実装工程を説明する工程図。FIG. 3 is a process diagram illustrating a mounting process of a flip-chip mounting method of a semiconductor device according to a second embodiment of the present invention.
【図４】従来の半導体素子のフリップチップ実装方法の
実装工程を説明する工程図。FIG. 4 is a process diagram for explaining a mounting process of a conventional flip-chip mounting method for a semiconductor element.
１ ・・・ 基板 ２ ・・・ 基板パッド ３ ・・・ フィルム状接着剤 ４ ・・・ 半導体素子 ５ ・・・ バンプ ６ ・・・ はんだ ７ ・・・ 封止樹脂 ３２ ・・・ 基板側隆起 ３３ ・・・ 半導体素子側微少な隆起 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Substrate pad 3 ... Film adhesive 4 ... Semiconductor element 5 ... Bump 6 ... Solder 7 ... Sealing resin 32 ... Substrate side protrusion 33 ... Small bumps on semiconductor device
Claims (10)
に形成された基板パッドとを接続することにより前記半
導体素子を前記基板上に実装する半導体素子のフリップ
チップ実装方法において、前記基板に接触する面の 中央部が隆起した固形接着剤を
前記基板に圧着する第１のステップと、 前記固形接着剤を前記半導体素子に圧着する第２のステ
ップと、 前記バンプと前記基板パッドとを電気的に接続する第３
のステップと、 前記固形接着剤に加熱することにより前記基板と前記半
導体素子とを固着する第４のステップと、 を備えることを特徴とする半導体素子のフリップチップ
実装方法。1. A method of mounting a semiconductor element on a substrate by connecting a bump formed on the semiconductor element to a substrate pad formed on the substrate, the method comprising: A first step of pressing a solid adhesive having a raised central portion of the surface to be bonded to the substrate, a second step of pressing the solid adhesive to the semiconductor element, and electrically connecting the bump and the substrate pad. Connect to the third
And a fourth step of fixing the substrate and the semiconductor element by heating to the solid adhesive. A flip chip mounting method for a semiconductor element.
る第５のステップと、 前記固形接着剤の前記中央部から遠ざかる方向に向かっ
て前記固形接着剤と前記基板とが順次圧着する第６のス
テップと、 を備えることを特徴とする請求項１記載の半導体素子の
フリップチップ実装方法。2. The first step, wherein: a fifth step in which a central portion of the solid adhesive and a central portion of the substrate are pressure-bonded; and a step away from the central portion of the solid adhesive. 6. The method according to claim 1, further comprising: a sixth step of sequentially pressing the solid adhesive and the substrate.
圧着する第７のステップと、 前記固形接着剤の前記中央部から遠ざかる方向に向かっ
て前記固形接着剤と前記半導体素子とが圧着する第８の
ステップと、 を備えることを特徴とする請求項１記載の半導体素子の
フリップチップ実装方法。3. The second step includes: a seventh step in which a central portion of the solid adhesive and a central portion of the semiconductor element are pressure-bonded; and a direction away from the central portion of the solid adhesive. 8. The method according to claim 1, further comprising: an eighth step in which the solid adhesive and the semiconductor element are pressure-bonded. 9.
子の実装方法において、前記基板に接触する面の中央部が隆起した 固形接着剤を
前記半導体素子と前記基板との間に挿入する第１のステ
ップと、 前記半導体と前記基板間の空気を排除する第２のステッ
プと、 前記固形接着剤に加熱することにより前記基板と前記半
導体素子とを固着する第３のステップと、 を備えることを特徴とする半導体素子の実装方法。 4. A method for mounting a semiconductor element on a substrate, the method comprising : inserting a solid adhesive having a raised central portion of a surface in contact with the substrate between the semiconductor element and the substrate. And a second step of removing air between the semiconductor and the substrate; and a third step of fixing the substrate and the semiconductor element by heating the solid adhesive. Characteristic semiconductor element mounting method.
を前記半導体素子に圧着する第４のステップと、 前記固形接着剤を前記基板に圧着する第５のステップ
と、 を含むことを特徴とする請求項４記載の半導体素子の実
装方法。5. The method according to claim 1, wherein the second step includes a fourth step of pressing the solid adhesive to the semiconductor element, and a fifth step of pressing the solid adhesive to the substrate. The method for mounting a semiconductor device according to claim 4.
れる接着剤において、 前記接着剤が、中央部が隆起した固形の接着剤であるこ
とを特徴とする半導体実装用接着剤。6. An adhesive used for mounting a semiconductor element on a substrate, wherein the adhesive is a solid adhesive having a raised central portion.
面の中央部が前記半導体素子と接触する第２の面の中央
部よりも隆起していることを特徴とする請求項６記載の
半導体実装用接着剤。7. The adhesive according to claim 6, wherein a central portion of the first surface in contact with the substrate is higher than a central portion of the second surface in contact with the semiconductor element. Adhesive for semiconductor mounting.
ることを特徴とする請求項６記載の半導体実装用接着
剤。8. The adhesive according to claim 6, wherein the adhesive is formed in a film shape.
からなることを特徴とする請求項６記載の半導体実装用
接着剤。9. The adhesive according to claim 6, wherein the adhesive is made of a resin that melts and adheres at a low temperature.
ことを特徴とする請求項９記載の半導体実装用接着剤。10. The semiconductor mounting adhesive according to claim 9, wherein said adhesive is made of an epoxy resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7041541A JP2647047B2 (en) | 1995-03-01 | 1995-03-01 | Flip chip mounting method for semiconductor element and adhesive used in this mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7041541A JP2647047B2 (en) | 1995-03-01 | 1995-03-01 | Flip chip mounting method for semiconductor element and adhesive used in this mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08236578A JPH08236578A (en) | 1996-09-13 |
| JP2647047B2 true JP2647047B2 (en) | 1997-08-27 |
Family
ID=12611288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7041541A Expired - Lifetime JP2647047B2 (en) | 1995-03-01 | 1995-03-01 | Flip chip mounting method for semiconductor element and adhesive used in this mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2647047B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6333206B1 (en) * | 1996-12-24 | 2001-12-25 | Nitto Denko Corporation | Process for the production of semiconductor device |
| JPH11186326A (en) | 1997-12-24 | 1999-07-09 | Shinko Electric Ind Co Ltd | Semiconductor device |
| JP3625646B2 (en) | 1998-03-23 | 2005-03-02 | 東レエンジニアリング株式会社 | Flip chip mounting method |
| JP3957244B2 (en) * | 1998-07-17 | 2007-08-15 | 日東電工株式会社 | Manufacturing method of semiconductor devices |
| US6410415B1 (en) | 1999-03-23 | 2002-06-25 | Polymer Flip Chip Corporation | Flip chip mounting technique |
| JP3451373B2 (en) | 1999-11-24 | 2003-09-29 | オムロン株式会社 | Manufacturing method of data carrier capable of reading electromagnetic wave |
| AU5285101A (en) * | 2000-04-06 | 2001-10-23 | Cintech Ad Venture Pte Ltd | Process and assembly for applying an adhesive to a substrate |
| JP5429092B2 (en) * | 2010-07-21 | 2014-02-26 | 株式会社デンソー | Semiconductor device and manufacturing method of semiconductor device |
| JP6161411B2 (en) * | 2012-06-22 | 2017-07-12 | キヤノン株式会社 | Method for manufacturing liquid ejection device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62169433A (en) * | 1986-01-22 | 1987-07-25 | Fuji Xerox Co Ltd | Manufacture of semiconductor device |
| JP2676828B2 (en) * | 1988-09-30 | 1997-11-17 | 株式会社デンソー | Manufacturing method of hybrid integrated circuit device |
-
1995
- 1995-03-01 JP JP7041541A patent/JP2647047B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08236578A (en) | 1996-09-13 |
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