JP2640871B2 - Virtual computer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a virtual computer system including a scalar unit and a vector unit, in this kind of virtual computer system, an efficient virtual computer mechanism capable of running different OSs on different processors For the purpose of realizing the above, the number of duplicate registers equal to the number of scalar units sharing the vector unit is provided on the output port side of the vector register address generator, and each duplicate register is associated with a scalar unit. The register holds the value of the address base register and the value of the address limit register of the corresponding scalar unit.

[Industrial applications]

The present invention relates to a virtual computer system including a scalar unit and a vector unit.

With the development of vector processing devices in recent years, there are a plurality of OSs that can use the vector processing mechanism, and a virtual machine mechanism that runs a plurality of OSs simultaneously is required. In a multi-processor in which the main memory is shared by a plurality of vector processing devices, it is necessary to be able to operate different virtual machines for each vector processing device in order to run a different OS that can use a vector processing mechanism for each processor. is there.

[Conventional technology]

As a method of realizing a virtual machine mechanism in a conventional vector processing apparatus, a copy of an address base register / address limit register existing in a scalar unit is provided in a vector unit, and an address base register is copied by a scalar instruction. It has already been proposed to execute and set a duplicate register of a vector unit as a HARD instruction when setting a register / address limit register (see Japanese Patent Application No. 1-177640).

However, depending on the mode, the vector computer system can operate as either a multiprocessor system in which each vector unit of the replica follows a separate scalar unit, or as a uniprocessor system that operates in parallel according to one scalar unit. No. 1-181377)
Or a vector computer system (Japanese Patent Laid-Open No. 2-127768) in which a vector access processing unit is composed of a plurality of systems and a vector address generation unit and a main memory priority control unit of all systems are synchronously controlled. , A set of address base registers / addresses for the vector unit
Since it had only a limit register, a virtual machine mechanism that could function effectively in any mode could not be realized.

[Problems to be solved by the invention]

Therefore, for example, in the case of a multi-processor, there is a problem that a domain of a common virtual machine must be accessed.

An object of the present invention is to realize an efficient virtual machine mechanism that can run different OSs on different processors in the above-described complex vector processing system.

[Means for solving the problem]

FIG. 1 is an explanatory view of the principle of the invention of claim (1). In the virtual machine system according to the present invention, a plurality of vector processors VP each including a scalar unit SU for processing scalar instructions and a vector unit VU for processing vector instructions share a main storage device. In the virtual machine system, a copy register RR for holding an address base for the virtual machine and an address limit is provided for each vector unit VU, and an address base is stored in the control register ABR / ALR of the scalar unit SU. When the address limit is set,
Vector unit corresponding to the scalar unit SU
A feature is provided in which means for updating the value of the VU copy register RR is provided.

FIG. 2 is an explanatory view of the principle of the invention of claim (2). The virtual machine system according to the invention of claim (2) is accessed by a vector processor VP comprising a scalar unit SU for processing scalar instructions and a plurality of vector units VU for processing vector instructions, and a vector processor VP. A virtual computer system including a main storage device MSU, which is provided with a copy register RR for holding an address base and an address limit for the virtual computer for each vector unit VU, and connected to the scalar unit SU. Each of the vector units VU has a mechanism 50, 52 for setting a mode in which one vector instruction processing division unit is processed in parallel. Under this mode state, the address register is stored in the control register ABR / ALR of the scalar unit SU. Base and address
If a limit is set, the scalar unit
A means for simultaneously updating the values of the copy registers RR of all the vector units VU connected to the SU is provided.

FIG. 3 is an explanatory view of the principle of the invention of claim (3). A virtual computer system according to claim 3, wherein the plurality of scalar units SU share one vector unit VU or a vector unit set including a plurality of vector units VU. And for each vector unit VU,
For each scalar unit SU that shares a VU, a duplicate register RR that holds the address base and address limit for the virtual machine is provided, and a scalar unit (SU) control register (ABR / ALR)
When an address base and an address limit are set for each vector unit,
The unit (VU) has means for updating the copy register (RR) corresponding to the scalar unit (SU).

FIG. 4 is a view for explaining the principle of the invention of claim (4). A virtual computer system according to a fourth aspect of the present invention is the virtual computer system according to the third aspect, wherein each of the scalar units SU sharing the vector unit is provided for each address generation unit ADRS of each vector unit. A copy register RR that holds the address base and address limit is provided in response to, and the hypervisor mode HPV is added to the tag of the vector instruction sent from each scalar unit SU to the vector unit VU to control the vector instruction. The unit Vi has a means for sending a main memory access instruction to the address generation unit ADRS by adding address creation information, a hypervisor mode HPV, and a scalar unit number for identifying a scalar unit (SU). The address generation unit ADRS has a means for issuing a request for a required vector length to the storage control device. However, when the hypervisor mode HPV is ON, the storage controller MCU does not perform the address clogging based on the address base of the duplicate register RR and does not perform the address limit check based on the address limit of the duplicate register RR. When the hypervisor mode HPV is off, the copy register RR specified by the scalar unit number
Based on the address base and address limits of
It is characterized by having means for putting on the address clogs and checking the address limit.

[Action]

The operation of the virtual machine system according to the present invention will be described. According to the invention of claim (1), since the copy register RR holding the address base and the address limit is provided for each vector unit VU, a different value can be set for each vector processor VP. Therefore, it is possible to assign a different virtual machine domain to each vector processor VP. As a result, each vector processor VP can independently execute an OS that can use the vector unit, and different OSs share main memory and I / O to perform high-speed data transfer between OSs. As a completely different computer, the virtual computer can function with almost no overhead.

The operation of the virtual machine according to the invention of claim (2) will be described. In the virtual machine system shown in FIG. 2, the address generators of the two vector units VU are connected to the same scalar unit SU. When an instruction for setting the address base register / address limit register ABR / ALR is issued in the scalar unit SU, the vector instruction control unit of the upper vector unit VU is sent from the scalar unit SU. Sends the incoming address base value, address limit value, and ABR / ALR setting instruction for setting data to the duplicate register RR to the address generator, and starts the connected address generator. . Address base value, address
The limit value and the ABR / ALR setting instruction are sent to the copy register RR via the address generator. Duplicate register RR
Are the address base value, address limit value and
When the ABR / ALR setting instruction is received, the value of the copy register RR is updated. In the virtual computer system according to the invention of claim (2), since all of the copy registers of the vector unit connected to the scalar unit SU are updated at the same time, the efficiency is not impaired and the control is simple (originally, In the mode, the structure is such that a plurality of address generators can be activated simultaneously.) Therefore, a loss due to having a plurality of duplicate registers RR holding the address base and the address limit does not occur, and a configuration having a vector unit with high parallelism in a multiprocessor is possible.

The operation of the virtual machine system according to the invention of claim (3) will be described. In the virtual machine system according to the third aspect of the present invention, a copy register RR is provided for each of the plurality of scalar units sharing the vector unit VU. An address base and an address limit are set in the copy register RR. In the example of FIG. 3, two copy registers RR are connected to the address generation unit. The upper copy register corresponds to the upper scalar unit SU, and the lower copy register corresponds to the lower scalar unit SU. Compatible with unit SU. Address base register / address limit register of scalar unit SU
When setting the ABR / ALR, all the copy registers RR corresponding to the scalar unit SU are updated. In the virtual computer system according to the invention of claim (3), the vector unit VU
It is efficient because it is not necessary to reset the address base and address limit in the duplicate register RR every time the exclusive use right is switched, the ABR / ALR setting instruction in the vector unit is set to HARD-OP, and the scalar It can be controlled by moving the unit away from the vector unit (Japanese Patent Laid-Open No. 2-76069). Also in the virtual computer system according to the invention of claim (3), a different domain can be set for each scalar unit, and each vector processor can flow an OS capable of using a vector unit independently, and different OSs are mainly used. While sharing storage and I / O to perform high-speed data transfer between OSs, it is possible to function as a completely separate computer with little overhead of a virtual computer.

The operation of the virtual machine system according to the invention will be described. In the virtual machine system according to the present invention, a scalar unit number SU and a hypervisor mode HPV are added for each access request.
In the virtual machine system according to the present invention, a scalar processor constituting a dual scalar unit processor is provided.
Each of the units can switch between the VM mode and the hypervisor mode without being aware of the other scalar units at all, and furthermore, a so-called mixed mode in which vector instructions of each scalar unit are mixed without serialization. Can operate in mode.

〔Example〕

FIG. 5 is a block diagram of one embodiment of the present invention, and shows a multi-vector virtual computer system covering all of claims (1) to (4). In the figure, SU
0 to SU3 are scalar units, VU0 and VU1 are vector
Unit, Vi0 and Vi1 are vector instruction control units, ADRS0 and RDR
S1 is the address generator, MCU is the storage controller, PRIORITY is the priority circuit, MSU is the main storage, R01 to R05
Is a tag register, R21 to R25 are also tag registers, 10
And 12 are selectors, 20 and 22 are switch circuits, 30 and 32 are data registers, 40 and 42 are merge circuits, 50 and 52 are selectors, and 60 and 62 are start address registers / distance registers.
Address registers, 70 to 73 are selectors, 80 to
83 is a logical address holding register, 90 to 93 are index registers, 100 to 103 are adders, 110 to 113
Is a logical address register, 120 to 123 are address conversion registers, 130 to 133 are merge circuits, 150 to 153
Is a request address register, 160 to 163 are adders, 170 to 173 are selectors, 180 to 183 are merge circuits, 190 to 193 are addressing exception check circuits,
200 to 203 are duplicate registers for holding the address base and address limit of the scalar unit, 210
Reference numerals 213 indicate selectors.

Scalar unit SU0 and scalar unit SU1 are connected to vector instruction control unit Vi0 of vector unit VU0.
The scalar unit SU2 and the scalar unit SU3 are connected to the vector instruction control unit Vi1 of the vector unit VU1.

When the vector main memory access instruction is detected, the scalar unit SU0 sends the detected vector main memory access instruction, address creation information (head address, distance, index, etc.), vector length, and the like to the vector instruction control unit Vi. . When setting or updating the contents of its own address base register / address limit register, the scalar unit uses control information or ABR / ALR setting instruction and address base value for the vector unit. And the address limit value to the vector unit. The details are disclosed in Japanese Patent Application No. 1-177640. Other scalar units SU1 to SU3
Performs a similar operation.

Since the vector unit VU0 and the vector unit VU1 have the same configuration, the vector unit VU0 will be mainly described.

The vector unit VU0 has a vector instruction control unit Vi0 and an address generation unit ADRS0. The vector instruction control unit Vi0 includes a selector 10, a switch circuit 20, a data register 30, a merge circuit 40, a duct register R01, and the like. The data transmitted from the scalar unit SU0 and the data transmitted from the scalar unit SU1 are input to the selector 10, and the input data specified by the switch circuit 20 is output from the selector 10. The switch circuit 20 instructs the selector 10 which input data should be selected. For example, when the switch circuit 20 indicates 0, the data sent from the scalar unit SU0 is output from the selector 10, and when it indicates 1, the data output from the scalar unit SU1 is output from the selector 10. The scalar unit number is output from the switch circuit 20, and the scalar unit number is input to the tag register R01. The scalar unit number corresponds to a selection instruction signal sent from the switch circuit 20 to the selector 10. Data register 30 contains
Address creation information (head address, distance, index) and control information are set. The control information includes a hypervisor bit, an operation code, a part of the PSW, and the like. The hypervisor bit specifies whether or not the mode is the hypervisor mode. Tag register
The scalar number of R01 and the control information of the data register 30 are input to the merge circuit 40, and the merge circuit 40 outputs tag information including a scalar unit number and control information.

The address generator ADRS0 has a selector 50.
The upper input terminal of the selector 50 is connected to the output of the data register 30 of the vector instruction control unit Vi0, and the lower input terminal is connected to the output of the data register 32 of the vector instruction control unit Vi1. The data output from the selector 50 is
It is set in the start address register / distance register 60. , And 130 constitute a 0-side address pipeline, and 71, 81,..., And 131 constitute a 1-side address pipeline.
In the case of block access, the address pipeline on the 0 side is used. In the case of distance access or indirect access, the address pipeline on the 0 side and the address pipeline on the 1 side are used alternately. You. There are two address conversion registers 120, and the one specified by the scalar unit number is used. The same applies to the address conversion registers 121, 122 and 123.
The address pipeline is described in detail in JP-A-61-264455, and a description thereof will be omitted.

Tag information from the merge circuit 40 is input to the upper input terminal of the selector 140, and tag information from the merge circuit 42 is input to the lower input terminal of the selector 140. Selector 14
The tag information output from 0 is the duck register R02, R03, R
It is sent to the storage control unit MCU via 04. The selector 50 and the selector 140 perform the same operation. That is, when the selector 50 selects the data of the upper input terminal, the selector 140 also selects the data of the upper input terminal, and when the selector 50 selects the data of the lower input terminal, the selector 140 also selects the data of the lower input terminal. I do.

The storage control unit MCU will be described. Storage control unit MCU
The request address from the merge circuit 130 of the address generator ADRS0 is set in the request address register 150 of the address generator 150. Request address register 150
And the address base output from the selector 210 are added by the adder 160. Adder 160
And the upper address of the request address register 150 are input to the selector 170. The selector 170 selects the upper input data when the hypervisor bit is 0, and selects the upper input data when the hypervisor bit is 1. Select the lower input data. The output of the selector 170 and the lower address of the request address register 150 are merged by a merge circuit 180. The address designation exception check circuit 190 outputs 1 when the address (system absolute address) from the merge circuit 180 exceeds the address limit from the selector 211.

The request address from the merge circuit 131 of the address generator ADRS0 is set in the request address register 151. Request address register 151
The upper address and the address base are added by an adder 161 and the addition result and the request address register 151
Is input to the selector 171 and the selector 1
The output of 71 and the lower address of the request address register are merged by a merge circuit 181, and an address specification exception check circuit 191 determines whether or not the output (system absolute address) of the merge circuit 181 exceeds an address limit.
Will be checked by.

The tag information of the tag register R05 includes a scalar unit number and control information (hypervisor bit, opcode, part of PSW, etc.). When the hypervisor bit is 0, the selector 170 selects the upper input data. When the hypervisor bit is 1, the selector 170 selects the upper input data.
170 selects the lower input data. The selector 171 performs the same operation as the selector 170.

In the selector 210, the address base of the copy register 200 is input to the upper input terminal, and the address base of the copy register 201 is input to the lower input terminal of the selector 210. The address limit of the copy register 200 is input to the upper input terminal of the selector 211, and the address limit of the copy register 201 is input to the lower input terminal of the selector 211.

If the hypervisor bit of the tag register R05 is 0 and the scalar unit number is 0, the selector 210 selects the upper input data, and if the hypervisor bit of the tag register R05 is 0 and the scalar unit number is In the case of 1, the selector 210 selects the lower input data. The selector 211 performs the same operation as the selector 210.

If the opcode indicates ABR / ALR setting,
The register 200 and the register 201 enter the write enable state. ABR / ALR stands for address base register / address limit register. When ABR / ALR is set, the address base and address limit are set to 0.
Flows through the side address pipeline. When the scalar unit number in the tag information is 0 under the ABR / ALR setting state, the address base and the address limit from the merge circuit 130 are set in the copy register 200, and the scalar in the tag information is set. When the unit number is 1, the address base and the address limit from the merge circuit 130 are set in the copy register 201.

The portions 152 to 212 and the portions 153 to 213 in the storage controller MCU are portions corresponding to the address generator ADRS1. The portions 152 to 212 and the portions 153 to 213 perform the same operations as the portions 150 to 210 and the portions 151 to 211.

The system of FIG. 5 can constitute various types of DSUPs (dual scalar unit processors). With the system of FIG. 5, two DSUPs can be realized. In this case, scalar unit SU0, scalar unit
One DSUP with unit SU1 and vector unit VU0
And scalar unit SU2 and scalar unit SU3
And one other DSUP is constituted by the vector unit VU1. Vector unit VU0 selector 50 and selector 1
40 selects the upper input data and the vector unit VU
The selectors 52 and 142 select the lower input data. DSUP consisting of scalar unit SU0, scalar unit SU1, and vector unit VU0, and scalar unit SU2, scalar unit SU3, and vector
Since the operation of the DSUP configured by the unit VU1 is the same, the operation of the DSUP configured by the scalar unit SU0, the scalar unit SU1, and the vector unit VU0 will be described.

Scalar unit SU0 is an ABR / ALR setting instruction, address
When the base value and the address limit value are sent to the vector unit VU0, the address base value and the address limit value are set in the copy register 200. Similarly, when the scalar unit SU1 sends the ABR / ALR setting instruction, address base value, and address limit value to the vector instruction control unit Vi0, these address base value and address limit value are set in the copy register 201. Is done.

Scalar unit SU0 or SU1 stores vector main memory access instruction, address creation information, etc. in vector unit VU
When it is sent to 0, the request address is output from the address generator ADRS0. When the request address from the address generator ADRS0 is based on the instruction and data from the scalar unit SU0, the duplicate register 200 is selected. Request from the address generator ADRS0
If the address is based on an instruction and data from scalar unit SU1, duplicate register 201 is selected.

The scalar unit SU0, scalar unit
One DSUP can be configured by the unit SU1, the vector unit VU0, and the vector unit VU1. In this case, selector 50 and selector 1 of vector unit VU0
40 selects the upper input data and the vector unit VU
The selectors 52 and 142 also select the upper input data. Scalar unit SU2 and scalar unit SU3
Works without vector units.

DSU composed of scalar unit SU0, scalar unit SU1, vector unit VU0, and vector unit VU1
The operation of P will be described. Scalar unit SU0 is ABR /
When the ALR setting instruction, the address base value, and the address limit value are sent to the vector unit VU0, the address base value and the address limit value are set in the copy registers 200 and 202. Similarly, scalar unit S
When U1 sends the ABR / ALR setting instruction, the address base value and the address limit value to the vector instruction control unit Vi0, these address base value and address limit value are set in the copy registers 201 and 203.

Scalar unit SU0 or SU1 stores vector main memory access instruction, address creation information, etc. in vector unit VU
When it is sent to 0, the request address is output from the address generators ADRS0 and ADRS1. When the request address from the address generator ADRS0 is based on the instruction and data from the scalar unit SU0, the copy register
If the request address 200 is selected and the request address from the address generator ADRS0 is based on the instruction and data from the scalar unit SU1, the duplicate register 201 is selected. If the request address from the address generation unit ADRS1 is based on the instruction and data from the scalar unit SU0, the duplication register 202 is selected, and the request address from the address generation unit ADRS1 is converted to the scalar unit SU1. If the instruction is based on the instruction and data from the CPU, the duplication register 203 is selected.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, a DSUP system can be used for both a vector multiprocessor and a vector uniprocessor in a mode in which a plurality of vector units are operated in parallel. Also DS
A virtual computer that can operate different OSs that can use the vector processing mechanism for each vector processor, taking advantage of TCMP, even for the mixed mode of the UP and for the multi-processor effectively. The system can be realized.

[Brief description of the drawings]

1 to 4 are explanatory diagrams of the principle of the present invention, and FIG. 5 is a block diagram of one embodiment of the present invention. SU0 to SU3 ... Scalar unit, VU0 and VU1 ... Vector unit, Vi0 and Vi1 ... Vector instruction control unit, AD
RS0 and ADRS1 address generator, MCU storage controller, PRIORITY priority circuit, MSU main memory, R01 to R05 tag registers, R21 to R25
…… tag registers, 10 and 12 …… selectors, 20 and 22 ……
Switch circuits, 30 and 32 ... data registers, 40 and 42 ...
... Merging circuit, 50 and 52 ... Selector, 60 and 62 ... Start address register / distance address register, 70 to 73 ... Selector, 80 to 83 ... Logical address holding register, 90 to 93 ... Index Registers, 100 to 103: Adders, 110 to 113: Logical address registers, 120 to 123: Address conversion registers, 130 to 133: Merge circuit, 150 to 153 ...
… Request address register, 160 to 163 ……
Adder, 170 to 173 ... selector, 180 ... merge circuit, 190 to 193 ... addressing exception check circuit,
200 to 203... Duplicate registers holding the address base and address limits, 210 to 213.

Claims (4)

(57) [Claims] 1. A virtual machine shared by a main storage device, wherein a plurality of vector processors (VP) each comprising a scalar unit (SU) for processing scalar instructions and a vector unit (VU) for processing vector instructions. In the system, for each vector unit (VU), a copy register (RR) for holding an address base and an address limit for a virtual machine is provided, and a control register (ABR / ABR / SCR) for a scalar unit (SU) is provided. When the address base and the address limit are set in the ALR, a means for updating the value of the copy register (RR) of the vector unit (VU) corresponding to the scalar unit (SU) is provided. A virtual computer system. 2. A vector processor (VP) comprising a scalar unit (SU) for processing scalar instructions and a plurality of vector units (VU) for processing vector instructions.
A virtual machine system comprising a main storage unit (MSU) accessed by a vector processor (VP), and for each vector unit (VU), holding an address base and an address limit for the virtual machine. A copy register (RR) is provided, and a mechanism (50, 52) is provided for setting the vector unit (VU) connected to the scalar unit (SU) to a mode in which one vector instruction processing division unit is processed in parallel. If the address base and the address limit are set in the control register (ABR / ALR) of the scalar unit (SU) under this mode state, all of the connected scalar units (SU) Vector unit (V
A virtual computer system comprising means for simultaneously updating the value of a duplicate register (RR) in U). 3. A virtual computer system in which a plurality of scalar units (SU) share one vector unit (VU) or a vector unit set composed of a plurality of vector units (VU). For each vector unit (VU), a copy register holding an address base and an address limit for the virtual machine corresponding to each of the scalar units (SU) sharing the vector unit (VU). (RR), and when the address base and address limit are set in the control register (ABR / ALR) of the scalar unit (SU), the corresponding scalar in each vector unit (VU) belonging to the vector unit set -A virtual computer system provided with means for updating a replication register (RR) corresponding to a unit (SU). 4. The virtual computer system according to claim 3, wherein each address generation unit (ADRS) of each vector unit comprises:
For each scalar unit (SU) sharing the vector unit, a duplicate register (RR) that holds the address base and the address limit is provided, and the scalar unit (SU) converts the vector unit ( V
Hypervisor mode (HPV) is added to the tag of the vector instruction to be sent to U), and the vector instruction control unit (Vi) uses the address generation unit (ADRS)
Address generation information, hypervisor mode (HPV), and means for adding a scalar unit number for identifying a scalar unit (SU) and transmitting a main memory access instruction. ADRS) has a means for issuing a request for a required vector length to the storage controller, and the storage controller (MCU) operates in the hypervisor mode (HP
When V) is on, the address clogging of the address based on the duplicated register (RR) and the address limit check by the address limit of the duplicated register (RR) are not performed, and the hypervisor mode (HPV) is used.
When is off, there is a means to carry out address clogging and address limit checking based on the address base and address limit of the duplicate register (RR) specified by the scalar unit number. Characterized virtual computer system.