JP2636746B2 - I / O cache - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output cache in an input / output processing device located between a central processing unit and an input / output device.

[0002]

2. Description of the Related Art An input / output cache is a small-capacity, high-speed memory provided as a storage hierarchy level between a main storage device and an input / output device. Provides fast access to output devices. In a conventional cache memory, as a method of selecting block data to be replaced when a cache miss occurs, for example, a random method or an LRU (Least Re
cently Used) method. The random method is a method of randomly determining which block is to be replaced next by using a random number literally. According to this random method, replacement control hardware can be realized with a simple configuration. In addition, the LRU method is used to prevent a block storing high-necessity data among valid data blocks from being flushed to main memory.
Record the access status to each block in the cache,
In this method, the data of the block that has not been accessed for the longest time is to be replaced. According to the LRU method, a frequently used block remains in the cache, so that efficient data transfer can be performed.

[0003] These conventional block replacement methods are described in, for example, "Nagashima, Horikoshi: Cache Storage, Information Processing, Vol. 21, No. 4, pp. 332-340 (April 1980)".
Can be referred to.

[0004]

However, in the conventional random method, even if the data block is highly necessary,
There is a possibility that the data will be replaced without being taken into consideration and be expelled to the main memory.

Even if the LRU method is used, since the operation of frequently rewriting data at the same address is rare in the input / output cache, a difference in the frequency of use between blocks is hard to be obtained. There was a problem that improvement could not be expected so much.

That is, in data transfer of an input / output device, a large amount of data is often accessed by a continuous address. Therefore, rather than accessing the data once accessed again immediately, the data is transferred from the beginning to the end of the block once. Once accessed, the block is often unnecessary. Also, among input / output devices, there are relatively high-speed devices such as disk devices, and low-speed devices such as line systems. Therefore, when deciding the replacement target block in the input / output cache, it is necessary to consider the circumstances specific to these input / output devices.

An object of the present invention is to solve the above-mentioned problem and to provide an input / output cache having a block replacement algorithm suitable for the input / output cache.

Another object of the present invention is to determine a block that has accessed up to the last byte in a block or a block having data from a device other than a disk device,
An object of the present invention is to determine a replacement target block utilizing a characteristic of an input / output device at the time of a cache miss.

Another object of the present invention is to improve the data transfer performance between a main storage device and an input / output device.

[0010]

In order to solve the above problems, an input / output cache according to the present invention is an input / output cache managed for each block and accessed by an input / output device. If the input / output device is an input / output device other than a disk device, a first access flag holding means for holding a first access flag to be set for each block, and a new block is secured in the input / output cache. In this case, a replacement target block determination unit that determines which block from the blocks of the input / output cache should be a replacement target block in accordance with the contents of the first access flag holding unit.

Further, another input / output cache according to the present invention includes:
An input / output cache managed for each block and accessed by an input / output device, wherein a first access flag which is set if a line-based access is made from the input / output device is set for each block. First to hold
Access flag holding means, and when a new block is reserved in the input / output cache, which block is replaced with any of the blocks of the input / output cache according to the contents of the first access flag holding means. Replacement target block determination means for determining whether or not the replacement should be performed.

Further, another input / output cache according to the present invention includes:
A first access flag that is set for an I / O cache that is managed for each block and that is accessed by the I / O device if the I / O device accesses the I / O device other than the disk device. First access flag holding means for holding each block, and second access flag indicating that the last byte in the block has been accessed.
Second access flag holding means for holding the access flag for each block, and when securing a new block in the input / output cache, the first access flag holding means and the second access flag holding means And a replacement target block determining means for determining which block among the blocks of the input / output cache is to be replaced.

Another input / output cache according to the present invention includes:
An input / output cache managed for each block and accessed by an input / output device, wherein a first access flag which is set if a line-based access is made from the input / output device is set for each block. First to hold
Access flag holding means, a second access flag holding means for holding, for each block, a second access flag indicating that the byte at the last position in the block has been accessed, and a new access flag holding means in the I / O cache. When allocating a block, it is determined which of the blocks of the input / output cache should be a replacement target block according to the contents of the first access flag holding means and the second access flag holding means. And a replacement target block determining unit.

Further, another input / output cache according to the present invention includes:
In the I / O cache managed for each block and accessed by the I / O device, the replacement target block determination unit includes an unused block presence / absence determination unit that determines whether there is a free block in the I / O cache, A first access block presence / absence determining unit for determining whether or not there is a block in which the first access flag is set according to the contents of the first access flag holding unit; A block status determination unit that determines the status, and a search position holding unit that holds a block search start position when determining a replacement block, from the position held by the search position storage unit by the unused block presence / absence determination unit Each block is searched, and if there is an unused block, the block is set as a replacement target block. Is determined, the first access block presence / absence determining unit searches each block from the position held by the search position holding unit, and if there is a block in which the first access flag is set, the block is replaced with a target block. To be determined.

Further, another input / output cache according to the present invention includes:
In the I / O cache managed for each block and accessed by the I / O device, the replacement target block determination unit includes an unused block presence / absence determination unit that determines whether there is a free block in the I / O cache, A first access block presence / absence determining unit that determines whether or not there is a block in which the first access flag is set in the input / output cache in accordance with the contents of a first access flag holding unit; In the input / output cache according to the contents of the access flag holding means.
A second access block presence / absence determination unit that determines whether there is a block for which the access flag is set,
A block status determination unit that determines a status of each block of the input / output cache; and a search position holding unit that holds a block search start position when determining a replacement block, wherein the search is performed by the unused block presence / absence determination unit. Each block is searched from the position held by the position holding unit, and if there is an unused block, the block is determined as a replacement target block, and the second access block presence / absence determining unit determines from the position held by the search position holding unit. Each block is searched, and if there is a block in which the second access flag is set, the block is determined as a replacement target block, and the position held in the search position holding unit by the first access block presence / absence determining unit is determined. , And the second access flag is set. The lock is determined as the target block replaces the block, if any.

Further, another input / output cache according to the present invention includes:
A data array for storing data; and a tag array for storing address and control information corresponding to the data array, wherein the control information is stored in the first access flag holding unit and the second access flag holding unit. including.

Further, another input / output cache according to the present invention includes:
When the cache block is accessed with a certain number of bytes or more, the first access flag corresponding to the accessed block is set.

Further, another input / output cache according to the present invention includes:
When a cache access is not accompanied by a disk device identification signal, the first access flag corresponding to the accessed block is set.

[0019]

Next, an embodiment of the input / output cache according to the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, an input / output cache 100 according to an embodiment of the present invention includes a system bus 103 to which a central processing unit 101 and a main storage device 102 are connected, and input / output device groups 106-1 to 106-n. In the input / output processing unit 104 located between the input / output bus 105 and the input / output bus 105.

When the CPU 101 issues a transfer command from the main storage device 102 to the I / O device 106, the I / O device 106
11 and the input / output cache 1 via the selector 112
Access 00. If the desired data exists in the input / output cache 100, the data is transferred to the destination input / output device 106 via the selector 114 and the input / output bus output buffer 110. If the desired data does not exist in the input / output cache 100, a request is notified to the main storage device 102 via the selector 113 and the system bus output buffer 108. After the block containing the requested data is read from the main storage device 102, it is stored in the input / output cache 100 via the system bus input buffer 107 and the selector 112. The requested data is sent to the destination input / output device 106 via the selector 114 and the input / output bus output buffer 110.
Will also be forwarded. By storing the block in the input / output cache, subsequent access to the main storage device 102 for data in the block becomes unnecessary.

FIG. 1 shows only a part of the input / output processing device 104 related to the input / output cache.

Referring to FIG. 2, an input / output cache 100 according to an embodiment of the present invention includes a data array 208 for storing data and a tag array 207 for storing addresses and control information corresponding to the data array 208. Contains. The input / output cache 100 is provided with a data buffer 2 for holding commands, addresses and data.
01, an unused block presence / absence determination circuit 202 for determining the presence / absence of an unused block, an LBU block presence / absence determination circuit 203 for determining the presence / absence of an LBU (Last Byte Used) block, and a block for determining the status of each block A status determination circuit 204 and an NDA block presence / absence determination circuit 20 for determining the presence / absence of an NDA (access by a device other than a disk, abbreviation for Non Disk Access)
5, a replacement block determination circuit 206 that determines a block to be replaced and issues an instruction to that effect, and a replacement pointer 209 that indicates a starting point for searching for a replacement target.
And a comparator 210 for detecting whether the block to be replaced matches the block indicated by the replacement pointer 209, and a cache control circuit 211 for controlling the cache tag array 207 and the cache data array 208. I have.

An input / output cache according to an embodiment of the present invention includes:
In the cache tag array 207, "invalid (hereinafter referred to as I)", "shared (hereinafter referred to as S)", "match /
It is assumed that the status has one of the statuses “exclusive (hereinafter, referred to as CE)” and “mismatch / exclusive (hereinafter, referred to as DE)”. If the status is "I", it indicates that no valid data is stored in that block. If "S", the block is the central processing unit 101
And the I / O cache 100. If "CE", it indicates that the block is occupied by the I / O cache 100 and its contents match those of the storage device. In addition, if it is “DE”, it indicates that the block is exclusively used by the input / output cache 100 and that its contents do not match those of the storage device. These statuses are due to existing technology, for example:
"Amano et al .: Parallel processing mechanism, Maruzen, pp.186-190 (198
Aug. '09) ".

An input / output cache according to an embodiment of the present invention includes:
The cache tag array 207 further holds an LBU flag and an NDA flag for each block.

The LBU flag indicates that a read or write access has been made to the last byte in the block. I / O device data transfer
Often, a large amount of data is accessed at a continuous address, and rather than accessing the data once accessed again, once the block is accessed from the beginning to the end, the block may become unnecessary. Many. Therefore, this LBU flag is provided, and the block accessing the last byte is to be replaced.

The NDA flag indicates that the block is used by a device other than the disk device. 16-byte transfer is the mainstream for high-speed transfer disk-based access, and low-speed transfer access for line-based systems is mainly 2 bytes. I / O cache can be used more efficiently if data from a device is removed. In order to set the NDA flag, for example, when the input / output cache is accessed by transfer of less than 16 bytes, a method of setting the NDA flag of the block to be accessed may be considered. When the disk device is accessed, an identification signal is sent to the input / output processing device 104. In the absence of the signal, the block is regarded as being accessed by a device other than the disk device, and May be set.

The cache control circuit 211 changes the status of the cache tag corresponding to each block according to the command and address held in the data buffer 201 and the contents of the cache tag array 207, and also changes the LBU flag and the NDA flag. Is set. Further, the cache control circuit 211 performs a process of replacing the cache tag array 207 and the cache data array 208 at the time of a cache miss in accordance with the replacement block and the replacement instruction from the replacement block determination circuit 206.

The block status determination circuit 204 refers to the data of the cache tag array 207 and determines whether the status of each block is "S" or "CE".
It is determined whether it is “DE” and the result is determined by the LBU block presence / absence determination circuit 203 and the NDA block presence / absence determination circuit 2
Send to 05.

The unused block presence / absence determination circuit 202 refers to the content corresponding to each block of the cache tag array 207 and the replacement pointer 209, and if there is a block whose status is "I", that fact and the number of the block To the replacement block determination circuit 206.

The LBU block presence / absence determination circuit 203 determines whether the LBU corresponding to each block of the cache tag
By referring to the U flag, the value of the replacement pointer 209, and the status information of each block from the block status determination circuit 204, if there is a block in which the LBU flag is set, that fact is replaced by the block number and status. This is sent to the block determination circuit 206.

The NDA block presence / absence determination circuit 205 determines the ND corresponding to each block of the cache tag array 207.
By referring to the A flag, the value of the replacement pointer 209, and the status information of each block from the block status determination circuit 204, if there is a block in which the NDA flag is set, the fact and the number and status of the block are replaced. This is sent to the block determination circuit 206. If there is no block in which the NDA flag is set, the fact, the number and status of the block are set as follows.
This is sent to the replacement block determination circuit 206.

The replacement block determination circuit 206 performs replacement based on the replacement pointer 209 and each determination result of the cache block by the unused block presence determination circuit 202, the LBU block presence determination circuit 203, and the NDA block presence determination circuit 205. Determine the block,
The block number and the replacement instruction are output.

When the replacement instruction is output from the replacement block determination circuit 206, the comparator 210 compares the number of the replacement block output from the replacement block determination circuit 206 with the value of the replacement pointer, and the two values match. In this case, the value of the replacement pointer 209 is increased by one.

Next, the operation of one embodiment of the input / output cache of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 3 and FIG. 2, the initial state of the replacement pointer 209 is 0, indicating the head block of the cache (S301). When a cache block needs to be replaced due to a cache miss (S302), first, the replacement pointer 209 is replaced.
It is checked whether the status of the block indicated by “I” is “I” (S
303), if "I", the current replacement pointer 2
09 is determined as a replacement target (S
304).

If the status of the block indicated by the current replacement pointer 209 is not "I", the other blocks are searched for "I" in order from the block closest to the replacement pointer (S305). If there is a block "", the block is set as a replacement target (S306).

If there is no block of "I" in the above processing, there is no empty block in the cache, and the replacement target is searched for from the used blocks. Therefore, it is determined whether there is a block that has been used up to the last byte.

The LBU flag is set, and the block whose status is "S" or "CE" is searched in order from the block closest to the replacement pointer (S30).
7) If present, the block is replaced (S3)
08). If there is no corresponding block, the status is "D
In the block of “E”, the LBU flag is set, and the block closest to the replacement pointer is searched in order (S309). If there is a block, the block is set as a replacement target (S310). Where "S" and "CE"
The block was replaced first because, in these statuses, the same data exists in main memory,
At the time of replacement, there is no need to write back the data of the block to the main memory, so the replacement process can be performed immediately.
In the case of the block "E", the data does not match the data in the main memory. Therefore, it is necessary to write the data of the block back to the main memory at the time of replacement. This is because the data cannot be replaced with the block.

In the above process, if there is no block using the last byte, it is determined whether or not the NDA flag is set.

If the NDA flag is set, and
A search is made for a block whose status is "S" or "CE" in the order of proximity to the replacement pointer 209 (S31).
1) If present, the block is set as a replacement target (S3
12). If there is no corresponding block, the status is "D
In the block of "E", the block in which the NDA flag is set is searched in order from the block closest to the replacement pointer (S313), and if there is, the block is set as a replacement target (S314). Here, the status is "DE"
Is replaced, the data of the block is written to the main memory and the replacement process is performed in the same manner as the process when the LBU flag is set (S310).

In the above processing, when there is no block in which the NDA flag is set, it is known that all the blocks in the cache are related to the disk, so that the block whose status is "S" or "CE" first. Are searched in order from the block closest to the replacement pointer 209 (S315), and if there is, the block is determined as a replacement target (S316). If there is no corresponding block, only the block whose status is "DE" is set, and at that time, the block indicated by the replacement pointer 209 is set as a replacement target (S317).

With the above processing, the block to be replaced is determined, and the status of the block is set to "S".
Or, if "CE", the replacement process is executed without writing back the data held in the block to the main memory, and if the status is "DE", first, the data held in the block is written to the main memory. Then, the replacement process is executed (S318). Then, the number of the replaced block is compared with the value of the replacement pointer (S
319) If different, the value of the replacement pointer 109 is the same value. If they match, the value of the replacement pointer 209 is incremented by one (S320) to prepare for the next cache access (S302).

As described above, according to the input / output cache according to one embodiment of the present invention, the last byte in the block is accessed by providing the LBU flag and the NDA flag in each block of the cache tag array 207. A block having data by a device other than the block and the disk device is transferred to the LBU block presence / absence determination circuit 203 or ND.
It can be easily determined by the A block presence / absence determination circuit 205,
Blocks to be replaced can be determined from the viewpoint of performance emphasis.

[0045]

As is apparent from the above description, according to the present invention, the provision of the LBU flag and the NDA flag as the state of the cache memory allows the block other than the block or disk device which has accessed the last byte in the block. Blocks having data by the device can be easily identified,
Since the block to be replaced can be determined by utilizing the characteristics of the input / output device at the time of a cache miss, the data transfer performance between the main storage device and the input / output device can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a connection between an input / output cache and the outside according to the present invention.

FIG. 2 is a diagram illustrating a configuration of an embodiment of an input / output cache according to the present invention.

FIG. 3 is a diagram illustrating an operation of an input / output cache according to an embodiment of the present invention.

DESCRIPTION OF SYMBOLS 100 input / output cache 101 central processing unit 102 main storage device 103 system bus 104 input / output processing device 105 input / output bus 106 input / output device 107 system bus input buffer 108 system bus output buffer 110 input / output bus output buffer 111 Input / output bus input buffers 112 to 114 Selector 201 Data buffer 202 Unused block presence / absence determination circuit 203 LBU block presence / absence determination circuit 204 Block status determination circuit 205 NDA block presence / absence determination circuit 206 Replacement block determination circuit 207 Cache tag array 208 Cache data array 209 Replace pointer 210 Comparator 211 Cache control circuit

Claims (6)

(57) [Claims] 1. An input / output device that is managed for each block
In accessed Ru O cache, disk instrumentation when an access from said input device
If the input / output device is a device other than the
A first access flag holding unit for holding a block flag for each block ; and when securing a new block in the I / O cache, a block of the I / O cache according to the contents of the first access flag holding unit. An input / output cache, comprising: a replacement target block determination unit that determines which block is to be replaced. 2. It is managed for each block and is controlled by an input / output device.
In accessed Ru O cache, A than a predetermined speed from the low-speed input-output processor
The first access flag set when there is access
A first access flag holding unit for holding a block for each block; and, when a new block is secured in the input / output cache, a block of the input / output cache according to the contents of the first access flag holding unit. An input / output cache, comprising: a replacement target block determination unit that determines which block is to be replaced. 3. An input / output device which is managed for each block
In accessed Ru O cache, disk instrumentation when an access from said input device
If the input / output device is a device other than the
A first access flag holding unit for holding a block flag for each block , and a second access flag for each block indicating that a byte at the last position in the block has been accessed.
A second access flag holding unit, and when securing a new block in the input / output cache, the first access flag holding unit and the second access flag holding unit .
And a replacement target block determining means for determining which block from among the blocks of the input / output cache is to be replaced according to the contents of the access flag holding means. 4. It is managed for each block and is controlled by an input / output device.
In accessed Ru O cache, A than a predetermined speed from the low-speed input-output processor
The first access flag set when there is access
A first access flag holding means for holding a block for each block , and a second access flag for each block indicating that a byte at the last position in the block has been accessed.
A second access flag holding unit, and when securing a new block in the input / output cache, the first access flag holding unit and the second access flag holding unit .
And a replacement target block determining means for determining which block from among the blocks of the input / output cache is to be replaced according to the contents of the access flag holding means. 5. An unused block presence / absence determining unit for determining whether or not there is a free block in the input / output cache, and a content of the first access flag holding unit. Said
A first access block determining unit determines whether the first access flag is block being set, and determines the block status determination unit the status of each block of the input cache, the replacement block A search position holding unit for holding a block search start position at the time of determination, wherein the unused block presence / absence determination unit searches for each block from the position held by the search position holding unit, and if there is an unused block, A block in which the first access flag is set is determined by determining the block as a replacement target block and searching for each block from the position held by the search position holding unit by the first access block presence / absence determining unit. > claim 1, wherein the determining the target block replaces the block if there is locked Input and output cache. 6. An unused block presence / absence determining unit for determining whether or not there is a free block in the input / output cache, and a content of the first access flag holding unit. The first access flag is set in the I / O cache
A first accession <br/> Seth block determining unit determines whether the block is being, the second access to the output cache in accordance with the content of the second access flag holding means A second action for determining whether or not there is a block with the flag set.
Access block presence / absence determination unit, a block status determination unit for determining the status of each block in the input / output cache, and a search position holding unit for holding a block search start position when determining a replacement block, Each block is searched from the position held by the search position holding unit by the block presence / absence determination unit, and if there is an unused block, the block is determined as a replacement target block, and the second access block presence / absence determination unit determines the search position. if the searches the blocks from the position held by the holding portion second access flag blanking <br/> lock has been set is determined as the object block replaces the block, the first access block whether the determination unit the search position holder position from the second to search each block to hold the O cache of claim 3 Kusesufuragu is characterized by determining a target block replaces the block if there is <br/> block being set.