JP2634896B2 - Debug device memory circuit - Google Patents

Description

The present invention relates to a memory circuit of a debugging device.

(Prior Art) A debugging device for a microcomputer or the like is a device for evaluating a program of the microcomputer or the like and an evaluation of a peripheral circuit, and must perform the same operation as the microcomputer or the like.

However, in order to display or change the contents of an internal register, a data memory, a program memory, and the like of the microcomputer, a memory circuit provided in the debugging device is preferably one in which data can be easily rewritten.

Therefore, the typical microcomputer data memory and a program memory such as a mask ROM, EPROM, or E ² is a memory device such as a PROM is used, the memory circuit in the debugging apparatus, the rewriting of data For ease of use, RAM has been used instead of each of the aforementioned memories.

(Problems to be Solved by the Invention) By the way, more strictly, it is desired that the memory device in the debugging device has all of the following three requirements.

(1) Data rewriting is easy as a function of the debugging device. (2) The written content is retained even when the power is turned off. (3) The debugging device is similar to the microcomputer or the like. Since the operation is performed, it is possible to prevent the inconvenience of writing the data “1” once where the data “0” has been written once.

However, in a conventional memory circuit using a RAM simply as a memory element, the requirement (1) can be satisfied, but the requirements (2) and (3) cannot be satisfied.

Therefore, instead of the RAM, it is conceivable to use an E ² PROM or an EPROM.
All of the requirements (1) to (3) cannot be satisfied.

For example, when the E ² PROM is used, the requirements (1) and (2) can be satisfied, but the requirement (3) cannot be satisfied.

When an EPROM is used instead of the RAM, the requirements (2) and (3) can be satisfied, but the requirement (1) is not sufficient.

The present invention has been made in view of the above circumstances, and provides a memory circuit of a debug device that satisfies all of the above three requirements. (2) The written contents are retained even after the power is turned off. (3) Since the debugging device operates in the same manner as the microcomputer, the EPRO
When M is used, provide a memory circuit of a debugging device that satisfies all of the requirements of once writing data "0" and preventing the inconvenience of writing data "1". The purpose is to do.

Memory circuit debugging device according to (SUMMARY for a) the present invention includes a E ² PROM is a memory device, interposed between the data input-output bus and the E ² PROM to the E ² PROM And a data control circuit for controlling the input data.

The data control circuit includes an OR circuit and an AND circuit.

Then, the OR circuit is "L" of the selection signal input to one input terminal, the data or hexa code held in the E ² PROM by "H" switching FFH (i.e., "1111111
1)) is output alternatively.

The AND circuit is configured to logically AND the input / output data on the data input / output bus and the output data of the OR gate and output the result to the E ² PROM.

(Operation) In the memory circuit of the debugging device according to the present invention, the data written to the E ² PROM as a memory element is obtained by logically connecting the data on the data input / output bus and the output data of the OR circuit by the AND circuit in the control circuit. It is the product.

Here, the output data from the OR circuit is data held in the E ² PROM when the selection signal input to the OR circuit is “L”, and when the selection signal is “H”. Is FFH data.

Therefore, for example, if the data already held in the E ² PROM is “01010101” and the data input from the data input / output bus is “10011001”, if the selection signal is “L”, the OR The output data from the circuit is the data “01010101” held in the E ² PROM,
010101 ”is the data“ 10011001 ”on the data input / output bus
As a result, the data written to the E ² PROM becomes “00010001”, and as a result, the EP where data “1” cannot be written where data “0” has already been written
Functions as ROM.

On the other hand, when the selection signal is “H”, the output data of the circuit is FF regardless of the data held in the E ² PROM.
H (that is, “11111111”), and the data “1111111”
Results 1 "is the logical product between the data" 10011001 "on the data input bus, the data to be written to the E ² PROM is" 100110
01 ", and consequently, already it will function as E ² PROM capable of writing the data inputted to the data input-output bus regardless of the data written in the E ² PROM.

That is, in the memory circuit of the debugging device according to the present invention,
Although an E ² PROM is used as the memory element, switching of the selection signal input to the OR gate in the control circuit causes
It can function as both an E ² PROM and an EPROM.

Therefore, in the memory circuit of the debugging device of the present invention, E ²
Since the data is held by using a PROM, and it is made to function as an E ² PROM by switching the selection signal,
Data can be easily rewritten, and by functioning as an EPROM, it becomes possible to perform the same operation as a microcomputer or the like in which an EPROM is built. (2) Even if the power is turned off,
(3) Since the debug device operates in the same manner as the microcomputer or the like, if the EPROM is used in the microcomputer or the like, data "0" is once written. Where you wrote
Further, the inconvenience of writing the data “1” can be prevented, and so on.

(Embodiment) FIG. 1 is a circuit diagram showing a configuration of a main part of an embodiment of the present invention.

This embodiment is, for example, a memory circuit in a debug device such as an emulator, and a memory element E ²
Data control circuit 3 between PROM 1 and data input / output bus 2
The E ² PROM is also made to function also as an EPROM by interposing a.

Note that reference numeral 4 in the figure denotes an address bus connected to the E ² PROM.

The data control circuit 3 controls the flow of data between the E ² PROM 1 and the data input / output bus 2 and has a first
It comprises an IC 6, a second IC 7, a third IC 8, an OR circuit 9, an AND circuit 10, and the like.

In the case of this embodiment, the E ² PROM 1 has eight data input / output terminals. These data input / output terminals are connected to the output terminal of the IC 6, the input terminal of the IC 7, and the IC 8 via the data bus 12. Are connected to each of the input terminals.

Each of the above-mentioned ICs 6 and 7 stores and holds data input at a certain time as it is, and outputs the stored and stored data under certain conditions.
8 has an output terminal connected to the data bus 2;
The data on the data bus 12 is output to the data input / output bus 2 via the D signal line 20.

The OR circuit 9 has an OR gate 9a corresponding to the number of input / output terminals of the E ² PROM1.
It consists ～9H, whereas, the AND circuit 10 is composed of AND gates 10a~10h the number of input and output terminals of the E ² PROM1.

Each of the OR gates 9a to 9h constituting the OR circuit 9 has one input terminal connected to the output terminal of the IC 7,
The other input terminal is connected to the E ² PROM / EPROM selection signal line 14.

Here, the selection signal line 14 is intended to flow a selection signal for determining whether to function the E ² PROM1 as E ² PROM, or to function as EPROM, selection signals in this case, "L" or "H".

Further, the output terminals of these OR gates 9a to 9h
The D circuit 10 is connected to one input terminal of the AND gates 10a to 10h.

That is, the above-mentioned OR gates 9a to 9h OR the selection signal input from the selection signal line 14 with the data held in the second IC 7 and output the OR to the corresponding AND gates 10a to 10h. I do.

As a result, when the selection signal is “L”, the signal output from the OR circuit 9 to the AND circuit 10 is the signal held in the IC 7, that is, the data already written in the E ² PROM 1. , When the selection signal is “H”, it becomes FFH.

The AND gates 10a to 10h constituting the AND circuit 10 include:
The output terminals of the OR gates 9a to 9h are connected to one input terminal, respectively, while the data input / output bus 2 is connected to the other input terminals. And each AND gate 1
Output terminals 0a to 10h are connected to input terminals of IC6.

The signal line 16 for sending a write command is
It is connected to the ▲ ▼ terminal 1x of the E ² PROM1 and the ▲ ▼ terminal (output enable terminal) 6x of the IC 6, and also connected to the ▲ ▼ terminal 1y of the E ² PROM1 via the inverter 17.

The data latch signal line 18 is connected to the CK terminal (clock terminal) 6y of the IC 6, the mask data latch signal line 19 is connected to the CK terminal 7x of the IC 7, and the RD signal line 20 for sending a read command is connected to the It is connected to the G terminal (gate terminal) 8x, 8y of IC8.

The ▲ ▼ data latch signal line 18 supplies a pulse signal for determining the data input / output timing in the IC 6.
It is for sending to IC6.

The mask data / latch signal line 19 is for sending a pulse signal for determining the timing of data input / output in the IC 7.

The ▲ ▼ terminal 7y of the IC 7 is grounded.

The operation of the memory circuit of the debugging device having the above configuration will be described with reference to FIGS. 2 (A) to 2 (H) and FIG.

As shown in FIG. 2 (A), the signal (▲ ▼ signal) from the ▲ ▼ signal line 16 is normally “H”.

When the ▲ ▼ signal is “H”, the E ² PROM1 ▲ ▼
Since the signal input to the terminal 1x becomes “L”, the E ² PROM1
, The data written to the address specified by the address 4 is always output (see FIG. 2B).

The data output from the E ² PROM 1 to the data bus 12 is
5H, and the content is “01010101”.

The data 55H output to the data bus 12 is captured and held in the IC 7 by a pulse signal (see FIG. 2C) from the mask data latch signal line 19.

The data 55H held in the IC 7 is output to the OR gates 9a to 9h at the rise of the pulse signal from the signal line 19 (second
(See FIGS. (C) and (D).) The selection signal from the selection signal line 14 is ORed.

At this time, the data output from the OR circuit 9 (see FIG. 2 (E)) is such that the selection signal is “H” (that is, “11”).
If the selection signal is "L" (i.e., "00000000"), it becomes FFH (i.e., "11111111").

The write data (see FIG. 2 (F)) sent to the data input / output bus 2 is set to 99H, and the content is set to “10011”.
001 ".

The data output from the OR circuit 9 is input to the AND circuit 10 and is ANDed with the data 99H of the data input / output bus 2.

As a result, when the selection signal is "L", the data output from the AND circuit 10 is 11H (by ANDing the data 55H from the OR circuit 9 and the data 99H from the data input / output bus 2). That is, “00010001”).

When the selection signal is “H”, the data output from the AND circuit 10 is 99H by ANDing the data FFH from the OR circuit 9 and the data 99H from the data input / output bus 2. Become.

The output data (see FIG. 2 (G)) from the AND circuit 10 is taken into the IC 6 by a pulse signal (see FIG. 2 (H)) from the WR data latch signal line 18, and
Will be retained.

When the signal from the signal line 16 becomes "L", the data held in the IC 6 is output to the E ² PROM 1 and written.

That is, as shown by reference numeral 101 to 107 in FIG. 3, E ² PROM / E
When the selection signal from the PROM selection signal line 14 is "L",
Data 55H “01010101” output from E ² PROM1
1) passes through the second IC 7 (reference numerals 102 and 103) and becomes an input (reference numeral 104) of the OR circuit 9 and the selection signal “00000” of the selection signal line 14
000 ”and the data 55H“ 01010101 ”(code 10
5) becomes the output data of the OR circuit 9.

This data is the data 99H "10011001" of the data input / output bus 2 which is the data to be written by the AND circuit 10.
(Code 200) and data 11H "00010001"
(Reference numeral 106) is created.

Since the data 11H “00010001” (reference numeral 107) is written to the E ² PROM 1 via the IC 6, as a result, the data already written (data 55H “01010101” (reference numeral 101))
(Where "0" is written), "0" is written even if the data to be written is "1", and the original data remains substantially, and new data "1" is written. It functions as an EPROM that cannot do it.

On the other hand, as shown by reference numerals 301 to 307 in FIG. 3, when the selection signal is “H”, the data 55H output from the E ² PROM 1
"01010101" (reference numeral 301) passes through the second IC7 (reference numeral 302,
303), which becomes an input (reference numeral 304) of the OR circuit 9 and is ORed with the selection signal “11111111” to obtain the data FFH “11111111”
(Reference numeral 305) is output data of the OR circuit 9.

This data is the data 99H "10011001" of the data input / output bus 2 which is the data to be written by the AND circuit 10.
(Code 200) and data 99H "10011001"
(Reference numeral 306) is created.

Since this data 99H “10011001” (symbol 307) is written to the E ² PROM 1 via the IC6, the data on the data bus 2 is consequently irrespective of the already written data “01010101” (symbol 301). Can be written
This means that it functions as an E ² PROM.

That is, in the memory circuit of this embodiment, an E ² PROM is used as a memory element. However, by switching a selection signal input to the OR circuit 9 in the control circuit, the E ² PROM is also used.
It can also function as an EPROM.

Therefore, in the memory circuit of the debugging device of the present invention, E ²
Since the data is held by using a PROM, and it is made to function as an E ² PROM by switching the selection signal,
Data can be easily rewritten, and by functioning as an EPROM, it becomes possible to perform the same operation as a microcomputer or the like in which an EPROM is built. (2) Even if the power is turned off,
(3) Since the debug device operates in the same manner as the microcomputer or the like, if the EPROM is used in the microcomputer or the like, data "0" is once written. Where you wrote
Further, the inconvenience of writing the data “1” can be prevented, and so on.

In the above it has been described the flow of data when data is written to the E ² PROM1 detail, E ² PROM1
In the case where the data written in is read out via the data input / output bus 2, the operation is as follows.

First, by referring to the address to be read specified by the address, the data corresponding to the address written in the E ² PROM 1 is output to the data bus 12, and via the IC 8 according to the signal obtained through the RD signal line 20. Output on the data input / output bus 2.

(Effects of the Invention) As is apparent from the above description, in the memory circuit of the debugging device according to the present invention, E ² PR
The data written to the OM is obtained by ANDing the data on the data input / output bus and the output data of the OR circuit by the AND circuit in the control circuit.

Here, the output data from the OR circuit is data held in the E ² PROM when the selection signal is “L” input to the OR circuit, and when the selection signal is “H”. Is FFH data.

Therefore, for example, the data already held in the E ² PROM is “01010101” and the data on the data input / output bus is “1001
If the selection signal is “L”, the output data from the OR circuit is “01010101”, and the data “01010101” is ANDed with “10011001” as a result,
The data written to the E ² PROM is “00010001”, and as a result, it functions as an EPROM in which data cannot be written where data has already been written.

On the other hand, when the selection signal is “H”, the output data FFH from the OR circuit (that is, “11111111”) results in the logical product of “11111111” and “10011001”,
E ² data written to the PROM "10011001", and consequently, E ² PR, which can already written to by which data written the data on the data input and output on the bus regardless
It will function as OM.

That is, in the memory circuit of the debugging device according to the present invention,
Although an E ² PROM is used as the memory element, switching of the selection signal input to the OR gate in the control circuit causes
It can function as both an E ² PROM and an EPROM.

Therefore, in the memory circuit of the debugging device of the present invention, E ²
By using a PROM to hold data and switching the selection signal to function as an E ² PROM, data can be easily rewritten.
By making it function as M, it becomes possible to perform the same operation as a microcomputer or the like having a built-in EPROM. Therefore, (1) data rewriting is easy as a function of a debugging device, and (2) (3) Since the debug device operates in the same manner as the microcomputer or the like even if the EPROM is used, if the EPROM is used in the microcomputer or the like, the data is once stored. It is possible to satisfy all the requirements, such as preventing the inconvenience of writing data "1" where "0" is written.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a time chart at the time of a write operation in one embodiment, and FIG. 3 is an explanatory diagram of data written to an E ² PROM in one embodiment. 1 ...... E ² PROM, 2 ...... data output bus, 3 ...... data control circuit, 6, 7, 8 ...... IC, 9 ...... OR circuit, 10 ...... the AND circuit, 14 ...... selection signal lines, 16 …… ▲ ▼ Signal line.

Claims (1)

(57) [Claims] An E ² PROM as a memory element, and a data control circuit interposed between a data input / output bus and the E ² PROM to control input data to the E ² PROM. A memory circuit of a debugging device, wherein the data control circuit selects data held in the E ² PROM or FFH data by switching “L” or “H” of a selection signal input to one input terminal. A debugging circuit characterized by comprising: an OR circuit that outputs a logical output; and an AND circuit that logically ANDs input data on a data input / output bus and output data of the OR gate and outputs the logical product to the E ² PROM. Memory circuit.