JP2634340B2 - Control circuit - Google Patents

Control circuit

Info

Publication number
JP2634340B2
JP2634340B2 JP3269992A JP26999291A JP2634340B2 JP 2634340 B2 JP2634340 B2 JP 2634340B2 JP 3269992 A JP3269992 A JP 3269992A JP 26999291 A JP26999291 A JP 26999291A JP 2634340 B2 JP2634340 B2 JP 2634340B2
Authority
JP
Japan
Prior art keywords
transmission
reception
phase
switching
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3269992A
Other languages
Japanese (ja)
Other versions
JPH0583156A (en
Inventor
全広 寺澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3269992A priority Critical patent/JP2634340B2/en
Publication of JPH0583156A publication Critical patent/JPH0583156A/en
Application granted granted Critical
Publication of JP2634340B2 publication Critical patent/JP2634340B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Transceivers (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は制御回路に関し、特に
レーダ装置等に利用されるフェーズドアレイアンテナ用
送受信モジュールに組み込まれる制御回路に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit, and more particularly to a control circuit incorporated in a transmission / reception module for a phased array antenna used in a radar device or the like.

【0002】[0002]

【従来の技術】図3(a) は送信時に、例えば2種の送信
位相を設定する機能を有した従来の制御回路の構成を示
す図であり、図において、1は制御回路全体を示し、2
は受信位相メモリ、3aは第1送信位相メモリ、3bは
第2送信位相メモリである。4は送受信モジュールの外
部から制御装置へ伝送される送信位相切換基準信号であ
り、6はこの基準信号4をもとにして第1送信位相メモ
リ3aと第2送信位相メモリ3bとの送信位相データを
切り換えて設定する送信位相設定回路、11は送受信モ
ジュールの外部から制御回路へ伝送される送信/受信切
換基準信号、7は送信/受信切換基準信号11をもとに
して送信位相と受信位相とを切り換えて設定する送信受
信位相設定回路、8は上記送信受信位相設定回路7の出
力である送信受信位相設定信号で、この信号は後段の図
示しない送受信モジュール内の移相器へ伝送される。9
は上記送信/受信切換基準信号11をもとにして、送受
信モジュール内の各種RFデバイスの動作の制御(ON
/OFFまたはスイッチの切換)を行い、送信,受信の
切り換えを行うための駆動信号10を発生させる送信受
信切り換え回路である。
2. Description of the Related Art FIG. 3 (a) is a diagram showing a configuration of a conventional control circuit having a function of setting, for example, two kinds of transmission phases at the time of transmission. 2
Denotes a reception phase memory, 3a denotes a first transmission phase memory, and 3b denotes a second transmission phase memory. Reference numeral 4 denotes a transmission phase switching reference signal transmitted from the outside of the transmission / reception module to the control device. Reference numeral 6 denotes transmission phase data of the first transmission phase memory 3a and the second transmission phase memory 3b based on the reference signal 4. , A transmission / reception switching reference signal transmitted from the outside of the transmission / reception module to the control circuit, and a transmission / reception phase reference signal based on the transmission / reception switching reference signal. Is a transmission / reception phase setting circuit which is an output of the transmission / reception phase setting circuit 7 and is transmitted to a phase shifter in a transmission / reception module (not shown) at a subsequent stage. 9
Controls the operation (ON) of various RF devices in the transmission / reception module based on the transmission / reception switching reference signal 11
/ OFF or switching of a switch) to generate a drive signal 10 for switching between transmission and reception.

【0003】図3(b) は送信位相切換基準信号4と送信
受信切換基準信号11と送信受信位相設定信号8のタイ
ミングチャートの一例である。
FIG. 3B is an example of a timing chart of the transmission phase switching reference signal 4, the transmission / reception switching reference signal 11, and the transmission / reception phase setting signal 8.

【0004】次に動作について説明する。送信/受信切
換基準信号11をもとにして、送信受信切り換え回路9
では送信期間に送信系のRFデバイスをONし、受信系
のRFデバイスをOFFし、スイッチ等を送信側に切り
換える等の駆動信号10を発生して、送受信モジュール
を送信状態とする。一方、受信期間では、送信系RFデ
バイスをOFFし、受信系RFデバイスをONし、スイ
ッチ等を受信側に切り換え、送受信モジュールを受信状
態とする。
Next, the operation will be described. Transmission / reception switching circuit 9 based on transmission / reception switching reference signal 11
Then, during the transmission period, the RF signal of the transmission system is turned on, the RF device of the reception system is turned off, and a drive signal 10 for switching a switch or the like to the transmission side is generated, and the transmission / reception module is set to the transmission state. On the other hand, in the reception period, the transmission system RF device is turned off, the reception system RF device is turned on, a switch or the like is switched to the reception side, and the transmission / reception module is set in the reception state.

【0005】さらに、送信受信位相切換回路7では送信
受信切換基準信号11をもとにして、受信期間では受信
位相メモリ2から読み出した受信位相設定値を後段の図
示しない送受信モジュール内の移相器へ送り出し、送信
期間には送信位相設定回路6から送られてくる送信位相
を図示しない後段の移相器へ送り出す。この時、送信位
相設定回路6では、送信位相切換基準信号4をもとに送
信位相を、第1送信位相メモリ3aからの値と第2送信
位相メモリ3bからの値とを切り換えて後段の送信受信
位相設定回路7へ送り出す。従って、送信受信位相設定
信号8は送信期間中に2種類の送信位相の設定が可能に
なる。
Further, in the transmission / reception phase switching circuit 7, based on the transmission / reception switching reference signal 11, the reception phase set value read from the reception phase memory 2 in the reception period is transferred to a phase shifter in a transmission / reception module (not shown) at the subsequent stage. During the transmission period, the transmission phase transmitted from the transmission phase setting circuit 6 is transmitted to a subsequent phase shifter (not shown). At this time, the transmission phase setting circuit 6 switches the transmission phase between the value from the first transmission phase memory 3a and the value from the second transmission phase memory 3b based on the transmission phase switching reference signal 4, and transmits the signal at the subsequent stage. The signal is sent to the reception phase setting circuit 7. Therefore, the transmission / reception phase setting signal 8 can set two types of transmission phases during the transmission period.

【0006】[0006]

【発明が解決しようとする課題】従来の制御回路は以上
のように構成されているので、送信受信位相を切り換え
るための信号と、2種類の送信位相を切り換えるための
信号を送受信モジュールに送らねばならず、送る側の回
路での処理も複雑なものであった。さらに、送受信モジ
ュールのインタフェース用のコネクタのピン数を減らす
ための障害の原因ともなるという問題点があった。
Since the conventional control circuit is constructed as described above, a signal for switching the transmission / reception phase and a signal for switching the two types of transmission phases must be sent to the transmission / reception module. In addition, the processing on the sending side was complicated. Further, there is a problem that it may cause a failure to reduce the number of pins of the interface connector of the transmission / reception module.

【0007】この発明は上記のような問題点を解消する
ためになされたもので、送信受信位相を切り換えるため
の信号と、送信位相を切り換えるための信号を1種類の
信号にまとめ、インタフェースの処理を容易にするとと
もに、インタフェース用のコネクタのピン数を減らすこ
とのできる制御回路を得ることを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. A signal for switching a transmission / reception phase and a signal for switching a transmission phase are combined into one type of signal, and an interface process is performed. And a control circuit capable of reducing the number of pins of an interface connector.

【0008】[0008]

【課題を解決するための手段】この発明に係る制御回路
は、送信受信切換信号の送信期間の間に短い受信期間を
設けて送信期間を分割した単一の基準信号を用い、送信
受信の切換と、複数の送信位相の選択切換を行うように
したものである。
A control circuit according to the present invention uses a single reference signal obtained by dividing a transmission period by providing a short reception period between transmission periods of a transmission / reception switching signal and switching transmission / reception. And selection switching of a plurality of transmission phases.

【0009】また、受信期間の長さをモニタし、通常の
受信期間と異なる長さの受信信号を検出する切換信号検
出手段を設け、該検出手段出力でもって、送信位相を変
化させるようにしたものである。
Further, switching signal detecting means for monitoring the length of the receiving period and detecting a received signal having a length different from the normal receiving period is provided, and the transmission phase is changed by the output of the detecting means. Things.

【0010】[0010]

【作用】この発明においては、送信受信切換信号の送信
期間の間に短い受信期間を設けて送信期間を分割した単
一の基準信号を用い、送信受信の切換と、複数の送信位
相の選択切換を行うようにしたから、送受信モジュール
と外部との信号インタフェースを簡易にすることができ
る。
According to the present invention, switching of transmission / reception and selection switching of a plurality of transmission phases are performed by using a single reference signal obtained by dividing a transmission period by providing a short reception period between transmission periods of a transmission / reception switching signal. The signal interface between the transmitting / receiving module and the outside can be simplified.

【0011】また、受信期間の長さをモニタし、通常の
受信期間と異なる長さの受信信号を検出する切換信号検
出手段を設け、該検出手段出力でもって、送信位相を変
化させるようにしたから、外部からの制御なしに確実に
位相設定することができる。
Further, switching signal detecting means for monitoring the length of the reception period and detecting a reception signal having a length different from the normal reception period is provided, and the transmission phase is changed by the output of the detection means. Therefore, the phase can be reliably set without external control.

【0012】[0012]

【実施例】図1はこの発明の一実施例による制御回路の
ブロック図であり、図3と同一符号は同一または相当部
分を示し、41は従来の送信受信切換信号の送信区間を
複数に区切った送信受信切換信号、5は送信受信切換信
号41をもとにして送信位相の同期をとる自己同期回路
であり、受信時間の長さを検出することによって、同期
をとるものである。61は送信受信切換信号41と自己
同期回路5からの同期信号によって送信位相を切り換え
て設定する送信位相設定回路である。また図1(b) は上
記送信受信切換基準信号41、及び送信受信位相設定信
号8のタイミングチャートである。
1 is a block diagram of a control circuit according to an embodiment of the present invention. The same reference numerals as in FIG. 3 denote the same or corresponding parts, and 41 designates a conventional transmission / reception switching signal transmission section divided into a plurality of sections. The transmission / reception switching signal 5 is a self-synchronizing circuit for synchronizing the transmission phase based on the transmission / reception switching signal 41, and synchronizes by detecting the length of the reception time. Reference numeral 61 denotes a transmission phase setting circuit that switches and sets the transmission phase according to the transmission / reception switching signal 41 and the synchronization signal from the self-synchronization circuit 5. FIG. 1B is a timing chart of the transmission / reception switching reference signal 41 and the transmission / reception phase setting signal 8.

【0013】次に動作について説明する。上記のように
構成された制御回路1において、送信受信切換基準信号
41をもとにして、送信受信切り換え回路9では送信期
間に送信系のRFデバイスをONし、受信系のRFデバ
イスをOFFし、スイッチ等を送信側に切り換える等の
駆動信号10を発生して、送受信モジュールを送信状態
とする。一方、受信期間では、送信系RFデバイスをO
FFし、受信系RFデバイスをONし、スイッチ等を受
信側に切り換え、送受信モジュールを受信状態とする。
Next, the operation will be described. In the control circuit 1 configured as described above, based on the transmission / reception switching reference signal 41, the transmission / reception switching circuit 9 turns on the transmission RF device and turns off the reception RF device during the transmission period. , A drive signal 10 for switching a switch or the like to the transmission side, and the transmission / reception module is set to the transmission state. On the other hand, during the reception period, the transmitting RF device is turned off.
FF is performed, the receiving RF device is turned on, a switch or the like is switched to the receiving side, and the transmitting / receiving module is set to the receiving state.

【0014】しかしながら本実施例では、送信受信切換
基準信号41の受信期間中において、所定期間パルスが
反転した部分があり、自己同期回路5で受信期間を常時
モニタし、上記パルス反転期間がある一定の長さ以上継
続すると、その次の送信期間を第2送信位相にセットす
るよう、送信位相設定回路6にトリガ信号Tを送る。
送信位相設定回路6では、そのトリガ信号Tを受けた
後の送信期間に適応するように、順番に第1送信位相,
第2送信位相を設定する。
However, in the present embodiment, during the reception period of the transmission / reception switching reference signal 41, there is a portion where the pulse is inverted for a predetermined period. continuing the above length, so as to set the next transmission period to the second transmission phase, and sends the trigger signal T to the transmitting phase setting circuit 6 1.
In the transmission phase setting circuit 61, to accommodate transmission period after receiving the trigger signal T, a first transmission phase in order,
Set the second transmission phase.

【0015】そして送信受信位相設定回路7では送信受
信切換基準信号41をもとにして、受信期間では受信位
相メモリ2から読み出した受信位相設定値を後段の図示
しない送受信モジュール内の移相器へ送り出し、送信期
間には以上のようにして切り換えられた第1送信位相と
第2送信位相とを入力とする送信位相設定回路61から
送られてくる送信位相を図示しない後段の移相器へ送り
出す。
In the transmission / reception phase setting circuit 7, based on the transmission / reception switching reference signal 41, the reception phase setting value read from the reception phase memory 2 during the reception period is transmitted to a phase shifter in a transmission / reception module (not shown) at the subsequent stage. During the transmission period, the transmission phase transmitted from the transmission phase setting circuit 61 having the first transmission phase and the second transmission phase switched as described above as inputs is transmitted to a subsequent phase shifter (not shown). .

【0016】なお上記受信期間において、短い期間、送
信受信切換基準信号41が反転することで送信受信位相
設定回路7において、送信状態から受信状態に切り換え
られその出力に短い受信位相が現れるが、これは送信受
信切換基準信号41のタイミングを用いる等して後段の
回路で容易に処理することができ、動作上は何ら支障を
来すことがない。
In the above-mentioned reception period, the transmission / reception switching reference signal 41 is inverted for a short period, so that the transmission / reception phase setting circuit 7 switches from the transmission state to the reception state, and a short reception phase appears at the output. Can be easily processed by a subsequent circuit by using the timing of the transmission / reception switching reference signal 41 or the like, and there is no problem in operation.

【0017】このように本実施例によれば、送信受信切
換基準信号41に、その送信期間中に短い期間パルス反
転させた部分を設け、自己同期回路5にて、この短いパ
ルス反転期間を検出して送信位相設定回路61にトリガ
信号Tを発し、第1送信位相メモリ3aと第2送信位相
メモリ3bとを切り換えるようにしたから、1種類の信
号でもって送信受信位相を切り換えるとともに、送信位
相を切り換えることができ、インタフェースの処理を容
易にするとともに、インタフェース用のコネクタのピン
数を減らすことができる。
As described above, according to the present embodiment, the transmission / reception switching reference signal 41 is provided with a portion in which the pulse is inverted for a short period during the transmission period, and the self-synchronization circuit 5 detects the short pulse inversion period. As a result, a trigger signal T is issued to the transmission phase setting circuit 61 to switch between the first transmission phase memory 3a and the second transmission phase memory 3b. Can be switched, interface processing can be facilitated, and the number of pins of the interface connector can be reduced.

【0018】なお上記実施例では、送信位相を2種類設
定する場合について示したが、送信位相の数がこれに限
られるものではなく、例えば3種類になってもよい。図
3を用いて本発明の第2の本実施例を説明すると、この
実施例は図3(a) に示すように、第3送信位相メモリ3
cを新たに追加し、送信位相切換回路6を3種類の位
相設定に対応するよう構成し、図3(b) に示すような送
信受信切換基準信号42を用いるようにしたものであ
る。
In the above embodiment, the case where two types of transmission phases are set has been described. However, the number of transmission phases is not limited to this, and three types may be used. The second embodiment of the present invention will be described with reference to FIG. 3. This embodiment is, as shown in FIG.
The c newly added, configured to accommodate the transmission phase switching circuit 6 2 to 3 kinds of the phase setting, in which to use a transmission reception switching reference signal 42 as shown in FIG. 3 (b).

【0019】このように構成することで、自己同期回路
5にて、2種の送信位相設定の場合と同様に受信期間を
常時モニタし、ある一定時間以上の反転パルスを検出し
たらトリガ信号Tを発し、送信位相設定回路6にて、
次の送信期間から順に、第1送信位相,第2送信位相,
第3送信位相が出力されるよう、第1送信位相メモリ3
a,第2送信位相メモリ3b,第3送信位相メモリ3c
を切り換えて出力することにより、より多くの送信位相
の値を用いた制御を行うことができる。
With such a configuration, the self-synchronization circuit 5 constantly monitors the reception period as in the case of setting two types of transmission phases, and when the inversion pulse for a certain time or more is detected, the trigger signal T is generated. issued at transmission phase setting circuit 6 2,
The first transmission phase, the second transmission phase,
The first transmission phase memory 3 so that the third transmission phase is output.
a, second transmission phase memory 3b, third transmission phase memory 3c
By switching and outputting, control using more transmission phase values can be performed.

【0020】[0020]

【発明の効果】以上のように、この発明に係る制御回路
によれば、送信受信切換信号の送信期間の間に短い受信
期間を設けて送信期間を分割した単一の基準信号を用
い、送信受信の切換と、複数の送信位相の選択切換を行
うようにしたから、送受信モジュールと外部とのインタ
フェースの信号を減らすことができ、また送受信モジュ
ールのインタフェース用端子を削減することができ、そ
の結果装置の小型化を図ることができるという効果があ
る。
As described above, according to the control circuit of the present invention, a short reference period is provided by providing a short reception period between the transmission periods of the transmission / reception switching signal, and the transmission is performed using a single reference signal. Since reception switching and selection switching of a plurality of transmission phases are performed, signals at the interface between the transmission / reception module and the outside can be reduced, and the number of interface terminals of the transmission / reception module can be reduced. As a result, There is an effect that the size of the device can be reduced.

【0021】また、受信期間の長さをモニタし、通常の
受信期間と異なる長さの受信信号を検出する切換信号検
出手段を設け、該検出手段出力でもって、送信位相を変
化させるようにしたから、送信位相の設定数が増加して
も確実に位相を設定することができるという効果があ
る。
Further, switching signal detection means for monitoring the length of the reception period and detecting a reception signal having a length different from the normal reception period is provided, and the transmission phase is changed by the output of the detection means. Therefore, there is an effect that the phase can be reliably set even if the number of set transmission phases increases.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の一実施例による制御回路を示すブロ
ック図である。
FIG. 1 is a block diagram showing a control circuit according to one embodiment of the present invention.

【図2】この発明の第2の実施例による制御回路を示す
ブロックー図である。
FIG. 2 is a block diagram showing a control circuit according to a second embodiment of the present invention.

【図3】従来の制御回路を示すブロック図である。FIG. 3 is a block diagram showing a conventional control circuit.

【符号の説明】[Explanation of symbols]

1 制御回路 2 受信位相メモリ 3a 第1送信位相メモリ 3b 第2送信位相メモリ 3c 第3送信位相メモリ 4,41,42 送信位相切換基準信号 5 自己同期回路(切換信号検出手段) 6,61,62 送信位相設定回路 7 送信受信位相設定回路 8 送信受信位相設定信号 9 送信受信切換回路 10 送信受信切換信号 11 送信位相切換基準信号1 the control circuit 2 receives the phase memory 3a first transmission phase memory 3b second transmission phase memory 3c third transmission phase memory 4 and 41, 42 transmits the phase switching reference signal 5 self-synchronous circuit (switching signal detecting means) 6 and 61, 62 Transmission phase setting circuit 7 Transmission / reception phase setting circuit 8 Transmission / reception phase setting signal 9 Transmission / reception switching circuit 10 Transmission / reception switching signal 11 Transmission phase switching reference signal

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 第1の基準信号により複数の送信位相の
1つを選択して出力する送信位相設定手段と、該送信位
相設定手段出力と受信位相とを受け、第2の基準信号に
より上記選択された送信位相と上記受信位相とを切り換
えて出力する送信受信位相設定手段とを有する制御装置
において、 上記第1及び第2の基準信号に代えて、送信期間中に上
記送信位相設定手段出力を切り換える信号成分を含む単
一の基準信号を用いて、上記送信位相設定手段と上記送
信受信位相設定手段を制御するようにしたことを特徴と
する制御回路。
1. A transmission phase setting means for selecting and outputting one of a plurality of transmission phases according to a first reference signal; receiving the output of the transmission phase setting means and a reception phase; A control device having transmission / reception phase setting means for switching and outputting the selected transmission phase and the reception phase, wherein the transmission phase setting means outputs during a transmission period instead of the first and second reference signals. A control circuit for controlling the transmission phase setting means and the transmission / reception phase setting means using a single reference signal including a signal component for switching between the transmission phase setting means and the transmission phase setting means.
【請求項2】 上記単一の基準信号は、その送信期間中
に短い受信期間を有するものであり、 該短い受信期間を検出し、上記送信位相設定手段出力に
切換要求信号を出力する切換信号検出手段を設け、 上記切換要求信号を用いて上記複数の送信位相を切り換
えるようにしたことを特徴とする請求項1記載の制御回
路。
2. The switching signal according to claim 1, wherein the single reference signal has a short reception period during the transmission period, and detects the short reception period and outputs a switching request signal to an output of the transmission phase setting means. 2. The control circuit according to claim 1, further comprising detecting means for switching the plurality of transmission phases using the switching request signal.
JP3269992A 1991-09-20 1991-09-20 Control circuit Expired - Fee Related JP2634340B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3269992A JP2634340B2 (en) 1991-09-20 1991-09-20 Control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3269992A JP2634340B2 (en) 1991-09-20 1991-09-20 Control circuit

Publications (2)

Publication Number Publication Date
JPH0583156A JPH0583156A (en) 1993-04-02
JP2634340B2 true JP2634340B2 (en) 1997-07-23

Family

ID=17480059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3269992A Expired - Fee Related JP2634340B2 (en) 1991-09-20 1991-09-20 Control circuit

Country Status (1)

Country Link
JP (1) JP2634340B2 (en)

Also Published As

Publication number Publication date
JPH0583156A (en) 1993-04-02

Similar Documents

Publication Publication Date Title
JP2634340B2 (en) Control circuit
EP0268664B1 (en) A method of coupling a data transmitter unit to a signal line and an apparatus for performing the invention
US4254401A (en) Local device in a control information transfer system
US5481753A (en) I/O device having identification register and data register where identification register indicates output from the data register to be an identifier or normal data
JPS6040749B2 (en) serial transmission device
US5008802A (en) Dynamic input method and apparatus for programmable controller
KR100406967B1 (en) Parallel Port Multiple Input Expansion Unit
JP2550891B2 (en) Line switching device
JP2682438B2 (en) Transmission transmission frame correction method when switching the clock redundancy system
JP2724323B2 (en) Signal switching device and signal switching method
JP2663487B2 (en) Digital communication equipment
JP3355830B2 (en) Transmission / reception module
JP3246096B2 (en) Self-diagnosis device for digital equipment
JPH02114734A (en) Timing clock control circuit
JP2730148B2 (en) Control start pulse generation circuit
JP3239371B2 (en) Device connection processing method
JP3160927B2 (en) Loop test circuit
JPH02202137A (en) Switching system for digital transmission line
JP2571007B2 (en) Bipolar signal switch
EP0667058B1 (en) A method and a device for a changeover of asynchronous clock signals
JP3516152B2 (en) Synchronization establishing device
JPS62123541A (en) Control system for reception data buffer
JPS62205442A (en) Alarm detecting system
JPH0993145A (en) Transmission output control system
JPS6379434A (en) Reception data switching device

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees