JP2628506B2 - Digital filter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a waveform shaping filter using digital signal processing.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional digital filter 10. In the figure, reference numeral 1 denotes an analog signal input terminal, and 2 denotes an A / A converter for sampling an analog signal input to the input terminal 1 at a high speed and converting it into a digital signal. A D-converter 3, a product-sum operation circuit for receiving the digital signal output from the A / D converter 2 as an input and accumulatively adding the product with the coefficient data stored therein, and a product-sum operation circuit 4 A digital filter output terminal for outputting the result of 3; a clock input terminal 5 for N times the symbol rate (f _CLK ) of the analog signal input to the input terminal 1; 11 a D / A connected to the output terminal 4
It is a converter.

Next, the operation will be described. The analog signal input to the input terminal 1 is first sampled at a high speed by the A / D converter 2 and converted into a digital signal. Below,
The processing of the digital signal will be mainly described. Here, the digital signal processing operation is a finite impulse response (FIR) operation, and its relational expression can be expressed by the following expression.

Here, {x _m } is a discrete-time input sequence, {y _m } is a discrete-time output sequence, and {h _n } is a system impulse response sequence.

FIG. 5 shows a response example of a well-known filter. FIG. 5 (A) shows a filter 20 when an impulse signal is input.
FIG. 5B shows that the impulse response is sampled every period T and the amplitude value at that time is {h ₀ , h ₁ ,..., H _n }. This corresponds to the impulse response sequence {h _n } of the system shown in the equation (1), and is also called a tap coefficient.

This type of filter can usually be realized by a unit delay element having a delay time T, a multiplier and an adder. FIG. 6 is a block diagram showing an (n + 1) -order FIR filter for realizing the above equation (1). In FIG. 6, reference numeral 30 denotes an input terminal of the accumulating circuit 3, and 310 to 318 input to this input terminal 30. The shift register 300 is a unit delay element that delays data by a unit delay amount (T = 1 / N.f _CLK ). 320-329 multiplier which performs the product of the output data of the delay elements 310 - 318, and tap coefficients h ₀ to h _n which is already stored, 33 adds the outputs of these multipliers 320 to 329 An adder 34 is a data output terminal for outputting the addition result of the adder 33.

Next, the operation will be described. Data x _n input to the input terminal 30, tap coefficients h ₀ at the same time is input to the unit delay element 310 is input to the first multiplier 320 loaded. The first multiplies the multiplier 320 the input data x _n and the load coefficient values h ₀ is executing x _n · h ₀ is output. The other multipliers 321 to 329 perform the same operation, but FIG. 6 shows the operation of the filter at time n.

That is, the first multiplier 320 is given a x _n becomes the input data, given the input data and the coefficient value h ₁ comprising x _n-1 delayed by the unit delay element 310 in the second multiplier 321 Can be Similarly to the multiplier 329 of the final stage is given the input data and the coefficient value h _n consisting x _0, is in each multiplier 320-329 coefficient data h ₀ to h _n and the input data x _n ~x ₀ After the multiplication, the data is added by the adder 33 and output data y _n is output to the output port 34.
Is output as In this way, the operation expression shown in Expression (1) is executed.

As is well known, the transfer function of a filter that can obtain the output represented by the above equation (1) is given by Z = e ^ST . And the frequency characteristic is H (e ^jωT ) = | H (e ^jωT ) | q ^{jθ (ω)}
It is represented by (3).

In designing a digital filter, the tap coefficients {h ₀ , h ₁ ,..., H _n } are determined so as to satisfy a desired frequency characteristic or a desired time-domain characteristic.

A Nyquist filter that performs waveform shaping of an input signal using such a filter, identifies its output for each clock synchronized with it, and obtains final data will be considered.

FIG. 7A shows an input signal waveform at a point (a) of the digital filter 10, and FIG.
(B) of the D / A converter 11 for converting the output of the
5 shows an example of an output signal waveform at a point.

Although the input signal waveform indicates a filter input signal whose band is limited, all possible combinations of pulse waveforms are shown in a superimposed form in the figure.

This is obtained by linearly combining band-limited single pulse responses for all combinations, and is called an eye pattern.

The output signal waveform is an eye pattern when a Nyquist waveform is generated from the input signal waveform through the digital filter 10, and the single pulse response shown in FIG. This is obtained as a result of overlapping the combinations.

7 (B) and 7 (C) are plotted every T seconds (T = 1 / N · f
_CLK ) has a stepped waveform because the product-sum operation by the digital filter 10 is performed at a period of T seconds.

Normally, the output signal waveform obtained at the point (b) is sampled at an identification time every N · T seconds indicated by an arrow, and the data is reproduced by determining whether the transmission data is “0” or “1”. I do.

In FIG. 7 (B), the waveform at the point (b) is shown assuming that the A / D converter 2 and the product-sum operation circuit 3 operate at N · f _CLK where N = 4.

[Problems to be solved by the invention]

Since the conventional digital filter is configured as described above, the product-sum operation circuit needs a high-speed operation every T seconds even though the identification data as the final output is every NT seconds. In addition, among the calculation results, the required final output is one out of N and the remaining N-1 are unnecessary data.

The present invention has been made to solve the above problems, and the first invention enables low-speed processing and can cope with an equivalently higher information transmission speed. Also, the second
It is an object of the present invention to obtain a small digital filter by halving the number of multipliers when tap coefficients are symmetrical.

[Means for solving the problem]

The digital filter according to the first aspect of the present invention includes: delay means for sequentially delaying the digitally converted input signal by an N-fold clock signal; N-divider means for dividing the N-fold clock signal by 1 / N; Phase shifting means for changing the phase of the output clock of the N frequency divider, holding means for holding the output of the delay means at the phase timing of the phase shifting means, and calculation based on a predetermined coefficient of the holding means Calculation means.

A digital filter according to a second aspect of the present invention includes: a delay unit for sequentially delaying the digitally converted input signal by an N-fold clock signal; an N-divider unit for dividing the N-fold clock signal by 1 / N; Phase shifting means for changing the phase of the output clock of the N frequency divider; holding means for holding the output of the delay means at the phase timing of the phase shifting means; It comprises a first calculating means for calculating outputs and a second calculating means for calculating the calculation result of the first calculating means with the equal coefficient.

[Action]

The digital filter according to the first invention has an A / D
By latching the input data coefficients with a low-speed clock obtained by dividing the sampling clock used in the converter, the product-sum operation is finally executed only for the input data at the time required for identification, and the number of operations is reduced. It is possible to reduce and equivalently operate at higher speed.

The digital filter according to the second aspect of the present invention includes:
After adding the input data to the multipliers having the same tap coefficient value, the data is input to the multiplier, thereby reducing the number of the multipliers by half and downsizing.

〔Example〕

An embodiment of the first invention will be described below with reference to the drawings. In FIG. 1 where the same reference numerals are given to the same parts as in FIGS. 4 and 6, reference numeral 500 denotes an N frequency divider which divides the clock N.f _CLK inputted to the clock input terminal 5 by N and outputs it.
Is a phase shifter as a frequency dividing means for changing the phase of the output clock of the N frequency divider 500. The data latched by the latch circuit 400 is supplied to multipliers 320 to 323, and the outputs of the multipliers 320 to 323 are added by an adder 33 and output to an output terminal. You.

Next, the operation will be described. Symbol rate is f
Analog signal equivalent to _CLK (symbol / second) is input terminal 1
And is sampled by the A / D converter 2 every 1 / N · f _CLK cycle, converted into digital data, and shifted by the shift register.
Enter 300. The shift register 300 is N · f _CLK becomes the unit delay amount by the clock frequency T (= 1 / N · f CLK)
Only the input data is shifted to the right.

On the other hand, the N-fold clock N · f _CLK is frequency- _divided by the N frequency divider 500 to have a frequency of f _CLK , and then the phase is shifted by the phase shifter 510. The phase shifter 510, for example, as the phase of the clock f _CLK as shown in FIG. 7 (B) may take the N, Kutsuku phase {0, 1, 2, 3, ..., N} for each of the waveform Has no effect on the calculation for generating the waveforms of the other phases.
Input data that gives an operation result corresponding to
The phase is selected such that the shift register 300 is latched to the latch circuit 400.

Figure 2 for clock f _CLK phase of N divider, N =
Four examples are shown. Accordance connexion, the signal processing operation to be carried out by the product-sum operation circuit 3 of FIG. 1, when t = mτ (τ = 1 / f CLK), if the output sequence y _m of the discrete time system and the (1) At t = (m + 1) τ after one symbol At t = (m + 2) τ after two symbols become that way. In this way, the necessary final output can be obtained by one product-sum operation per symbol.

FIG. 1 shows a configuration in which after the data of the shift register 300 is latched by the latch circuit 400, these data are each subjected to a desired operation as input data of separate multipliers 320 to 323. If the numbers {h ₀ , h ₁ , ... h _n } are symmetrical about the center, In this case, the number of multipliers can be almost reduced.

FIG. 3 is a block diagram showing a digital filter according to an embodiment of the second invention. In FIG. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals. Latch circuit
The output of 400 has the same tap coefficient value and is input to adders 330 to 332 as first calculating means.
The outputs of 330 to 332 are used as multipliers 320 to 3 as second calculating means.
It becomes 22 input data.

Next, the operation of the digital filter having the configuration shown in FIG. 3 will be described. A / D input signal input to input terminal 1
After conversion into digital data by the converter 2, the data is input to the shift register 300, and only the necessary data is latched and latched by the latch circuit 400 in the same manner as in the invention of the embodiment shown in FIG. It is.

The data latched by the latch circuit 400 preliminarily adds data input to the multipliers having the same tap coefficient value to an adder.
Addition is performed by 330 to 332, and the addition result is calculated by multipliers 320 to 3
Tap coefficient value as input data of 22 (N: odd number) or (N: even number) and multiplication.

After the multiplication results of the multipliers 320 to 322 are added by the adder 33,
The data is output from the output terminal 4 as digital filter output data. This makes it possible to execute the required number of operations only once per symbol while halving the number of multipliers.

In the above embodiment, the multipliers 320 to 322 are shown as being built-in, but this is a read-only memory (Read-only memory) in which the multiplication result according to the input data and the tap coefficient is written.
Only a memory (ROM) may be provided internally or externally to take in the multiplication result.

In the embodiment of the digital filter 10, the latch circuit
Although 400 is placed only on the output side of the shift register 300, a latch circuit having a data latch function such as a flip-flop is appropriately inserted in the middle of the signal transmission path according to the actual operation speed of the multiplier or adder, and the pipe is inserted. Even if the line processing is performed, the same effect as in the above embodiment can be obtained.

〔The invention's effect〕

As described above, according to the first aspect, when the input data sequence is latched by the low-speed clock, the timing is controlled so that the final operation which is considered to have the highest data reliability among the high-speed sample data is performed. Since the product-sum operation is performed only for the input data related to the result, the number of operations can be reduced, and an equivalently faster operation can be achieved.

Further, according to the second aspect of the present invention, since data having the same predetermined tap coefficient value among the latched data is added to each other, and then the data is input to the multiplier, the number of multipliers is reduced. There is an effect that it is possible to reduce the size and cost of the device by halving it.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a digital filter according to an embodiment of the first invention, FIG. 2 is a time chart for explaining a clock after frequency division in FIG. 1, and FIG. FIG. 4 is a block diagram showing a conventional digital filter according to an embodiment of the second invention, FIG. 4 is a block diagram showing a conventional digital filter, FIG. 5 is a diagram showing an example of an impulse response of the digital filter, and FIG. FIG. 7 is a detailed block diagram of a product-sum operation circuit which is a component of the digital filter. FIG. 7 is a diagram showing an example of input / output waveforms of the digital filter. 2 is an A / D converter, 3 is a product-sum operation circuit, 300 is a shift register, 400 is a latch circuit, 320 to 323 are multipliers, and 33,330 to 332
Is an adder, 500 is an N divider, and 510 is a phase shifter. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. A delay means for sequentially delaying a digitally converted input signal by an N-fold clock signal, an N-divider means for dividing the N-fold clock signal by 1 / N, and an output of the N-divider. Phase shifting means for changing the phase of the clock, holding means for holding the output of the delay means at the phase timing of the phase shifting means, and calculating means for calculating based on a predetermined coefficient of the holding means. Digital filter. 2. A delay means for sequentially delaying a digitally converted input signal by an N-fold clock signal, an N-divider means for dividing the N-fold clock signal by 1 / N, and an output of the N-divider. A phase shifter that changes the phase of the clock, a holding unit that holds the output of the delay unit at the phase timing of the phase shifter, and outputs that are calculated using the same coefficient among the outputs of the holding unit, respectively. A digital filter, comprising: a first calculating means; and a second calculating means for calculating a calculation result of the first calculating means with the equal coefficient.