JP2624375B2 - IC memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an IC memory.

[Conventional technology]

FIG. 3 is a block diagram of a memory (data width is 4 bits) of a conventional IC.

The input / output control signal group 360 is input to the control circuit 361, and as its output, control signals for memory access and input / output are generated. The control signal and the address input signal 301 are input to the address decode circuit 302, and a memory selection signal 303 corresponding to each of all address values is output as an output thereof. The memory block 310 (for bit 0), the memory block 311 (for bit 1), the memory block 312 (for bit 2), and the memory block 313 (for bit 3) corresponding to each bit transmit the memory selection signal 303 to the memory in the block. Each cell is input as a selection signal, and the selected memory cell is associated with each of the data lines 330 to 333. Four data input / output buffers 340 to 343 corresponding to each bit
Performs input / output between the data signal line 350 and the previous data lines 330 to 333 according to an input or output designation and access operation request signal from the control circuit 361.

In the case of the IC memory, the input address becomes a common address for each memory block, and the contents of the same address of each memory block are simultaneously accessed by one memory access operation.

[Problems to be solved by the invention]

The above-mentioned conventional IC memory is a method of assigning an address to data in units of a certain specific bit (for example, 8 bits) and inputting / outputting the data. For applications that use this format (e.g., a bitmap display), if you want to specify an address in bit units and input and output data for a certain number of consecutive bits from there, even if the data signal line is Even if the number of bits is equal to or greater than the number of bits, unless the value of the address in bit units is an integral multiple of the number of bits in circuit units, the input / output operation cannot be performed at once, and
There is a drawback that the number of operations is required.

SUMMARY OF THE INVENTION An object of the present invention is to provide an IC memory capable of accessing continuous data having a data width of 2 ⁿ bits from an arbitrary bit position in one access.

[Means for solving the problem]

IC memory of the present invention, the address input of the m, 2 ⁿ number of memory blocks, and address decode circuit for outputting a memory selecting signal of 2 ^m this than the address input of the m lines, the 2 ⁿ consecutive bits N bit address inputs for specifying which bit of data to access, n access width specification inputs for specifying how many bits are to be accessed at the same time, and an input / output control signal for specifying read / write for a memory block A group and 2 ⁿ shift circuits that are provided for each memory block, shift 2 ^m memory select signals from the address decode circuit by 0 or 1 bit according to an address shift request signal, and output to the memory block; 2 ⁿ data input / output buffers provided for each memory block and holding data written to or read from the memory A control circuit that inputs the input / output control signal group, the bit address input, and the access width designation input, outputs an access request signal to each memory block and each data input / output buffer, and outputs an address shift request signal to each shift circuit. Have.

[Action]

The bit address input and the access width designation input are input, and the memory selection signal of the memory block of the bit preceding the bit designated by the bit address input among the 2 ^m memory selection signals is shifted by one bit. With a single access, data with a data width of 2 ⁿ bits can be accessed from any bit position.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an IC memory (1K × 4 bit IC memory) according to an embodiment of the present invention, and FIG. 2 is a block diagram of shift circuits 120 to 123 in FIG.

Ten address inputs 101 are input to the address decode circuit 102, and 1024 memory selection signals 103 are output. The memory selection signal 103 is not directly input to the memory blocks 110 to 113, is input to the memory block 110 via the shift circuit 120, and is input to the memory block 111.
Is input to the memory block 112 and the shift circuit 1
The data is input to the memory block 113 via the shift circuit 123. Each memory block 110-113
The memory cell selected in the above-mentioned manner is connected to each data input / output buffer 140, data input / output buffer 141, data input / output buffer 142, and data input / output buffer 143 via the data signal lines 130 to 133 in the same manner as in the above-described conventional example. Is connected to the data signal line 150 to perform input / output.

In this embodiment, an input / output control signal group 160 similar to the conventional example and two bit address input signals 162 for designating which bit of the newly added four bit data is to be accessed are provided to the control circuit 161. And two access width designation input signals 163 for designating how many bits are to be accessed at the same time, and shift control signals 170-1 to shift circuits 120-123.
Outputs 73. The shift control signals 170 to 173 are
For 120 to 123, it is composed of two signals of an access request signal and an address shift request signal. Table 1 shows the correspondence between input signals and output signals of the control circuit 161.

Here, a case is shown in which the input / output control signal group 160 is realized by an access request signal (A) and a write signal (B). Here, the place where "1" is described in the input part has a request, and "0"
Where it is described, there is no request. Further, a place described as “x” indicates that neither 0 nor 1 is related.
The bit address input signal 162 is represented by a two-digit binary number, where “00” is access from bit 0 to the upper direction of data, “01” is access from bit 1 to the upper direction of data, and “10” is access from the bit 1 to the upper direction of data. Similarly, access from bit 2 and “11” mean access from bit 3. The access width designation input signal 163 is represented by a 2-digit binary number, where "00" is a 1-bit access, "01" is a 2-bit access, and "10".
Indicates that 3-bit access is requested, and “11” requests 4-bit access. Further, the portion described as "0" or "1" in the output portion corresponds to a shift circuit in FIG. 2 described later.

In this circuit, for example, the bit address input signal 16
The binary number “10” meaning designation from the position shifted by 2 bits in the upper direction of the data is input to 2, and the binary number “11” indicating 4-bit access is input to the address width designation input signal 163. When the input / output control signal group 160 indicates a read request, the access request signal to all the shift circuits 120 to 123 is 1 from Table 1, and the shift request signal is 1 to the shift circuit 120 and the shift circuit 121. 0 is input to the shift circuit 122 and the shift circuit 123. On the other hand, the address input from the address input 101 is one of the 1024 memory selection signals 103 by the address decode circuit 102.
Only books are activated and output. As a result, the memory cell of the corresponding address is selected in the memory block 113 and the memory block 112. However, the memory block 110 and the memory block 111 are caused by the address shift request signal.
The shift circuit 120 and the shift circuit 121 shift the address of each of the 1024 memory selection signals 103 by one address in the upper direction, and input them to each of the memory blocks 110 and 111 to select the memory cell corresponding to the corresponding address + 1. That is, the address indicated by the current memory selection signal is selected as the upper two bits, and the next address is selected as the lower two bits.
As a result, 4-bit data shifted in the upper direction by 2 bits as a whole is output to the data signal line 150 via the data input / output buffers 140 to 143.

FIG. 2 is a circuit diagram of the shift circuits 120 to 123 in FIG. 201 _{1 to} 201 _{10 24} are 1024 memory selection input signals, 20
5 _{1 to} 205 _{10 24} are data select circuits for selecting one from 1024 two memory select signals, 203 is a shift request signal, 202 is an access request signal, 204 is an inverter, and 206 ₁ to
Reference numerals 206 _{10 24} denote 1024 memory selection output signals which are respectively converted. As can be seen from FIG. 2, the access request signal 202
Is 0, all memory selection output signals 206 _{1 to} 206 _{10 24}
Becomes 0, and all the memory cells are not selected. When the access request signal 202 is 1, if the shift request signal 2030 is the same, all the memory selection output signals 206 _{1 to} 206 _{10 24} output the same contents as the memory selection signals 201 _{1 to} 201 _{10 24} .

On the other hand, the access request signal 202 in the case of 1, each memory selection signal 201 _{2-201 10 24} next with 201 ₁ is output to the memory request output signal 206 _{1-206 10 24.}

Although the number of the data select circuits is 1024, they can be easily realized with a small area because they are regularly arranged in the design of the integrated circuit.

〔The invention's effect〕

As described above, according to the present invention, an address shift request signal is output to a shift circuit by an n-bit address input and an n-bit access width designation input, and a memory selection signal is shifted by 0 or 1 bit, whereby an address of m Width and 2 ⁿ
Data access of IC memory with data width of bit
The data having the continuous data width can be accessed from an arbitrary bit position by one access, and efficient data access is possible when the data is used for an IC memory such as a bit-mapped video RAM.

[Brief description of the drawings]

FIG. 1 is a block diagram of an IC memory according to an embodiment of the present invention, FIG. 2 is a circuit diagram of shift circuits 120 to 123 in FIG. 1, and FIG. 3 is a block diagram of a conventional IC memory. 101 ... address input, 102 ... address decode circuit,
103 memory selection signals, 110 to 113 memory blocks, 120 to 123 shift circuits, 130 to 133 data lines,
140 to 143: data input / output buffer, 150: data signal line, 160: input / output control signal group, 161: control circuit, 16
2 ... bit address input signal, 163 ... access width designation input signal, 201 _{1 to} 201 _{10 24} ... memory selection input signal, 20
2 ... access request signal, 203 ... shift request signal, 204
…… Inverter, 205 _{1 to} 205 _{10 24} …… Data select circuit, 206 _{1 to} 206 _{10 24} …… Memory selection output signal.

 ────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-59-56276 (JP, A) JP-A-63-14395 (JP, A) JP-A-63-14397 (JP, A)

Claims (1)

(57) [Claims] 1. A memory IC having an address width of m bits and a data width of 2 ⁿ bits, wherein m address inputs, 2 ⁿ memory blocks, and 2 ^m addresses from the ^m address inputs An address decode circuit that outputs a memory selection signal of ^n, an n-bit address input that specifies which bit of consecutive 2 ^n- bit data is to be accessed, and an n-address that specifies how many bits are to be accessed at the same time A width designation input, an input / output control signal group for designating read / write for each memory block, and a 2 ^m memory selection signal from the address decode circuit, which is provided for each memory block, is set to 0 or 2 ⁿ shift circuits that shift by one bit and output to the memory block; provided for each memory block; written to the memory;
Or, input ²ⁿ data input / output buffers for holding data to be read, input / output control signal group, bit address input, and access width designation input, and request access to each memory block and each data input / output buffer. An IC memory having a control circuit that outputs a signal to each shift circuit to output an address shift request signal.