JP2619524B2 - Ghost detection reference signal extraction circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ghost detection reference signal extraction circuit that constitutes a ghost removal device installed in a television receiver.

(Prior Art) Some television receivers have a built-in ghost removal device to prevent image quality deterioration due to the appearance of ghosts.

As shown in FIG. 4, the ghost eliminator includes a ghost elimination circuit composed of a transversal filter.
31 and a reference signal extraction circuit for extracting a ghost detection reference signal inserted into a predetermined portion of the received television signal.
32, and a ghost detection circuit 33 that detects a ghost from the distortion of the extracted reference signal waveform and sets a coefficient in a transversal filter of the ghost removal circuit 31.

As the ghost detection reference signal, a signal obtained by superimposing an integrated waveform of an isolated pulse on a pedestal signal of a predetermined line in a vertical blanking period is used. This reference signal is subjected to averaging (accumulation) processing over several hundred fields in order to remove the influence of noise. Further, in order to avoid interference due to the ghost component of the horizontal synchronizing signal and the color burst, it is planned to use an eight-field sequence reference signal as shown in FIG.

That is, 4 out of 8 consecutive fields F1 to F8
For each of the fields F1, F3, F6 and F8, an isolated pulse [(sinX) / X] is applied to each of the pedestal waveforms of a predetermined line (the 18th or 281st line) in the vertical blanking period.
Are integrated and the remaining four fields F2, F4, F5
18th or 281 in the vertical blanking period
A ghost detection reference signal waveform of an eight-field sequence consisting of only the pedestal waveform of the second line is included in the television video signal. Reference signal extraction unit in FIG.
Reference numeral 32 denotes an integrated waveform of an isolated pulse by adding four fields to each other for an integrated waveform of an isolated pulse, and adding and subtracting a horizontal synchronization signal and a color burst signal in a pedestal waveform so as to cancel each other by eight fields. The ghost detection reference signal is extracted while removing the ghost components of the horizontal synchronizing signal and the color burst signal appearing in (1).

That is, in the example of FIG. 5, eight continuous fields Fi
(I = 1 to 8) for the reference signal waveform S _{Fi of, S = (S F1 + S} F3 + S F6 + S F8) - addition and subtraction is performed for _{(S F2 + S F4 + S} F5 + S F7). First, the horizontal synchronization pulse is removed from the addition / subtraction value S of the reference signal waveform by subtracting the added values of the four fields. Since the color burst is inverted between adjacent frames, it is canceled out in (S _F1 + S _F3 ). Similarly, (S _F2 + S _F4 ) is canceled and removed. Since the color burst included in (S _F6 + S _F8 ) and the color burst included in (S _F5 + S _F7 ) have the same amplitude and inverted phases, they are removed by subtraction.

The fact that the horizontal sync pulse itself and the color burst itself are removed in this way is derived from them, that is, they are mixed in the integrated waveform of the isolated pulse with a predetermined delay time and a predetermined attenuation. This means that the ghost component of the horizontal sync pulse and the ghost component of the color burst are similarly canceled out.

Conventionally, when the reference signal extraction circuit 32 of FIG. 4 extracts a reference signal of the 8-field sequence of FIG. 5, as shown in FIG. A switching unit 42 comprising eight switches SW1 to SW8 which are cyclically switched, and an accumulating unit 43 comprising memories M1 to M8 for accumulating one of eight kinds of reference signals supplied via corresponding switches at the preceding stage. And a processor 44 for performing predetermined addition and subtraction on the reference signals accumulated in the memories M1 to M8 of the accumulating unit, and writing to the memories M1 to M8 by controlling the opening and closing of the switches SW1 to SW8 of the switching unit 42. And a writing control unit 45 for controlling.

Prior to the start of the extraction of the reference signal repeated at a substantially constant cycle, all the memories M1 to M8 are cleared. The writing control unit 45 extracts the synchronization signal included in the television image signal, and sequentially opens the switches S1 to S8 in one field cycle, thereby storing the reference signal for eight fields in the memory.
Accumulation is sequentially performed on each of M1 to M8. Reference signals for each field and memories M1 to
The relationship of M8 is indeterminate, and the memory allocated for the accumulation of the reference signal in each field may be different each time the reference signal is extracted.

(Problems to be Solved by the Invention) In the ghost detection reference signal extraction circuit shown in FIG. 6, the relationship between the reference signal of each field and the memories M1 to M8 assigned for accumulating them is undefined. The memory allocated for the accumulation of the reference signal in the field can be different for each extraction of the reference signal. For this reason, the processor 44
When starting the addition / subtraction to the reference signal of the field read from the memories M1 to M8, it is necessary to determine by trial and error which memory is allocated for accumulation of the reference signal of which field. There is a problem that the processing time is prolonged.

(Means for Solving the Problems) A ghost detection reference signal extraction circuit according to the present invention is characterized in that a high frequency band is extracted from a television video signal including an eight-field sequence reference signal by a combination of an integrated waveform of an isolated pulse and a pedestal signal. A low-pass filtering section for removing the component, and comparing the output of the low-pass filtering section with a predetermined DC level to determine whether the field is a field containing an integrated waveform of an isolated pulse or a field containing only a pedestal signal. A level comparing section for outputting a value signal, and detecting an array of the binary signal output from the level comparing section over eight fields or four fields of one jump, and if this matches a predetermined array, the effect is detected. Field position detecting means comprising a field array detecting unit for generating a signal for notifying
A reference signal accumulating means for accumulating a reference signal of a predetermined field at a predetermined position based on the detection result of the field position detecting means, and fixing a relation between the reference signal of each field and a memory allocated for accumulation. This eliminates the need for trial and error by software and realizes a high extraction speed.

 Hereinafter, the operation of the present invention will be described in detail with examples.

FIG. 1 is a block diagram showing a configuration of a ghost detection reference signal extraction circuit according to an embodiment of the present invention.
Is the input terminal of the television video signal, 11 is the A / D converter, 12
Is a switching unit, 13 is an accumulation unit, 14 is a processor, 15 is a write control unit, and 16 is a field position detection unit.

The input terminal IN is supplied with a television video signal including a reference signal of the eight-field sequence shown in FIG. The reference signal of each field included in the television image signal is converted into a digital signal by the A / D conversion circuit 11 and then passed through the switches S1 to S8 to the corresponding memories M1 to M8.
, And are read out by the processor 14 to perform predetermined addition and subtraction.

FIG. 2 is a block diagram showing the configuration of the field position detector 16 of FIG. 1, where I is an input terminal, 21 is a clamp circuit, 22 is a synchronization separation / timing generation circuit, 23 is a low-pass filter circuit, 24 Is a comparison circuit, 25 is a field array detector,
O1 is an output terminal of the field position detection signal.

The synchronization separation / timing generation circuit 22 separates a horizontal synchronization signal and a vertical synchronization signal from the television video signal on the input terminal I, and a clamp timing signal and a latch timing signal having a predetermined timing relationship with respect to these synchronization signals. And supplies them to the clamp circuit 21 and the latch circuits L1 to L8 in the array detection unit 25, respectively. The television video signal on the input terminal I is clamped to a predetermined DC level by the clamp circuit 11 which operates upon receiving a clamp timing signal from the sync separation / timing generation circuit 22. This clamped television image signal is supplied to a non-inverting input terminal of a comparison circuit 14 after a high-frequency component is removed in a low-pass filtering circuit 13, and has a predetermined DC level supplied to an inverting input terminal. Be compared.

The predetermined DC level is set substantially at an intermediate level between the level of the pedestal signal and the DC level of the integrated waveform of the isolated pulse. Therefore, if the reference signal (waveform S _{F1 in} FIG. 5) of the first field of the eight-field sequence in which the integral waveform of the isolated pulse is superimposed on the pedestal signal is appearing at the input terminal I, the comparison circuit 24 outputs a high ( The binary signal “1”) is output, and is held in the latch L1 in synchronization with the latch timing signal output from the synchronization / separation timing generation unit 22. Subsequently, when a reference signal (waveform S _{F2 in} FIG. 5) of the second field consisting of only the pedestal signal appears at the input terminal, a low (“0”) binary signal is output from the comparison circuit 24 and latched in the latch L1. Is done. Note that the latch L1
Is held in the latch L2.

In this manner, each time the reference signal of each field appears at the input terminal I, a binary signal of "1" or "0" is output from the comparison circuit 24 depending on whether or not the integrated waveform of the isolated pulse is superimposed. , And are sequentially held in the latches L1 to L8. As a result, immediately after the appearance of the reference signal in the last field of the 8-field sequence, the latches L8 to L1 have "1", "0",
Binary signals are held in the order of “1”, “0”, “0”, “1”, “0”, “1”. The binary signal "1" held in the latches L8, L6, L3, L1 is supplied as it is to the four input terminals of an 8-input AND gate. Further, the binary signal “0” held in the latches L7, L5, L4, L2 is inverted by the inverters I4, I3, I2, I1 to become a binary signal “1”, and the remaining four signals of the 8-input AND gate A are output. Are supplied to the input terminals. As a result, only immediately after the appearance of the reference signal in the last field of the 8-field sequence, 8
The field position detection pulse output from the input AND gate A to the output terminal O1 rises to high.

1 is based on a field position detection pulse supplied from the output terminal O1 of the field position detection circuit 16 and a field pulse supplied from the output terminal 02. The signal is accumulated in the memory M1, the reference signal of the second field is accumulated in the memory M2, and so on.
Controls the opening and closing of S1 to S8. As a result, the processor 14
A predetermined addition / subtraction (S _F1 −S _{F2) is performed on} the reference signals from the first field to the last field accumulated in the memories M1 to M8.
+ S _F3 −S _F4 −S _F5 + S _F6 −S _F7 + S _F8 ) to immediately start the reference signal extraction processing.

FIG. 3 is a block diagram showing another configuration of the field position detection circuit 16 of FIG. 3, the same components as those in FIG. 2 are denoted by the same reference numerals as those in FIG.

The synchronization separation / timing generation circuit 22 generates a clamp timing signal and a latch timing signal having a predetermined timing relationship with respect to the synchronization signal separated from the television video signal, and respectively generates the clamp timing signal and the latch timing signal in the clamp circuit 21 and the array detection unit 25. It is supplied to the latch circuits L1 to L8. The clamp timing signal and the latch timing signal are generated at a frame cycle of every other field. Therefore, the comparison circuit 24
The binary signal output from the
It is held at L1 to L4. As a result, when the reference signal of the last field of the eight-field sequence is latched by the latch L1 in each of the latches L4 to L1, the latch L4 / L1
The binary signals being held at “1”, “1”, “0”, “0”
The field position detection signal output from the input AND gate A1 to the write control circuit 15 of FIG. 1 via the output terminal O1 rises to high. Further, a field pulse generated by the synchronization separation / timing generation circuit 22 is output from the output terminal O2 to the write control circuit 15.

(Effects of the Invention) As described above in detail, the ghost detection reference signal extraction circuit of the present invention compares a low-pass filtered reference signal with a predetermined DC level and determines whether there is an integrated waveform of an isolated pulse. A corresponding binary signal is output, a field position is detected from an array of eight fields of this binary signal or four fields of one jump, and a reference signal of a predetermined field is accumulated at a predetermined location based on the detection result. The reference signal accumulating means is provided to fix the relationship between the reference signal of each field and the memory allocated for each storage. Therefore, unlike the conventional circuit, the reference signal of each field is not subjected to trial and error by software. Is determined, and the effect of increasing the extraction speed is achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a circuit for extracting a ghost detection reference signal according to an embodiment of the present invention, and FIG.
3 is a block diagram showing an example of the configuration of the field position detection circuit 16 in FIG. 3, FIG. 3 is a block diagram showing another example of the configuration of the field position detection circuit 16 in FIG. 1, and FIG. FIG. 5 is a block diagram showing the configuration, FIG. 5 is a waveform diagram exemplifying the waveform of a ghost removal reference signal in an 8-field sequence, and FIG. 6 is a block diagram showing the configuration of a conventional ghost detection reference signal extraction circuit. IN: Input terminal of television video signal including ghost removal reference signal, 11: A / D converter, 12: Switching unit, 1
3: an accumulator composed of memories M1 to M8, 14: a processor for performing a predetermined addition / subtraction to the accumulated reference signal, 15: write control for controlling the opening and closing of switches S1 to S8 of the switching unit 12 Section, 16 ... field position detecting section, I ...
Input terminals, 21: clamp circuit, 22: sync separation / timing generation circuit, 23: low-pass filtering circuit, 24: comparison circuit, 25: field array detection unit, O1: field position detection signal Output terminal, O2 …… Field pulse output terminal.

Claims (1)

(57) [Claims] 1. An integrated waveform of an isolated pulse is superimposed on each of the pedestal waveforms of a predetermined line in a vertical blanking period in four of eight consecutive fields, and the remaining four fields are A television video signal including a ghost detection reference signal waveform of an 8-field sequence consisting of only a pedestal waveform of a predetermined line within a vertical blanking period is received, and a ghost detection reference signal waveform is extracted and accumulated for each field. The accumulated result of each field is added or subtracted so that the integrated waveform of the isolated pulse is added to four fields, and the horizontal synchronization signal and the color burst signal in the pedestal waveform are canceled by eight fields. Synchronization signal and color burst appearing in the integrated waveform of isolated pulse In a ghost detection reference signal extraction circuit for extracting a ghost detection reference signal while removing a ghost component of the signal, a low-pass filtering section for removing a high-frequency component from a television video signal including the reference signal, A level comparing unit that compares an output of the low-pass filtering unit with a predetermined DC level and outputs a binary signal according to whether the field includes an integrated waveform of the isolated pulse or a field of only a pedestal signal; A field position detecting section which detects an array of 8 fields of the binary signal output from the level comparing section or an array of 4 fields of one jump, and generates a signal notifying that the array matches a predetermined array. And a reference signal of a predetermined field is accumulated at a predetermined location based on the detection result of the field position detection circuit. A ghost detection reference signal extraction circuit, comprising: reference signal accumulation control means for accumulating the reference signal.