JP2608422B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to an output circuit for performing signal level conversion, which has high withstand voltage, high speed,
The present invention relates to an output circuit having characteristics excellent in high integration.

[Conventional technology]

Bipolar / CMOS composite technology has been developed with the aim of realizing an LSI that combines bipolar transistor and CMOS in a basic circuit, and has both low power consumption and high integration of CMOS and high speed of bipolar transistor. This bipolar / CMOS composite technology has been applied to memories, gate arrays, etc., and products have already been announced by various companies. An output circuit used for the gate array based on the bipolar / CMOS composite technology is disclosed in, for example, Nikkei Electronics ('85, 8, 12, p196). This circuit diagram is shown in FIG. The basic operation is as follows. The output signal of the internal circuit is input to the CMOS inverter 201. This inverter is an amplifier circuit for making the signal of the internal circuit full amplitude up to the power supply voltage. The output of inverter 201 is 202
, And the NMOS transistors 203 and 204, which drive the bipolar transistors 205 and 206, respectively. For example, “H” is input terminal 207
Is input, the input is inverted by the inverter 201 and becomes "L". Therefore, the PMOS of 202 is on, the NM of 203,204
OS is off, 205 NPN transistor is on, 206 NPN
The PN transistor is turned off, and the output of 208 eventually becomes “H”. Conversely, when “L” is input to the input 207, the inverter 201
As a result, the input is inverted and becomes "H". Therefore, 202 P
MOS is off, NMOS 203 and 204 are on, NPN transistor 205 is off, NPN transistor 206 is on,
Eventually, the output of 208 becomes “L”. As described above, the conventional output circuit receives the internal signal in the CMOS and performs the complementary operation by driving the bipolar by the CMOS, thereby achieving low power consumption.

[Problems to be solved by the invention]

The above prior art is used for a 5V power supply system,
No consideration is given to the withstand voltage of the device when the potential difference of the power supply is large.For example, when used in a power supply system having a potential difference of 10 V, the reliability of the circuit is reduced due to the problem with the withstand voltage of the device. drop down. Or, in the worst case, there is a problem when the circuit malfunctions.

Hereinafter, the problems of the related art will be described in detail. The conventional circuit shown in FIG. 2 has been developed for an LSI used with a single 5V power supply, and as long as it is used with a single 5V power supply, there is no problem with the breakdown voltage, including the margin. However, when used in a power supply system having a potential difference of 10 V or more, a problem in withstand voltage occurs as described below. FIG. 3 (a) shows that within one chip,
The power supply configuration of an LSI having two power supplies of + 5V and -5.2V is shown. Reference numeral 1 denotes a high potential power supply line having a potential of + 5V. Reference numeral 2 denotes a GND line, and reference numeral 3 denotes a low-potential power supply line having a potential of -5.2 V. Such a power supply configuration is necessary, for example, when a signal level of ECL and a signal level of TTL or CMOS are mixed in one chip. Reference numeral 301 denotes an internal circuit, which constitutes a circuit in which bipolar transistors and PMOS and NMOS are mixed. 304 and 305 are ECL input circuits and output circuits, respectively. Input the ECL signal from outside of the chip at 304 and 306
Is converted to an internal signal by the level conversion circuit. Also,
The level of the internal signal is converted by the level conversion circuit 307, and
Outputs ECL signal out of chip. 302 and 303 are TTL respectively
Alternatively, it is a CMOS input circuit and output circuit. The TTL level external signal enters the chip from the input circuit 302 and is output from the output circuit 303 outside the chip. By adopting such a power supply configuration, an LSI in which the ECL / TTL input / output circuits are mixed in one chip is realized. However, such a power supply configuration has the following problems. FIG. 3 (b)
1 shows a longitudinal sectional structure of an LSI. 404 is a P-type substrate, 401 is a bipolar transistor, 402 is a PMOS, 403 is an NMOS, 405
Is a collector, 406 is a PMOS N well, 407 is a PMOS source, and 408 is an NMOS drain. In the case of adopting the power supply configuration shown in FIG. 7A, the P-type substrate 404 is connected to the low potential power supply (-5.2 V) line 3, which is the lowest potential level, in order to achieve PN junction isolation. You. On the other hand, the following voltages are applied to the bipolar transistor 401 and the PMOS 402 and the NMOS 403 used in the internal circuit 301 or the input / output circuits 302 and 303 in FIG. That is, +5 V is applied to the collector 405 of the bipolar transistor 401 and the source 4 of the PMOS 402
07 is + 5V, and PMOS N well 406 is + 5V, NMOS4
+5 V is applied to the drain 408 of 03. At this time,
A voltage of 10.2 V is applied between 404, 406 and 404, 408 and 404, and a voltage of 10.2 V or more is applied in the worst case due to the fluctuation of the power supply potential. In this, the withstand voltage between the bipolar collector 405 and the substrate 404,
Also, the withstand voltage between the PMOS well 406 and the substrate 404 is sufficiently high, and no problem occurs. However, the withstand voltage between the drain 408 of the NMOS 403 and the substrate 404 cannot be said to be sufficiently high, and stable device characteristics cannot be expected. The problem with the withstand voltage of this NMOS is that the TTL input circuit 302 and the level conversion circuit shown in FIG.
306 and 307; an internal circuit 301; and a TTL output circuit 303. Since the drains of the NMOSs of the other circuits 304 and 305 receive only a voltage of 0 V or less, there is no problem of withstand voltage. Thus, the third
In the case of the power supply configuration shown in the figure, the breakdown voltage of the NMOS becomes a problem. Further, it is conceivable to make the power supply configuration as shown in FIG. The internal circuit 301 is connected to the second power supply line 3 and the GND line 2. The ECL signal outside the chip is converted into an internal signal by the input circuit 304, and the internal signal is output to the outside of the chip by the output circuit 305. The TTL signal is input to the input circuit 302 and is converted into an internal signal by the level conversion circuit 306. The internal signal is level-converted by the level conversion circuit 307 and output to the outside of the chip by the output circuit 303. In such a power supply configuration, the ECL input circuit 304, the internal circuit 301, and the ECL output circuit 305 are connected to the second power line 3
Since the maximum voltage applied to these circuits is 5.2 V, there is no problem with the withstand voltage even if power supply variations are taken into consideration. However, TTL input circuit 3
In the 02, level conversion circuit 306, TTL output circuit 303 and level conversion circuit 307, a voltage of +5 V is applied to the drain 408 of the NMOS 403 in FIG.
And a potential difference of 10.2 V is generated between them, and the withstand voltage between the drain and the substrate of the NMOS becomes a problem. Therefore, in the case of the power supply configuration shown in FIG. 4A, the input circuit 302, the level conversion circuits 306 and 307, and the output circuit 303 cannot be formed into a circuit configuration using an NMOS due to a problem in withstand voltage. Therefore, the output circuit 303
In addition, the conventional circuit using the NMOS shown in FIG. 2 cannot be used.

The present invention has been made in view of the above problems, and has as its object to provide an output circuit having high withstand voltage, low power consumption, and high speed.

[Means for solving the problem]

The above-mentioned problem is caused in a reactant integrated circuit device including a PMOS transistor, an NMOS transistor, and a bipolar transistor formed on the same semiconductor substrate, by a first potential which is a potential of the semiconductor substrate and a second potential which is higher than the first potential. And a third potential higher than the second potential is applied to the semiconductor integrated circuit device having a circuit formed by a PMOS transistor and a bipolar transistor between the power supply line of the second potential and the power supply line of the third potential. Will be resolved.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

FIG. 1 shows a first embodiment according to the present invention. In FIG. 1A, 101 and 102 are PMOSs, and 103 and 104 are NPN transistors. The PMOS 101 supplies the base current of the NPN transistor 103, and the 103 is driven. PMOS 102 supplies the base current of NPN transistor 104 and drives 104. Since the input stage is composed of MOS, the input impedance is high,
Since the output stage is composed of bipolar transistors, the output impedance is small and the driving force is high. This circuit is a PM
Since it is constituted by the OS and the NPN transistor, even if the power supply configuration shown in FIG. 4 is used and the substrate potential is -5.2 V, there is no problem in withstand voltage. This is because the only problem with the breakdown voltage is between the substrate and the drain of the NMOS,
This is because there is a sufficiently high breakdown voltage between the bipolar collector and the substrate or between the N well of the PMOS and the substrate.
Therefore, with the circuit configuration shown in FIG. 1A, the first object of increasing the breakdown voltage is achieved. Next, in order to obtain low power consumption, the NPN transistor 103 and the NPN transistor 104 need to perform complementary operations. In order for the transistors 103 and 104 to perform complementary operations, complementary signals of the gate terminal 105 of the PMOS 101 and the gate terminal 106 of the PMOS 102 may be input. Therefore,
The output terminals of the differential circuit are connected to the terminals 105 and 106. FIG. 1 (b) shows this circuit. 108 is a differential circuit, 109 is an input terminal, and 110 and 111 are NPN transistors. The circuit operation is as follows. When “H” is input to input terminal 109, NPN
The transistor 110 is turned on, and the NPN transistor 111 is turned off. Then, the collector 106 of 110 is “L”, the collector 1 of 111
05 becomes “H”. Since 105 and 106 are respectively connected to the gates of the PMOS 101 and 102, the PMOS 101 is turned off and the PMOS 102 is turned on. Accordingly, the NPN transistor 103 is turned off, the 104 is turned on, and the output 107 becomes “L”. On the other hand, when "L" is input to the input 109, 110 is turned off, 111 is turned on, and 106 is turned on.
Is "H" and 105 is "L". Accordingly, 101 and 103 are turned on, 102 and 104 are turned off, and the output 107 becomes “H”. Thus, by connecting the operating circuit to the input stage,
Complementary operation becomes possible, and low power consumption is achieved because there is no DC current in the output stage. In addition, since a bipolar transistor having a totem-pole configuration is used in the output stage, there is no problem with the withstand voltage in the operation circuit portion, and the output impedance is small and the load driving force is high, so that the operation speed is high. Also, since the totem bipolar is driven by a PMOS, the circuit becomes very small.

As is clear from the above description, the circuit according to the present invention achieves a high breakdown voltage by using a PMOS and NPN bipolar configuration, and performs a complementary operation to reduce power consumption by using a differential circuit in the input stage. Have achieved.

Next, a second embodiment will be described with reference to FIG. In the second embodiment, the level conversion circuit 307 and the output circuit 303 in the power supply configuration shown in FIG. 4A are realized. Therefore, the output circuit according to the present embodiment outputs a signal of an internal circuit that operates between the low-potential power supply −5.2 V and GND as a TTL level signal between the high-potential power supply +5 V and GND. It is. Based on the above, the circuit configuration and circuit operation will be described below. The circuit is roughly composed of an input unit 507, a level shift unit 508, and an output unit 509. The power supply terminal 505 of the input section is connected to GND, and the power supply terminal 50
6 is connected to a low potential power supply (-5.2V). Input terminal 501
Is supplied with a signal from an internal circuit. Low level V _I L of the internal signal -5.2V, the high level V _I L is the amplitude signal near or to 0V. The input unit 507 converts the input signal into a signal having an amplitude of about 0.8 V. A converted signal having an amplitude of about 0.8 V appears at the output 109 of the input unit. in this way,
An internal circuit signal with an amplitude of about 5 V is
The reason for converting the amplitude to 0.8 V is to minimize the reverse bias applied between the base and the emitter of the NPN transistor 110. Between the power supply terminal 505 and the power supply terminal 506 of the input section, a pair of PMOS transistor and NMOS transistor constituting a CMOS inverter are provided, and the source of the NMOS transistor is connected between a resistor and a base-emitter connected in parallel with each other. Are connected to a power supply terminal 506 via an NPN transistor having a short circuit. The base-collector capacitance (capacitance) of the NPN transistor acts as a speed-up capacitor for improving the operation speed, and improves the output fall characteristic of the input unit 507. Next, the power supply terminal 504 of the level shift unit is connected to a high-potential power supply (+5 V), and the power supply terminal 506 is connected to a low-potential power supply (−5.2 V). In this level shift unit 508, the output 1 of the input unit
09 The signal is level-shifted and amplified, and a complementary signal is created. Potential lower than GND and amplitude is about
The 0.8 V 109 signal is converted to a positive potential amplitude having an amplitude of about 5 V at 105 and 106. The signals 105 and 106 are inverted from each other. Finally, the power supply terminal 504 of the output unit 509 is connected to a high-potential power supply (+5 V), and the power supply terminal 505 is connected to GND. The output unit 509 is a buffer circuit, and outputs the complementary signals of 105 and 106 in a single-ended manner. The output terminal 107 outputs a TTL level signal. The function of the PMOSs 503 and 507 will be described later. The circuit configuration is as described above, and the circuit operation will be described below. In the following description, the input signal “H” level “L” level, the “H” level “L” level of the output 109 of the input unit 507, and the “H” level “L” level of the outputs 105 and 106 of the level shift unit will be described. The “H” level and “L” level of the output signal have different values, but for simplicity, all “H” levels are “H” and all “L” levels are “L”.
It is written. When “H” enters the input terminal 501, 109 becomes “L”. Thus, 110 is off, 111 is on, 106 is "H" and 105 is "L". Since 101 is turned on, 103 is turned on, and 507 and 102 are turned off, so that 104 is turned off. Therefore, "H" is output to the output terminal 107. When “L” is input to the input terminal 501, 109 becomes “H”, 110 is turned on, and 111 is turned on.
Turns off. Therefore, 105 becomes "H" and 106 becomes "L". Ten
103 turns off because 1 turns off, 104 because 507,102 turns on
Is turned on, so that "L" is output to the output terminal 107. From this operation, the second embodiment constitutes a through circuit. It is easy to change the second embodiment to an inverter circuit. That is, 105 connects to the 110 collector and 106 connects to the 111 collector. In such a configuration, a signal inverted from the above-described circuit operation is output, so that the circuit eventually becomes an inverter circuit. When it is desired to configure a multi-input logic, the logic can be configured by the CMOS unit of the input unit 507. Further, the circuit of the second embodiment is characterized in that a tri-state circuit is formed by adding a PMOS 503. When "H" is input to the enable terminal 502, the PMOS 503 is turned off, and the circuit operates normally. On the other hand, when “L” is input to 502, the PMOS 503 is turned on,
Emitters 110 and 111 are clamped high and 110
And 111 are both turned off. Therefore, 105 and 106 both become "H", and all the PMOS transistors 101, 102 and 507 are turned off.
That is, 103 and 104 are both turned off, and the output becomes high impedance. Finally, the PMOS 507 is the base supply MOS 104. When 106 is “L”, the 507 continues to supply the base current to the 104, so that the 104 maintains the ON state.
Was but connexion, output 107 connected to the TTL circuit can be sucked sufficiently sink current I _OL from TTL, "L" is maintained in the output. Incidentally, as apparent from the power supply configuration, only a voltage of 0 V at the maximum is applied to the drain of the NMOS used for the input unit 507 of the second embodiment. Therefore,
Since only 5.2 V potential is generated between the drain and the substrate of the NMOS in the input section, it is obvious that there is no problem with the withstand voltage.

〔The invention's effect〕

According to the present invention, since the output buffer circuit section is composed of a PMOS and a bipolar transistor, a high breakdown voltage can be achieved, and the single channel MOS by the PMOS is operated in a complementary manner.
When the level shift section in the preceding stage of the output buffer section is constituted by an operation circuit to perform a complementary operation, there is an effect that almost no DC current flows and low power consumption can be achieved.

[Brief description of the drawings]

1 (a) and 1 (b) are circuit diagrams showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional example, and FIGS. 3 (a) and 3 (b).
FIG. 4 is a diagram showing a power supply configuration, FIGS. 4A and 4B are diagrams showing other power supply configurations, and FIG. 5 is a circuit diagram showing a second embodiment of the present invention. 101,102 …… PMOS, 103,104 …… NPN transistor, 105,1
06: PMOS gate terminal, 107: Output terminal.

Claims (4)

(57) [Claims] 1. A semiconductor integrated circuit device including a PMOS transistor, an NMOS transistor, and a bipolar transistor, each of which is formed on the same semiconductor substrate, wherein the semiconductor integrated circuit device has a first potential which is a potential of the semiconductor substrate;
A second potential higher than the first potential and a third potential higher than the second potential are applied, and a power supply line of the first potential is connected to the second potential.
A first PMOS transistor and the first PMOS
A circuit comprising a first NMOS transistor connected in series to the transistor and a first bipolar transistor having a base connected to the drain of the first PMOS transistor is provided, and a power supply line of the second potential and the A second PMOS transistor and the second PM
A branch constituted by a third PMOS transistor connected in series to the OS transistor and a branch constituted by a second bipolar transistor and a third bipolar transistor connected in series to the second bipolar transistor are connected in parallel. Connecting the drain of the second PMOS transistor to the base of the second bipolar transistor, connecting the drain of the third PMOS transistor to the base of the third bipolar transistor, and connecting the second bipolar transistor to the third bipolar transistor. A semiconductor integrated circuit device, wherein an output circuit is provided by providing an output signal extracting end portion in the section. 2. A semiconductor integrated circuit device including a PMOS transistor, an NMOS transistor, and a bipolar transistor, each of which is formed on the same semiconductor substrate, wherein the semiconductor integrated circuit device has a first potential which is a potential of the semiconductor substrate;
A second potential higher than the first potential and a third potential higher than the second potential are applied, and a first signal having a signal level in a range between the first potential and the second potential is applied to the first potential. An input unit for converting the signal into a small-amplitude signal having a signal level in the range of not less than the second potential and not more than the second potential; A level shift unit for amplifying and level shifting to output a complementary signal; and a PM between the power supply line of the second potential and the power supply line of the third potential.
A semiconductor integrated circuit device comprising: an OS transistor and a bipolar transistor; and a buffer unit that externally outputs an output signal of the level shift unit. 3. A pair of a first PMOS transistor and a first NMOS.
A transistor constitutes a CMOS inverter, an input terminal is connected to the input side of the CMOS inverter, and the first PMOS transistor is connected to a first potential power supply line via a resistor and a capacitor connected in parallel to the source of the first NMOS transistor. Are connected to the power line of the second potential via the first NPN transistor which is diode-connected, respectively.
The first PMOS transistor has a first
The output side of the CMOS inverter is connected to the base of a second NPN transistor constituting an emitter follower, the collector of the second NPN transistor is connected to the source of the first PMOS transistor, and the emitter is connected to the second impedance element. And an input unit connected to the power supply line of the first potential through the input terminal and having an emitter of the second NPN transistor as an output terminal; a third NPN transistor and a fourth NPN transistor as a differential pair; the third NPN transistor and the fourth NPN transistor Are connected to a power supply line of a third potential via third and fourth impedance elements, respectively, and the emitters of the third and fourth NPN transistors are connected to each other via a fifth NPN transistor and a fifth impedance element. Connected to a 1-potential power supply line and connected to the third and fourth NPN transistors. A level shift unit that outputs a complementary signal from the power supply, and a power supply line of the second potential and a power supply line of the third potential,
The second PMOS transistor and the third PMOS connected in series with each other
A branch constituted by a transistor and a sixth impedance element, and a seventh impedance element, a sixth NPN transistor, a first diode and a seventh N connected in series with each other;
And a PN transistor, and a drain of the second PMOS transistor is connected to the sixth NPN.
A drain of the third PMOS transistor is connected to a base of the seventh NPN transistor; an anode of the first diode is connected to an emitter of the sixth NPN transistor; a cathode is connected to a collector of the seventh NPN transistor; 2 Connect the anode of the diode
The collector of 7NPN transistor, the cathode is the third PMO
The source of the S transistor, the anode of the third diode is connected to the connection between the third PMOS transistor and the sixth impedance element, the cathode is connected to the gate of the second PMOS transistor, and the source of the fourth PMOS transistor is connected to the second PMOS transistor. The source of the transistor, the drain is connected to the base of the seventh NPN transistor, the gate is connected to the gate of the third PMOS transistor, the second PMOS transistor, the gate of the third PMOS transistor of the complementary signal output from the level shift unit Input end,
A semiconductor integrated circuit device comprising: an output unit having an output terminal connected to a junction between the first diode and the seventh NPN transistor. 4. The semiconductor integrated circuit device according to claim 3, wherein a source is connected to an emitter of the first NPN transistor of the input unit, and a drain is connected to an emitter of a third NPN transistor of the level shift unit. A semiconductor integrated circuit device, further comprising: a fifth PMOS transistor that controls on / off states of the third NPN transistor and the fourth NPN transistor by a control signal input to a gate.