JP2595771B2 - Frequency discriminator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency discriminator for color signal processing of both 8 mm and VHS VTRs.

2. Description of the Related Art Conventionally, a circuit configuration as shown in FIG. 3 is used as this kind of frequency discriminating apparatus. An output signal _VCO of an oscillator (VCO) whose oscillation frequency is controlled by a voltage is applied to a _VCO input terminal 40 and input to one input terminal of an AND gate 0. The output signal of the AND gate 0 is 1/4 frequency divider 100
Is applied to On the other hand, the horizontal sync signal (HD) from which the half H has been removed applied to the horizontal sync signal input terminal 70 is the first, second, and second signals.
It is input to the input terminal of the 1/8 frequency divider 200 having the third decoded output. The half H means that one cycle of the horizontal synchronizing signal is H, the vertical synchronizing pulse and the period before and after this pulse are
It is a 1 / 2H pulse in the 3H period. The first decoded output signal a is applied to the other input terminal of the AND gate 0. The second decode output signal d is applied to the reset input terminal of the counter 300 connected to the clock input terminal (CK), while the output signal of the 1/4 frequency divider 100 is applied to the first, 2 count value judgment circuit 400
And 600 are applied to the reset input terminal. The third decoded output signal c is logically ANDed with each output signal of each of the count value judgment circuits 400 and 600 by the logic gates 9, 10, 29, 30. After this, the signal determined by the first count value determination circuit 400 and the result determined by the second count value determination circuit 600 are compared with the high value applied to the 8 mm / VHS switching signal input terminal 60. The signal is applied to each input terminal of an output switching circuit 700 that switches by a signal of level (H) or low level (L), and the output terminal of the output switching circuit 700 is connected to the discrimination signal output terminals 80 and 90.

The operation of the frequency discriminator configured as described above
This will be described with reference to the time chart in FIG. Voltage controlled oscillator (VC
The output signal ( _VCO ) of O) is intermittently input to the 1/4 frequency divider 100 for a 4H period by a signal a obtained by dividing the horizontal synchronization signal (HD) by 1/8. The divided output becomes the clock input signal of the counter 300, and the counter 300 counts the signal of _VCO / 4. During the 4H period, the count result of the counter that counts the signal of _VCO / 4 determines the output by the count value judgment circuits 400 and 600 according to the inside and outside of the set (counter decode value) range,
The signal is sent to the output switching circuit 700 at the timing of the third decoded output signal c of the 1/8 frequency divider 200. Thereafter, the counter 300 and the count value determination circuits 400 and 600 are reset by the second decode output signal d of the 1/8 frequency divider. Thereafter, the same operation is repeated, and it is possible to discriminate the frequency of the _{VCO in} a 1 / 8H cycle. The setting range for frequency discrimination is as follows.

_H: a horizontal synchronizing signal relationship _VCO and _H indicate the frequency to Expression of (HD), _VCO
Since / 4 is intermittently counted for the 4H period, the center values of the setting ranges may be 320, 321, 378, and 375, respectively. Next, in the range (dead zone), the color signal processing system in the PAL system is set to ± 1 _H so that side lock does not occur. Therefore, “32
“320” and “322” are set as decode values for “1.” Similarly, ± 1 values are set for the other center values.

That is, in the case of the VHS PAL system, if the count value of the counter is 320 or less, a negative pulse is output to the discrimination signal output terminal 90 (LOCL) for 1H period, and if the count value is 322 or more, the pulse is output to the discrimination signal output terminal 80 (LOCH). Outputs positive polarity pulse for 1H period.

Problems to be Solved by the Invention In the frequency discriminating apparatus of the prior art described above, when used in a VTR color signal processing system, in order to switch between the 8 mm system and the VHS system, it is necessary to determine the count value of the counter. The circuit requires two types of circuits, one for VHS and one for 8mm, and a circuit for switching the output signal of the judgment result between VHS and 8mm is required, which has the disadvantage of increasing the number of elements in integration. .

Means for Solving the Problems In order to solve the above problems, only one type of the counter count value judgment circuit for the VHS is used, and the difference between the 8 mm system counter decode value and the VHS system counter decode value is newly decoded. By resetting the counter once, it becomes unnecessary to switch the output signal of the determination result between VHS and 8 mm.

Operation For example, in the case of the NTSC system of 8 mm, _VCO is 378 · _H , so if the counter is reset once with the difference of 378−320 = 58 from the VHS system, and the remaining 320 are counted, the count value judgment circuit will be VHS The system can be used as it is for the 8 mm system. That is, the VHS frequency discriminator can be added to the 8mm system by simply adding a circuit that detects the count difference from the 8mm system and resets the counter.
It is possible to obtain a frequency discriminator for both the HS system.

Embodiment An embodiment of a frequency discriminating apparatus according to the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram of the embodiment, and FIG. 2 is an operation waveform diagram thereof.

One input terminal of an AND gate 0 is connected to a _VCO input terminal 40 to which an output signal ( _VCO ) of a voltage controlled oscillator (VCO) whose oscillation frequency is controlled by a voltage is input. The output terminal of the AND gate 0 is connected to the input terminal of the 1/4 frequency divider 100, while the horizontal synchronizing signal (HD) from which half H has been removed.
Is applied to the input terminal of the 1/8 frequency divider 200 having the first, second, third, and fourth decoded outputs. The first decoded output signal a is applied to the other input terminal of the AND gate 0. The second decode output signal d is applied via a negative OR gate 58 to a reset input terminal of a counter 300 whose output terminal is connected to a clock input terminal, and 300 is applied to the reset input terminal of the count value determination circuit 400. The third decoded output signal c is ANDed with each output signal of the count value judgment circuit 400 by the logic gates 9 and 10 and output to the discrimination signal output terminals 80 and 90, respectively.
Further, the clock input terminal of the counter 300 is connected to the clock input terminal of the flip-flop circuit 54, so that the count values 56 and 52 of the counter 300 are decoded and reset.
The output signal of the clock reset pulse generation circuit 500 and the fourth decoded output signal e of the 1/8 frequency divider 200 are input to a NAND gate 55, and the output is input to the negative OR gate 58.
Is applied to the other input terminal of the NTSC system.
In the case of the AL system, the frequency discriminator is reset once at "54".

The operation of the frequency discriminator configured as described above will be described with reference to a time chart in the case of the 8 mm type NTSC shown in FIG. The output signal _VCO of the voltage controlled oscillator (VCO) is intermittently input to the 1/4 frequency divider 100 for a 4H period by the signal a obtained by dividing the horizontal synchronization signal (HD) by 1/8. The divided output becomes the clock input signal of the counter 300, and the _VCO / 4
Is counted. During the 4H period, the count result of the counter that has counted _VCO / 4 determines the output based on the inside and outside of the range set by the count value determination circuit 400 (decode value of the counter).
The signal is output to the discrimination signal output terminals 80 and 90 at the timing of the third decode output signal c of the frequency divider 200. In the case of the 8mm system, the VHS system is additionally counted by 378−320 = 58 in the NTS system and 375−321 = 54 in the PAL system, but the counter is reset once the counter counts the difference. The counter is operated again from "59" in the NTSC system and "55" in the PAL system, and "320" in the NTSC system and "321" in the PAL system.
Frequency discrimination centered on.

However, in order to decode the timing of the counter temporary reset, the first appearing NTSC system is limited to “56” and the PAL system is limited to “52”, so that the fourth decoded output signal e of the 1/8 frequency divider 200 is We accept only during the period.
Here, the decoding value is 58-2 = 56 in the NTSC system and 5 in the PAL system.
4-2 = 52, which is smaller by 2 because the width of the reset pulse is used twice for the input clock of the counter.

If the count value of the counter is 377 or less, a negative pulse is output to the discrimination signal output terminal 90 (LOCL) for one period, and if the count value is 379 or more, a positive pulse is output to the discrimination signal output terminal 80 (LOCH) for 1H.

Effect of the Invention According to the frequency discriminator of the present invention, the frequency discriminator for VTR color signal processing can handle both the 8 mm system and the VHS system by switching, so that the number of elements can be significantly reduced and the integration In this case, the degree of integration can be increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a frequency discriminator of the present invention, FIG. 2 is an operation waveform diagram of FIG. 1, FIG. 3 is a circuit diagram of a conventional frequency discriminator, and FIG. FIG. 4 is an operation waveform diagram of FIG. 3. 100: 1/4 frequency divider, 200: 1/8 frequency divider, 300: Counter, 400: Count value judgment circuit, 500: Reset pulse generation circuit, 40: _VCO input terminal, 50: … NTSC system, PAL system switching signal input terminal, 60… 8mm system, VHS system switching signal input terminal, 70 …… Horizontal synchronization signal input terminal, 80,9
0: Discrimination signal output terminal.

Claims (1)

(57) [Claims] An output signal input terminal of a voltage controlled oscillator whose oscillation frequency is controlled by a voltage is connected to one input terminal of a first coincidence gate, and the output terminal of the coincidence gate is connected to 1 /
Connected to the input terminal of the frequency divider, while the first, second, third, fourth
Input terminal of the 1/8 frequency divider having a decode output terminal of
A horizontal sync signal input terminal to which a horizontal sync signal from which half H has been removed is applied; the first decode output terminal is connected to the other input terminal of the first match gate; An output terminal of the divider is connected to a clock input terminal of the counter, and the second decode output terminal is connected to a reset input terminal of the counter.
Connected to one input terminal of the coincidence gate of the counter and a reset input terminal of the count value determination circuit of the counter, and the third decode output terminal is gated with each output signal of the count value determination circuit to generate a discrimination signal. An output terminal connected to an output terminal, a clock input terminal of the counter being connected to a clock input terminal constituting a reset pulse generation circuit for decoding a count value of the counter and generating a pulse, and an output terminal of the reset pulse generation circuit being connected to one end; 1/8 input terminal
The fourth decode output of the frequency divider is connected to the other input terminal of a third match gate to which the fourth decode output is connected, and the output terminal of the third match gate is connected to the other input terminal of the second match gate. The frequency discriminator is reset once in the middle of counting while the counter counts intermittently.