JP2589780Y2 - Waveform output device for IC tester - Google Patents

Description

[Detailed description of the invention]

[0001]

This invention selectively distributes and supplies three timing clocks to a set terminal and a reset terminal of a first set / reset flip-flop in accordance with a designated waveform mode and pattern data. The present invention relates to a waveform output device for an IC tester that outputs an output of a flip-flop through a driver and controls the driver to an enabled state or a disabled state with an output of a second set reset flip-flop.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional waveform output device. Timing clocks T1 to T5 are output from the timing generators 11 to 15, respectively. The timing clock T1 from the timing generator 11 is input to gates 16 and 17, the timing clock T2 from the timing generator 12 is input to gates 18 and 19, and the timing clock T3 from the timing generator 13 is input to gates 21 and 22, respectively. You. The outputs of the gates 16, 18, 21 are supplied to the set terminal S of the first set / reset flip-flop 24 through the OR circuit 23, and the outputs of the gates 17, 19, 22 are reset via the OR circuit 25. It is supplied to terminal R.

The output of the first flip-flop 24 is supplied to one pin terminal of an IC device under test 27 through a driver 26. Timing clocks T4 and T5 from timing generators 14 and 15 are applied to gates 28 and 29, respectively.
And each output of the gates 28 and 29 is connected to the second
A set terminal S of the set / reset flip-flop 31;
It is supplied to the reset terminal R. Second flip-flop 3
The output of 1 controls the driver 26 to an enabled state or a disabled state. Gates 16, 17,
Terminals 31, 32, 33, 34, 35, 3 are input as the other inputs of 18, 19, 21, 22, 28, 29, respectively.
Control signals are supplied from 6, 37, and 38.

When the SBC mode is designated as the waveform mode and pattern data D1, D2, D3... Are given, the operation is performed as shown in FIG. When the pattern data D1 is "0" in the first test cycle, the terminals 31, 3
Control signals “1”, “0”, “0”, “1”, “1”, “0” are supplied to 2, 33, 34, 35, and 36, respectively. The timing clocks T1, T2, and T3 are sequentially delayed in phase with respect to the beginning of the test cycle, that is, T1 is the most advanced and T3 is the most delayed. Therefore T
1 passes through the gate 16 and the first flip-flop 24 is set at T1, then T2 passes through the gate 19 and the first flip-flop 24 is reset at T2,
After that, T3 passes through the gate 21, the first flip-flop 24 is set at T3, and for the pattern data D1 = 0, the output of the first flip-flop 24 is as shown in the output of the FF 24 in the test cycle of D1 in FIG. become.

When the waveform mode is SBC and the pattern data is D
When 2 = “1”, as shown in the second test cycle of FIG. 4, the control signals inverted to those when D1 = “0” are applied to the terminals 31 to 36, respectively. Therefore, T1 passes through the gate 17 and the first flip-flop 24 is reset by T1, then T2 passes through the gate 18 and the first flip-flop 24 is set from T2, and then T3 passes through the gate 22. Thus, the first flip-flop 24 is reset by T3. Therefore, for D1 = 1, the output of the first flip-flop 24 is as shown in the output of the FF 24 in the test cycle of D2 in FIG.

As can be understood from the above, the SBC waveform is such that an RZ waveform is created for the pattern data at T2 and T3, and the RZ waveform is surrounded by data obtained by inverting the pattern data before and after the RZ waveform. Therefore, in addition to T2 and T3, T1 is used as a timing clock to generate inverted data before the RZ waveform created by T2 and T3.

Further, in order to use this test system for input / output pins, the driver 26 is enabled (operated) or disabled (inoperative: high impedance output) by the output of the second flip-flop 31. State). To enable the driver 26, the control signal at the terminal 37 is set to "1", the gate 28 is opened, and the second flip-flop 31 is set at T4. To disable the driver 26, the control signal at the terminal 38 is set to "1", the gate 29 is opened, and the second flip-flop 31 is reset at T5. The driver 26 is enabled over a plurality of test cycles as shown in test cycles D1 to D3 in FIG. 4, or enabled only between T4 and T5 in one test cycle as shown in test cycle D4. Or be done. The output of the driver 26 in the control state of FIG. 4 is as shown in the bottom row of FIG.

[0008]

[Problem to be solved by the invention] As described above, S
In order to generate the BC waveform, one timing clock T1 which is advanced in addition to the timing clocks T2 and T3 for generating the RZ waveform is required. In order to output the SBC waveform data to the IC device under test 27 for one test cycle, the timing clock T4, which has advanced from T2, and T3,
It requires a later timing clock T5. As described above, conventionally, five timing clocks T1 to T5 are used, and therefore, five timing generators 1 are used.
1 to 15 were prepared. Timing generators that operate at high speed and with high accuracy are expensive, costing, for example, 200,000 yen.
Therefore, providing each of the five timing generators for all test systems (each pin) is a large sum of money for the timing generators alone.

[0009]

According to the invention, an output waveform of a designated waveform mode and pattern data is generated to enable a driver, that is, as a timing clock for setting a second flip-flop. The three timing clocks having the most advanced phases among the three timing clocks are used, and the three timing clocks for disabling the driver, that is, for generating the output waveform as a timing clock for resetting the second flip-flop, are used. A fourth timing clock whose phase is behind any of the timing clocks is used.

[0010]

FIG. 1 shows an embodiment of the present invention, in which parts corresponding to those in FIG. 3 are denoted by the same reference numerals. In this embodiment, FIG.
The timing generator 14 inside is omitted, that is, the timing clock T4 is omitted, and the gate 28 controlled by the control signal of the terminal 37 has the timing clock T1 from the timing generator 11, that is, three gates for generating an output waveform. The one with the most advanced phase among the timing clocks T1 to T3 is given. The output side of the gate 28 and the second
A delay element 41 is inserted in series between the flip-flop 31 and the set terminal S as needed.

FIG. 2 shows an operation example in this case corresponding to the example of FIG. Since T1 to T3 are the same as those in FIG. 4, the output (FF24) of the first flip-flop 24 formed by the designated waveform mode and pattern data
Outputs) are the same, and the control signals for the terminals 31 to 36 therefor are also the same. A gate 2 for setting the driver 26 to an enabled state or a disabled state.
The control signals at terminals 37 and 38 for 8, 29 are also the same as in FIG. However, when the driver 26 is to be enabled, the gate 37 is opened, T1 passes through the gate 37, and the second flip-flop 31 is set. At this time, in this example, the delay element 41 sets T1 to T1.
Since the second flip-flop 31 is set with a delay of a, the first flip-flop 24 is set or reset by T1, as shown in FIG. 2, and the set or reset state is reliably applied to the driver 26. After that, that is, after the driver 26 sets up the set or reset state, the second flip-flop 31 is set. Therefore, the state of the waveform set by T1 is reliably obtained as the output of the driver 26.

The control for disabling the driver 26 uses T5 which is delayed from any of the timing clocks T1 to T3 for generating a waveform as in the conventional case, and is controlled as in the conventional case. As in the operation shown in FIG. 4, a desired driver output can be obtained. Even if the delay element 41 is omitted, the delay element 41 can be omitted if the rise of the output of the first flip-flop 31 is delayed with respect to the setup of the driver 26 for the waveform control by T1.

[0013]

As described above, according to the present invention, as the timing clock for enabling the driver, the one having the most advanced phase among the three timing clocks for generating the waveform is also used. In addition, one timing generator can be omitted for each test system as compared with the conventional one, and the timing generator is expensive, so that the overall cost of the IC tester can be considerably reduced.

[Brief description of the drawings]

FIG. 1 is a logic circuit diagram showing an embodiment of the present invention.

FIG. 2 is a time chart showing an operation example of the embodiment of FIG. 1;

FIG. 3 is a logic circuit diagram showing a conventional waveform output device.

FIG. 4 is a time chart showing an operation example of the device of FIG. 3;

Claims (1)

(57) [Scope of request for utility model registration] 1. A method for selectively distributing and supplying three timing clocks to a set terminal and a reset terminal of a first set / reset flip-flop according to a designated waveform mode and pattern data, and outputting an output of the first flip-flop. A waveform output device for an IC tester that outputs through a driver and controls the driver to an enable state or a disable state by an output of a second set reset flip-flop, wherein the three timing clocks are used as setting timing clocks of the second flip-flop. An IC having the most advanced phase among the three timing clocks, and a fourth timing clock having a phase later than any of the three timing clocks is used as the reset timing clock for the second flip-flop. Waveform output for tester Power device.