JP2586383B2 - Method of forming reflection and interference prevention resin film - Google Patents

Method of forming reflection and interference prevention resin film

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Publication number
JP2586383B2
JP2586383B2 JP5184558A JP18455893A JP2586383B2 JP 2586383 B2 JP2586383 B2 JP 2586383B2 JP 5184558 A JP5184558 A JP 5184558A JP 18455893 A JP18455893 A JP 18455893A JP 2586383 B2 JP2586383 B2 JP 2586383B2
Authority
JP
Japan
Prior art keywords
film
resin film
reflection
interference
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5184558A
Other languages
Japanese (ja)
Other versions
JPH0745498A (en
Inventor
治夫 岩崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP5184558A priority Critical patent/JP2586383B2/en
Publication of JPH0745498A publication Critical patent/JPH0745498A/en
Application granted granted Critical
Publication of JP2586383B2 publication Critical patent/JP2586383B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Application Of Or Painting With Fluid Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体装置を製造するリ
ソグラフィ−工程における反射および干渉防止樹脂膜の
形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a reflection and interference preventing resin film in a lithography process for manufacturing a semiconductor device.

【0002】[0002]

【従来の技術】樹脂を用いた反射防止膜は、膜中に発生
する光の干渉により半導体基板側からの反射光を低下さ
せることができる。また、樹脂を用いた干渉防止膜は、
膜中に発生する光の干渉により感光性樹脂膜(レジス
ト)内に発生する多重干渉効果を低下させることができ
る。このプロセスは例えば、トップアンチリフレクター
プロセスである。
2. Description of the Related Art An antireflection film using a resin can reduce reflected light from the semiconductor substrate side due to interference of light generated in the film. In addition, the anti-interference film using resin,
The multiple interference effect generated in the photosensitive resin film (resist) due to the interference of light generated in the film can be reduced. This process is, for example, a top anti-reflector process.

【0003】これらのプロセスが近年注目されて来たの
は、次に挙げる理由による。
[0003] These processes have been receiving attention in recent years for the following reasons.

【0004】(1):露光光がi線(365nm)から
エキシマレーザー光(248nm)となり、感光性樹脂
膜内の干渉の影響が大きくなり、感光性樹脂膜の膜厚の
変動に対するパターン寸法の変化が無視できないほど大
きくなってきた。
(1): Exposure light changes from i-ray (365 nm) to excimer laser light (248 nm), the influence of interference in the photosensitive resin film increases, and the pattern size changes with respect to the change in the thickness of the photosensitive resin film. The change has become so large that it cannot be ignored.

【0005】(2):パターンの微細化により、反射に
よるパターン形状のくずれが無視できなくなってきた。
[0005] (2): With the miniaturization of patterns, deformation of pattern shapes due to reflection cannot be ignored.

【0006】しかしながら反射防止膜および干渉防止膜
は、どちらの膜においてもその膜内で位相を180度ず
らさなくてはならないため、きびしい膜厚制御が必要と
なる。干渉防止膜を例にとると、膜厚は次の式(1)の
通りでなければならない。
However, the anti-reflection film and the anti-interference film both need to be shifted in phase by 180 degrees in each film, so that strict film thickness control is required. Taking the anti-interference film as an example, the film thickness must be as in the following equation (1).

【0007】 [0007]

【0008】例えば、i線リソグラフィ−においては、
λ=365nm:N=1.47(PVAの場合):n=
1とすると、d=62nmとなり、干渉防止膜の膜厚は
62nmで5%以内の膜厚変動となるように制御しなく
てはならない。すなわち、位相が180度となる条件か
ら膜厚が5%より大きくずれた場合、その効果は得られ
ない。
For example, in i-line lithography,
λ = 365 nm: N = 1.47 (for PVA): n =
If it is set to 1, d = 62 nm, and the film thickness of the interference prevention film must be controlled so that the film thickness changes within 5% at 62 nm. That is, if the film thickness deviates more than 5% from the condition that the phase becomes 180 degrees, the effect cannot be obtained.

【0009】現在、反射防止および干渉防止樹脂膜は、
感光性樹脂膜と同様な回転塗布法により成膜される。
At present, anti-reflection and anti-interference resin films are:
The film is formed by the same spin coating method as the photosensitive resin film.

【0010】図6は従来より用いられていた方法を示す
概略図であり、スピンチャック2上に搭載された半導体
ウエハ(半導体基板)1の中央部の上方のノズル4から
反射防止および干渉防止樹脂膜の材料液を滴下させ、ス
ピンチャックとともに半導体ウエハを回転させてこの材
料液を塗布している。
FIG. 6 is a schematic view showing a conventional method, in which an anti-reflection and anti-interference resin is applied from a nozzle 4 above a central portion of a semiconductor wafer (semiconductor substrate) 1 mounted on a spin chuck 2. The material liquid for the film is dropped, and the material liquid is applied by rotating the semiconductor wafer together with the spin chuck.

【0011】[0011]

【発明が解決しようとする課題】しかしながら上記方法
で塗布して形成した反射防止および干渉防止樹脂膜
は、、図7の膜厚分布図に示すように、半導体ウエハ全
面で膜厚変動幅が25%にも達し、上記した5%以内の
膜厚均一性を満足することはできない。
However, the anti-reflection and anti-interference resin film formed by applying the above method has a film thickness variation range of 25 over the entire surface of the semiconductor wafer as shown in the film thickness distribution diagram of FIG. %, And the film thickness uniformity of 5% or less cannot be satisfied.

【0012】一方、感光性樹脂膜を形成する塗布におい
てはその膜厚をなるべく均一にするために種々の試みが
なされている。しかしながら感光性樹脂膜と本発明が対
象としている反射防止および干渉防止樹脂膜とでは、膜
の厚さやその粘度また要求される均一性の程度が全く異
なるから、感光性樹脂膜を形成する塗布技術は適用でき
ない。すなわち、感光性樹脂膜の標準的膜厚は700〜
2000nmであるが、反射防止および干渉防止樹脂膜
の標準的膜厚は60〜100nmである。またスピンコ
ートで塗布する感光性樹脂膜材の粘度と反射防止および
干渉防止樹脂膜材の粘度とは極端に異なり、反射防止お
よび干渉防止樹脂膜に要求される成膜の精度、均一性は
非常に厳しくなる。すなわち上記したように反射防止お
よび干渉防止樹脂膜は、膜内を通過する露光光の位相を
180度遅らせる必要があるから、ウエハ面内での膜厚
変動を5%以内にしなくてはならない。
On the other hand, in coating for forming a photosensitive resin film, various attempts have been made to make the film thickness as uniform as possible. However, since the photosensitive resin film and the anti-reflection and anti-interference resin film targeted by the present invention have completely different film thicknesses, their viscosities and the required degree of uniformity, a coating technique for forming the photosensitive resin film is used. Is not applicable. That is, the standard thickness of the photosensitive resin film is 700 to
Although it is 2000 nm, the standard thickness of the anti-reflection and anti-interference resin film is 60 to 100 nm. Also, the viscosity of the photosensitive resin film material applied by spin coating and the viscosity of the anti-reflection and anti-interference resin film material are extremely different, and the precision and uniformity of the film formation required for the anti-reflection and anti-interference resin film are extremely high. Stricter. That is, as described above, in the anti-reflection and anti-interference resin film, it is necessary to delay the phase of the exposure light passing through the film by 180 degrees, so that the film thickness variation in the wafer surface must be kept within 5%.

【0013】[0013]

【課題を解決するための手段】本発明の特徴は、半導体
装置を製造するリソグラフィー工程において、半導体基
板と感光性樹脂膜との間あるいは感光性樹脂膜上に成膜
して露光光の反射および干渉を防止する反射および干渉
防止樹脂膜の形成方法において、半導体ウエハ上にノズ
ルから前記膜を構成する材料液を滴下し前記半導体ウエ
ハを回転させて前記材料液を塗布するに際し、前記半導
体ウエハの中心部の上方に1個のノズルを配置し、前記
半導体ウエハの周辺部の上方に複数個のノズルを配置
し、前記中心部の上方の1個のノズルから前記半導体ウ
エハの中心部に滴下する前記材料液の濃度もしくは粘度
より前記周辺部の上方の複数個のそれぞれのノズルから
前記半導体ウエハの周辺部に滴下する前記材料液の濃度
もしくは粘度が大である反射および干渉防止樹脂膜の形
成方法にある。
A feature of the present invention is that, in a lithography process for manufacturing a semiconductor device, a film is formed between a semiconductor substrate and a photosensitive resin film or on a photosensitive resin film so as to reflect exposure light and reduce exposure light. in the method for forming a reflection and anti-interference resin film to prevent interference upon applying the material liquid by dropping a material solution for forming the film from a nozzle onto a semiconductor wafer by rotating the semiconductor wafer, the semiconductor
One nozzle is arranged above the center of the body wafer,
Multiple nozzles located above the periphery of the semiconductor wafer
And the semiconductor wafer is received from one nozzle above the central portion.
The concentration or viscosity of the material liquid dropped at the center of Eha
From a plurality of respective nozzles above the peripheral portion
The concentration of the material liquid dropped on the periphery of the semiconductor wafer
Alternatively, there is a method for forming a reflection and interference prevention resin film having a high viscosity .

【0014】[0014]

【実施例】以下図面を参照して本発明を説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

【0015】図1は本発明の実施例における反射および
干渉防止樹脂膜の形成方法においてその塗布方法を示す
図であり、スピンチャック2上に直径6インチの半導体
ウエハ1を搭載し、その中心部3a’の上方にノズル3
aを配設し、4箇所の周辺部3b’,3c’,3d’,
3e’のそれぞれの上方にノズル3b,3c,3d,3
eを配設する(尚、ノズル3d,3eは図示省略)。ま
た、中心部のノズル3aから周辺部のノズル3b,3
c,3d,3eはそれぞれ3.5cm離間している。
FIG. 1 is a view showing a coating method in a method of forming a reflection and interference prevention resin film according to an embodiment of the present invention. A semiconductor wafer 1 having a diameter of 6 inches is mounted on a spin chuck 2 and a central portion thereof. Nozzle 3 above 3a '
a, and four peripheral portions 3b ', 3c', 3d ',
Nozzles 3b, 3c, 3d, 3 above each of 3e '
e (nozzles 3d and 3e are not shown). In addition, the nozzles 3b, 3 from the central part
c, 3d, 3e are each separated by 3.5 cm.

【0016】反射および干渉防止樹脂膜をPVA(ポリ
ビニ−ルアルコール)を用いる場合、濃度1.5%のP
VA液(水を溶媒とし、それに1.5wt%のPVAを
溶質として混合した溶液)を材料液Aとし、濃度2.0
%のPVA液(水を溶媒とし、それに2.0wt%のP
VAを溶質として混合した溶液)を材料液Bとして用意
する。この材料液Aの粘度は約1cpであり、材料液B
の粘度はこれより大である。
When PVA (polyvinyl alcohol) is used for the reflection and interference prevention resin film, a 1.5% P
A VA solution (a solution in which water was used as a solvent and 1.5 wt% of PVA was used as a solute) was used as a material solution A, and a concentration of 2.0 was used.
% PVA solution (water is used as a solvent and 2.0 wt% P
A solution in which VA is mixed as a solute) is prepared as a material liquid B. The viscosity of the material liquid A is about 1 cp and the material liquid B
Are greater than this.

【0017】この材料液Aをノズル3aから半導体ウエ
ハの中心部3a’に滴下し、材料液Aより濃度および粘
度が大きい材料液Bをノズル3b,3c,3d,3eか
ら半導体ウエハの周辺部3b’,3c’,3d’,3
e’にそれぞれ滴下する。滴下後、半導体ウエハを50
0rpmの回転数で10秒間回転させ引き続き2000
rpmの回転数で20秒間回転させて塗布を完了する。
The material liquid A is dropped from the nozzle 3a onto the central portion 3a 'of the semiconductor wafer, and the material liquid B having a higher concentration and viscosity than the material liquid A is supplied from the nozzles 3b, 3c, 3d and 3e to the peripheral portion 3b of the semiconductor wafer. ', 3c', 3d ', 3
Drop each on e ′. After dropping, the semiconductor wafer is
Rotate at 0 rpm for 10 seconds and continue 2,000
Spin at 20 rpm for 20 seconds to complete the application.

【0018】このような塗布が行われた半導体ウエハを
100℃、60秒間ホットプレートでベークすることに
より、図2に示すように半導体ウエハの中心部から周辺
部にかけて膜厚変動が5%以内の膜厚均一性の良好な反
射および干渉防止樹脂膜が得られた。
By baking the coated semiconductor wafer on a hot plate at 100 ° C. for 60 seconds, the variation in film thickness from the center to the periphery of the semiconductor wafer is within 5% as shown in FIG. A reflection and interference prevention resin film having good film thickness uniformity was obtained.

【0019】図3は中央部に滴下するノズル3aからの
材料液の濃度を1.5%に固定し、周辺部に滴下するノ
ズル3b,3c,3d,3eからの材料液の濃度を変更
した場合の膜厚変動を示すグラフである。尚、他の条件
は上記実施例と同じである。周辺部が中央部と同じ濃度
1.5%の場合、図7の従来技術と同様に膜厚変動は2
5%となる。周辺部の濃度1.75%のとき膜厚変動は
約10%と減小され、さらに周辺部の濃度が実施例の
2.0%のときに膜厚変動は最小となり、この濃度2.
0%を中心に膜厚変動が5%以下となる濃度範囲が存在
する。そして逆に濃度をさらに2.25%とすると膜厚
変動は10%となった。
In FIG. 3, the concentration of the material liquid from the nozzle 3a dropped to the center is fixed at 1.5%, and the concentration of the material liquid from the nozzles 3b, 3c, 3d, 3e dropped to the periphery is changed. 6 is a graph showing a variation in film thickness in the case. The other conditions are the same as in the above embodiment. When the peripheral portion has the same concentration of 1.5% as the central portion, the film thickness variation is 2 as in the prior art of FIG.
5%. When the density at the peripheral portion is 1.75%, the variation in film thickness is reduced to about 10%. When the density at the peripheral portion is 2.0% in the embodiment, the variation in film thickness is minimized.
There is a concentration range where the film thickness variation is 5% or less centering on 0%. Conversely, when the concentration was further increased to 2.25%, the film thickness variation became 10%.

【0020】図4は本発明を干渉防止膜の形成に用いた
例を工程順に示した断面図である。所定の不純物領域を
形成し必要な下層配線構造等形成した半導体基板11上
の全面にアルミ膜12を堆積した半導体ウエハ1をフォ
トリソグラフィ−工程により、このアルミ膜12をパタ
ーニングしてアルミ配線を形成する場合、アルミ膜12
上に感光性樹脂膜(レジスト)6をスピンコート法で塗
布形成し、その上に図1で説明した本発明の方法でPV
A溶液7’(材料液Aおよび材料液B)を塗布し
(A)、ベークすることにより膜厚均一性の良いPVA
膜7を形成する(B)。次に、PVA膜7を通して感光
性樹脂膜6の選択領域に露光光8が照射する(C)が、
この際にPVA膜は干渉防止樹脂膜7として作用する。
そして現像により感光性樹脂膜6からレジストマスク1
6が形成され、PVA膜7はこの現像の際に除去される
(D)。その後、レジストマスク16をマスクにしてア
ルミ膜12をエッチングしてアルミ配線をパターニング
形成する。
FIG. 4 is a sectional view showing an example in which the present invention is used for forming an interference prevention film in the order of steps. The aluminum film 12 is patterned by a photolithography process on a semiconductor wafer 1 having an aluminum film 12 deposited on the entire surface of a semiconductor substrate 11 on which a predetermined impurity region is formed and a necessary lower layer wiring structure is formed, thereby forming aluminum wiring. If so, the aluminum film 12
A photosensitive resin film (resist) 6 is formed thereon by spin coating, and PVD is formed thereon by the method of the present invention described with reference to FIG.
A solution 7 '(material solution A and material solution B) is applied (A) and baked to obtain PVA with good film thickness uniformity
A film 7 is formed (B). Next, the exposure light 8 is applied to the selected area of the photosensitive resin film 6 through the PVA film 7 (C).
At this time, the PVA film functions as the interference prevention resin film 7.
Then, the resist mask 1 is removed from the photosensitive resin film 6 by development.
6 is formed, and the PVA film 7 is removed during this development (D). Thereafter, the aluminum film 12 is etched using the resist mask 16 as a mask to pattern and form an aluminum wiring.

【0021】図5は本発明を反射防止膜の形成に用いた
例を工程順に示した断面図である。所定の不純物領域を
形成し必要な下層配線構造等形成した半導体基板11上
の全面にアルミ膜12を堆積した半導体ウエハ1をフォ
トリソグラフィ−工程により、このアルミ膜12をパタ
ーニングしてアルミ配線を形成する場合、アルミ膜12
上にに図1で説明した本発明の方法でPVA溶液7’
(材料液Aおよび材料液B)を塗布し(A)、ベークす
ることにより膜厚均一性の良いPVA膜7を形成する
(B)。次にPVA膜7上に感光性樹脂膜(レジスト)
6をスピンコート法で塗布形成し、感光性樹脂膜6の選
択領域に露光光8が照射する(C)が、この際にPVA
膜は反射防止樹脂膜7として作用する。そして現像によ
り感光性樹脂膜6からレジストマスク16が形成され、
レジストマスク16下以外の露出するPVA膜7の部分
はこの現像の際に除去される(D)。その後、レジスト
マスク16をマスクにしてアルミ膜12をエッチングし
てアルミ配線をパターニング形成する。
FIG. 5 is a sectional view showing an example in which the present invention is used for forming an antireflection film in the order of steps. The aluminum film 12 is patterned by a photolithography process on a semiconductor wafer 1 having an aluminum film 12 deposited on the entire surface of a semiconductor substrate 11 on which a predetermined impurity region is formed and a necessary lower layer wiring structure is formed, thereby forming aluminum wiring. If so, the aluminum film 12
In the method of the present invention described above with reference to FIG.
(Material liquid A and material liquid B) are applied (A) and baked to form a PVA film 7 with good film thickness uniformity (B). Next, a photosensitive resin film (resist) is formed on the PVA film 7.
6 is formed by spin coating, and the selected area of the photosensitive resin film 6 is irradiated with exposure light 8 (C).
The film functions as an anti-reflection resin film 7. Then, a resist mask 16 is formed from the photosensitive resin film 6 by development,
Exposed portions of the PVA film 7 other than under the resist mask 16 are removed during this development (D). Thereafter, the aluminum film 12 is etched using the resist mask 16 as a mask to pattern and form an aluminum wiring.

【0022】[0022]

【発明の効果】以上説明したように本発明によれば、半
導体ウエハの中央部と周辺部とに互いに異なる濃度もし
くは粘度の反射および干渉防止樹脂膜の材料液を滴下し
て塗布することで、膜厚変動5%以内の反射および干渉
防止樹脂膜を成膜することができる。
As described above, according to the present invention, a material liquid for a reflection and interference prevention resin film having different concentrations or viscosities is dropped and applied to a central portion and a peripheral portion of a semiconductor wafer. A reflection and interference prevention resin film having a film thickness variation of 5% or less can be formed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例を説明する図であり、(A)は
断面図、(B)は半導体ウエハの平面図である。
FIGS. 1A and 1B are diagrams illustrating an embodiment of the present invention, wherein FIG. 1A is a cross-sectional view and FIG. 1B is a plan view of a semiconductor wafer.

【図2】本発明の実施例の方法により得られた反射およ
び干渉防止樹脂膜の膜厚変動を示す図である。
FIG. 2 is a diagram showing a variation in the thickness of a reflection and interference prevention resin film obtained by a method according to an example of the present invention.

【図3】半導体ウエハの中央部に滴下する材料液の濃度
を一定とし、周辺部に滴下する材料液の濃度を変化させ
た場合の反射および干渉防止樹脂膜の膜厚変動の変化を
示す図である。
FIG. 3 is a diagram showing a change in the thickness variation of the reflection and interference prevention resin film when the concentration of the material liquid dropped on the central portion of the semiconductor wafer is constant and the concentration of the material liquid dropped on the peripheral portion is changed. It is.

【図4】本発明の実施例によるPVA膜を干渉防止樹脂
膜として用いた例を示す断面図である。
FIG. 4 is a cross-sectional view showing an example in which a PVA film according to an embodiment of the present invention is used as an interference prevention resin film.

【図5】本発明の実施例によるPVA膜を反射防止樹脂
膜として用いた例を示す断面図である。
FIG. 5 is a sectional view showing an example in which a PVA film according to an embodiment of the present invention is used as an anti-reflection resin film.

【図6】従来技術を説明する図である。FIG. 6 is a diagram illustrating a conventional technique.

【図7】従来技術による反射および干渉防止樹脂膜の膜
厚変動を示す図である。
FIG. 7 is a diagram showing a variation in thickness of a reflection and interference prevention resin film according to a conventional technique.

【符号の説明】[Explanation of symbols]

1 半導体ウエハ 2 スピンチャック 3,4 滴下用ノズル 6 感光性樹脂膜(レジスト) 7 PVA膜 7’ PVA溶液 8 露光光 11 半導体基板 12 アルミ膜 16 レジストマスク DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Spin chuck 3, 4 Dropping nozzle 6 Photosensitive resin film (resist) 7 PVA film 7 'PVA solution 8 Exposure light 11 Semiconductor substrate 12 Aluminum film 16 Resist mask

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/30 564D ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 6 Identification code Agency reference number FI Technical display location H01L 21/30 564D

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体装置を製造するリソグラフィー工
程において、半導体基板と感光性樹脂膜との間あるいは
感光性樹脂膜上に成膜して露光光の反射および干渉を防
止する反射および干渉防止樹脂膜の形成方法において、 半導体ウエハ上にノズルから前記膜を構成する材料液を
滴下し前記半導体ウエハを回転させて前記材料液を塗布
するに際し、前記半導体ウエハの中心部の上方に1個のノズルを配置
し、前記半導体ウエハの周辺部の上方に複数個のノズル
を配置し、前記中心部の上方の1個のノズルから前記半
導体ウエハの中心部に滴下する前記材料液の濃度もしく
は粘度より前記周辺部の上方の複数個のそれぞれのノズ
ルから前記半導体ウエハの周辺部に滴下する前記材料液
の濃度もしくは粘度が大である ことを特徴とする反射お
よび干渉防止樹脂膜の形成方法。
In a lithography process for manufacturing a semiconductor device, a reflection and interference prevention resin film formed between a semiconductor substrate and a photosensitive resin film or on a photosensitive resin film to prevent reflection and interference of exposure light. In the method of forming, a material liquid constituting the film is dropped from a nozzle onto a semiconductor wafer, and when the material liquid is applied by rotating the semiconductor wafer, one nozzle is provided above a central portion of the semiconductor wafer. Arrangement
And a plurality of nozzles above a peripheral portion of the semiconductor wafer.
From one nozzle above the center and the half
The concentration or the concentration of the material liquid dropped onto the center of the conductive wafer
Is the number of each of the nozzles above the periphery
The material liquid dropped onto the periphery of the semiconductor wafer from the wafer
A method of forming a reflection and anti-interference resin film, characterized by having a high concentration or viscosity .
JP5184558A 1993-07-27 1993-07-27 Method of forming reflection and interference prevention resin film Expired - Fee Related JP2586383B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5184558A JP2586383B2 (en) 1993-07-27 1993-07-27 Method of forming reflection and interference prevention resin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5184558A JP2586383B2 (en) 1993-07-27 1993-07-27 Method of forming reflection and interference prevention resin film

Publications (2)

Publication Number Publication Date
JPH0745498A JPH0745498A (en) 1995-02-14
JP2586383B2 true JP2586383B2 (en) 1997-02-26

Family

ID=16155311

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5184558A Expired - Fee Related JP2586383B2 (en) 1993-07-27 1993-07-27 Method of forming reflection and interference prevention resin film

Country Status (1)

Country Link
JP (1) JP2586383B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3844177B2 (en) 1998-07-31 2006-11-08 株式会社リコー Paper discharge device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61238050A (en) * 1985-04-15 1986-10-23 Nec Corp Coating method
US5126289A (en) * 1990-07-20 1992-06-30 At&T Bell Laboratories Semiconductor lithography methods using an arc of organic material

Also Published As

Publication number Publication date
JPH0745498A (en) 1995-02-14

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