JP2586042B2 - Dynamic semiconductor memory device - Google Patents

Description

The present invention relates to a memory device such as a dynamic RAM.

B. SUMMARY OF THE INVENTION In the present invention, in a memory device in which memory cells are arranged at intersections of word lines and bit lines, a first sense amplifier and a second sense amplifier are arranged for each pair of bit lines. Switching means for dividing each bit line is provided, and the first means is controlled by the switching means.
By amplifying one signal of a pair of memory cells selected using a sense amplifier and amplifying the other signal of the memory cell using a second sense amplifier, high integration can be easily realized and differential Noise and the like can be reduced.

C. Prior Art In a memory device such as a DRAM, for example, a memory device having a so-called open bit line configuration and a memory device having a so-called folded bit line configuration are known depending on a bit line layout.

First, in a memory device having an open bit line configuration, cell arrays are arranged symmetrically in the bit line direction with a sense amplifier used for reading and rewriting interposed therebetween, and each memory cell of the cell array is It is arranged at the intersection of a word line and each bit line. A pair of bit lines connected to one sense amplifier exist on a straight line,
When one of the bit lines is a bit line for reading data, as viewed from the sense amplifier sandwiched therebetween,
The other bit line is used as a reference for the operation of the sense amplifier.

A memory device having a folded bit line configuration is also referred to as a memory device having a folded bit line configuration. A memory device having a folded bit line configuration includes a pair of adjacent bit lines arranged at an end thereof.
Connected to one sense amplifier, and when one bit line is used for reading data, the other bit line is used for reference. Each bit line has a memory cell at an intersection with every other word line, and a memory selected by one of the memory cells connected to a pair of adjacent bit lines. There is one cell.
That is, when one certain word line is selected, the access transistors of the memory cells connected to every other bit line are turned on in the entire cell array.

D. Problems to be Solved by the Invention As a conventional memory device, a memory device having an open bit line configuration and a memory device having a folded bit line configuration as described above are well known. Problems.

First, in a memory device having an open bit line configuration, memory cells are always arranged at intersections of each bit line and each word line, and the memory cells are arranged at high density because there is no waste in the arrangement. It is possible. However,
In a memory device having an open bit line configuration, bit lines arranged symmetrically to the left and right across a sense amplifier are operated as a pair. For this reason, for example, noise may be added only to the bit line related to one memory cell, and S /
This leads to the problem of deterioration of N. Furthermore, when the integration (advance) progresses and the interval (pitch) between bit lines is narrowed, the layout of sense amplifiers that need to be arranged at the same interval as the bit lines becomes difficult.

On the other hand, in a memory device having a folded bit line configuration, one of a pair of adjacent bit lines is used for reading data, and the other is used for reference. As a result, the bit line itself behaves in a similar manner, thereby reducing noise and effectively preventing malfunctions and the like. But,
Since a pair of adjacent bit lines is used for the operation of the sense amplifier, the number of word lines for the memory cell is doubled, which limits the high integration.

In view of the above problems, an object of the present invention is to provide a memory device that realizes high integration and also reduces noise and the like.

E. Means for Solving the Problems The present invention is directed to first and second switching means which are arranged in parallel, and are electrically connected and disconnected independently by first and second control signals. , A word line disposed orthogonal to the first and second complementary bit line pairs, and one and the other of the first complementary bit line pair A first memory cell array in which memory cells each including a capacitive element and an address selection gate are arranged in a grid at each intersection of a bit line and a word line, and one and the other bits of the second complementary bit line pair. At each intersection of a line and a word line, a second memory cell array in which memory cells each including a capacitor and an address selection gate are arranged in a grid pattern is electrically connected to each other independently by third and fourth control signals. A first sense amplifier in which a complementary input signal terminal pair is connected to the first complementary bit line pair via third and fourth switching means for controlling release and release, and fifth and sixth switching means. The second pair of complementary input signal terminals connected to the second pair of complementary bit lines via fifth and sixth switching means, each of which is electrically connected and disconnected independently by a control signal. The above problem is solved by a dynamic semiconductor memory device having a sense amplifier.

F. Function In order to achieve high integration, the above-described open bit line configuration is advantageous, but the arrangement of sense amplifiers, differential noise, and the like pose problems. Therefore, first, the memory cells are arranged in an open bit line configuration in which memory cells are arranged at intersections of bit lines and word lines, and two memory cells connected to the same word line of a pair of bit lines adjacent in the word line direction. In order to use other memory cells for reference in the cell, the first sense amplifier and the second sense amplifier are operated while dividing bit lines by switching means. That is, if the bit line is divided, the signal potential difference can be increased in accordance with the divided length. The signal potential difference differs by dividing the pair of bit lines to have different lengths by using the switching means. Will come. Then, even if adjacent memory cells in the word line direction are simultaneously conductive with the bit line, the sensing operation of the memory cell on the data side can be performed by, for example, the second sense amplifier using the difference in the signal potential difference, At the same time, the sensing operation of the memory cell on the reference side can be performed by the first sense amplifier. And at this time,
Since what is sensed is the potential between a pair of adjacent bit lines, differential noise is effectively reduced as in the memory device having the folded bit line configuration. Further, the sense amplifier is connected to a pair of bit lines adjacent in the word line direction. Even when the pitch of the bit lines is narrowed, the sense amplifier is compared with a memory device having a conventional open bit line configuration. Will have room for the layout.

G. Embodiment A preferred embodiment of the present invention will be described with reference to the drawings.

The memory device according to the present embodiment has two cell arrays, and at the same time, the memory cells are arranged at the intersections of the word lines and the bit lines, and at the same time, the differential noise and the like are reduced, thereby increasing the integration of the memory cells. Is realized.

First, as shown in FIG. 1, the configuration of the pair of bit lines is such that the DBs are connected via column select transistors 13 and 14, respectively.
And a pair of first and second bit lines BL1 and BL2 connected to the first and second bit lines BL1 and BL2.
1 and BL2 respectively. These first bit lines B
Between the L1 and the second bit line BL2, a first sense amplifier 3 is provided adjacent to the cell array 1, and a second sense amplifier 4 is provided adjacent to the cell array 2. The memory device of the present embodiment is further provided with switching means for dividing and using the bit line, and the switching means is provided with a switching transistor ST1.
~ ST6.

The cell arrays 1 and 2 are formed by arranging a plurality of memory cells. Although not particularly shown, memory cells are arranged at intersections of each word line and each bit line, which facilitates high integration. This is a cell array having a so-called open bit line configuration. That is, the word line provided with the memory cell between the first bit line BL1 and the second bit line BL2
However, the memory cells are provided, and as shown in the cell array 2, only one pair of the access transistors 5 and 6 of the memory cells adjacent to each other in the word line direction has a common word line WL. Therefore, when the signal ΦWL supplied to the word line WL becomes, for example, “H” level, both the access transistors 5 and 6 are turned on (conducting state), and are stored in the capacitors 7 and 8 respectively. The charge that was stored in each bit line BL1, BL2
However, by the operation of the switching means, which will be described later, the data is separately amplified for reading and for reference.
Note that the structure of the memory cell is not limited.

The first sense amplifier 3 and the second sense amplifier 4
Are circuits for sensing and restoring the data of the memory cells, respectively. The first sense amplifier 3
Each of the flip-flop circuits includes PMOS transistors 21 and 22 and NMOS transistors 23 and 24. The PMOS transistors 21 and 22 are driven by a signal φP, and the NMOS transistors 23 and 24 are driven by a signal φN. Similarly, the second sense amplifier 4 includes PMOS transistors 25 and 26 constituting flip-flop circuits, respectively.
And NMOS transistors 27 and 28, and the PMO
The S transistors 25 and 26 are driven by the signal ΦP,
The OS transistors 27 and 28 are driven by the signal ΦN. The first sense amplifier 3 is adjacent to the cell array 1 in the bit line direction, and is disposed between the cell array 1 and an equalizing circuit constituted by MOS transistors 11, 12, 11 to which the equalizing signal ΦEQ is supplied. Have been. The second sense amplifier 4 is disposed adjacent to the cell array 2 and between the cell array 2 and the column selection transistors 13 and 14 to which the column selection signal ΦY from the column decoder 15 is supplied. Each of these sense amplifiers 3, 4
One of them is used for amplification of a memory cell for reading, and the other is used for amplification of a memory cell for reference. For example, when the sense amplifier for reading is a second sense amplifier as in an operation example described later, the first sense amplifier 3 always amplifies the reference memory cell.

The switching means is a switching transistor
ST1 to ST6, the first and second bit lines BL1, BL
2 has a function of dividing the signal potential difference. These switching transistors ST1 to ST6
Has a function of performing the operation of dividing the bit line also at the time of the sensing operation and the restore operation of the sense amplifiers 3 and 4 to reduce the capacitance and speed up the voltage transition. Here, the switching transistor ST1 is connected to the first bit line B
L1 is divided between the cell array 1 and the cell array 2, and the capacity of the bit line BL1 is equally divided. This switching transistor ST1 outputs the signal ΦAT1
Is controlled by The switching transistor ST2 is
The second bit line BL2 is divided between the cell array 1 and the cell array 2. Similarly, the bit line BL2 is equally divided in capacity, and is arranged at a position facing the switching transistor ST1. The switching transistor ST2 is controlled by a signal ΦT2. The switching transistor ST3 is provided on the first bit line BL1 between the cell array 2 and the second sense amplifier 4, and receives a signal ΦT3
Controls the interruption. Switching transistor ST
4 is provided on the second bit line BL2 between the cell array 2 and the second sense amplifier 4, and the intermittent is controlled by the signal Φ4. The switching transistor ST5 is provided on the first bit line BL1 between the cell array 1 and the first sense amplifier 3, and the switching is controlled by a signal ΦT5. Finally, the switching transistor ST6 is connected to the second bit line between the cell array 1 and the first sense amplifier 3.
It is arranged on BL2, and the interruption is controlled by the signal ΦT6.

Next, an example of the operation of the memory device of the present embodiment having the above basic configuration will be described with reference to FIG. This operation example is an operation example when data of a memory cell connected to the second bit line BL2 of the cell array 2 is read.

First, the equalizing signal ΦEQ is initially set to the “H” level (high level), and the MOS transistors 11, 12, 11 are turned on, and the first bit line BL1 and the second bit line BL2 are turned on.
Is set to, for example, one half of the power supply voltage Vcc. At this time, the switching transistors ST1 to ST6
Are all in the ON state, and the selection signal ΦWL of the word line WL is also at the “L” level (low level).

Then, equalizing signal ΦEQ at time t ₀ is changed to "L" level from "H" level, the MOS transistors 11,12,11
Is turned off. Then the signal at time t ₁ ΦT1 and ΦT2
Changes from the “H” level to the “L” level, and the switching transistor ST1 and the switching transistor ST2
Changes from the on state to the off state. Then, both the first bit line BL1 and the second bit line BL2 have their capacitances substantially halved, and the cell array 1 and the cell array 2 are electrically disconnected.

Then, the signal ΦT1 at time t ₂ from the "L" level is changed to "H" level, the switch ring transistor ST1 is changed from the off state to the on state. Then, the first bit line BL1 conducts between the cell array 1 and the cell array 2. Therefore, in this state, the bit line capacities of the two bit lines BL1 and BL2 related to the portion connected to the cell array 2 are different. At the same time, the word line is set to the “H” level by the signal ΦWL, and a selecting operation corresponding to a predetermined address is performed. Here, for example, assuming that the illustrated word line WL is selected, the access transistors 5 and 6 of the two memory cells are both turned on, and the charge stored in the capacitor 7 is transferred to the first transistor via the access transistor 5. The charges appearing on the bit line BL1 and similarly stored on the capacitor 8 appear on the second bit line BL2 via the access transistor 6. All other word lines (not shown) connected to the cell array 2 are at "L" level (non-selected state).

Then, a signal potential difference appears on each of the bit lines BL1 and BL2. In the memory device of the present embodiment, in particular, since the bit line capacities of the two bit lines BL1 and BL2 connected to the cell array 2 are different, A signal potential difference corresponding to the bit line capacitance appears on each bit line BL1, BL2. That is, the first bit line BL1 has a capacitance corresponding to the entire length of the bit line because the signal ΦT1 is at the “H” level, and therefore, the signal potential difference Δ Is about the normal difference voltage,
In the second bit line BL2, the signal .phi.T2 is set to "L" level to divide the second bit line BL2, so that the bit line capacity is reduced to one half and the signal potential difference is substantially doubled. 2Δ
Of the order. At the same time, since no signal potential difference appears from the switching transistor ST2 to the bit line BL2 on the cell array 1 side, the second bit line BL2
Remains at the equalized voltage Vcc / 2, and the signal potential difference becomes 0V. Here, regarding the noise in the signal potential difference appearing on each bit line, as will be described later, although the configuration of the bit line is an open bit line configuration, as described later, such as a folded bit line configuration, Noise can be reduced.

Then, the signal ΦT3~T6 in matters t ₃ is changed to "L" level from "H" level, switch ing transistor ST3~ST6
Changes from the on state to the off state. Then, the sense amplifiers 3 and 4 are electrically disconnected from the cell arrays 1 and 2, respectively, while the signal potential differences 2Δ, Δ, and 0 appear on the bit lines BL1 and BL2. High-speed sensing operation is being performed.

Its sensing operation, the signal for driving each at time t ₄ sense amplifiers 3, 4 .PHI.P, .PHI.N is initiated changes respectively from Vcc / 2. First, the first sense amplifier 3 includes a part of the first bit line BL1 in which the signal potential difference Δ on the sense amplifier 3 side appears from the switching transistor ST5, and a signal potential difference 0 on the sense amplifier 3 side from the switching transistor ST6. The sensing operation is performed using a part of the second bit line BL2. The second sense amplifier 4 is connected to the first bit line BL1 in which a signal potential difference Δ on the sense amplifier 4 side appears from the switching transistor ST3.
And a second bit line BL having a signal potential difference 2Δ on the sense amplifier 4 side from the switching transistor ST4.
The sensing operation is performed using a part of 2. here,
The signal amplified by the first sense amplifier 3 uses the bit line BL2 having the signal potential difference 0 for reference, and the first sense amplifier 3 always amplifies and latches the signal potential difference Δ of the bit line BL1. This signal potential difference Δ
Access transistor 5 selected by the word line WL
And data of a memory cell having a capacity of 7
The sense amplifier 3 is used for sensing and restoring operations of a reference memory cell. Further, since the signal amplified by the second sense amplifier 4 is sensed between the signal potential difference 2Δ and the signal potential difference Δ, the signal potential difference Δ side having the data resulting from the reference memory cell is the second sense amplifier 4. The second sense amplifier 4 amplifies the signal potential difference 2Δ including the original data appearing on the divided second bit line BL2 to determine the output data. That is, this becomes output data for a predetermined address (memory cell having access transistor 6 of cell array 2), and is output to DB line and ▲ ▼ line via column selection transistors 13 and 14, respectively.

In such a sensing operation, each of the sense amplifiers 3 and 4 always operates with reference to the data of the adjacent memory cell or the reference voltage Vcc / 2, and the operation is performed by the differential noise as in the folded bit line configuration. Can be reduced. In the case of the operation of the second sense amplifier 4, if the data of the reference memory cell is different from the data of the memory cell to be read, the difference voltage is Δ + 2.
Δ = 3Δ, and the sensitivity is sufficiently high.

At time t _5, re-write operation is performed. This rewrite operation is performed by changing the signal ΦT4 and the signal ΦT5 from “L” level to “H” level, and the memory cell (reference memory cell) on the first bit line BL1 side of the cell array 2 and the first
The sense amplifier 3 is connected via the first bit line BL1, and the memory cell (reading memory cell) on the second bit line BL2 side of the cell array 2 and the second sense amplifier 4 are connected via the second bit line BL2. Connected. At this time, the first bit line BL1 is not connected to the second sense amplifier 4, and the second bit line BL2 is not connected to the first sense amplifier 3. Under the control of the switching means, the memory cell (reference memory cell) on the first bit line BL1 side of the cell array 2 is rewritten by the data of the first sense amplifier 3, and the second sense amplifier 4 With the data, the memory cell (reading memory cell) on the second bit line BL2 side of the cell array 2 is rewritten.

Then, the signal ΦWL supplied to the word line WL at time t ₆ is changed to "L" level from "H" level, the cell array 2
The two selected access transistors 5, 6 are
The state changes from the on state to the off state. Then the time t ₇ the signal .PHI.P, signal ΦN is the Vcc / 2, at time t ₈ to Ikoraisu signal ΦEQ "H" level, the time t ₉ in signal .phi.T2, signal Faiti3, signal ΦT6 "H" level and Then, the bit lines BL1 and BL2 are precharged.

Above is the operation for selecting the second bit line BL2 side of the memory cell of the cell array 2, when selecting the first bit line BL1 side of the memory cell of the cell array 1, the signal at time t ₂ .phi.t1 It was used as a "H" level, at time t ₅ signal ΦT
3. The control may be performed such that the signal ΦT6 becomes the “H” level. Further, in the case of selecting the second bit line BL2 side of the memory cell of the cell array 1, a signal ΦT2 at time t ₂ is set to "H" time t ₅ the signal Faiti4, signal ΦT5 becomes "H" level Such control may be performed. Further, when selecting the first bit line BL1 side of the memory cell of the cell array 2, a signal ΦT2 at time t ₂ is set to "H" time t ₅ the signal ΦT
3. The control may be performed such that the signal ΦT6 becomes the “H” level.

Although the above is about the read operation, a similar clock operation can be performed in the write cycle.

In the memory device of the present embodiment, if the sense amplifier for amplifying data is not particularly limited to the second sense amplifier 4, the position of the DB line is changed or a plurality of DB lines are provided and the control of the switching transistors ST1 and ST2 is changed. Thus, the side on which the signal potential difference becomes 2Δ (or Δ) can be always used for data reading. Furthermore, it is also possible to arrange more cell arrays on a combination such as block division or a pair of bit lines. Sense amplifier CM
It is not limited to the OS configuration.

In the memory device of the present embodiment that performs the above-described operation, first, the bit line configuration is an open bit line configuration in which a memory cell is formed at the intersection of a bit line and a word line. It is possible to achieve higher integration than a memory device having a folded bit line configuration in which memory cells are provided at intersections of lines and bit lines. Particularly, in the memory device of the present embodiment, the pair of bit lines BL1 and BL2 are amplified by using two sense amplifiers while being divided by the switching transistors, so that the pitch of the two bit lines (in the word line direction). In the meantime, the sense amplifier can be learned with a margin in the cell array, which is advantageous in the layout even when the pitch of the bit line is narrow, and the high integration of the memory device is easy.

In addition, in the operation, noise can be reduced as in the folded bit line configuration by the switching means, even though the configuration is the open bit line configuration as described above, and the signal potential difference is increased to increase the signal potential. Sensitivity can be improved.

H. Effects of the Invention The memory device of the present invention can achieve high integration such as an open bit line configuration from the above configuration, and at the same time, if the sense amplifiers are arranged at a pitch of two bit lines. Good for layout. Also, despite high integration like open bit line configuration, sensing operation is performed while referring to each other with a pair of bit lines, thus reducing differential noise like folded bit line configuration. can do.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of the memory device of the present invention. FIG. 2 is a time chart for explaining an example of the operation. 1,2: Cell array 3,4: Sense amplifiers ST1 to ST6: Switching transistors (switching means) BL1, BL2: Bit lines WL: Word lines

Claims (1)

(57) [Claims] A first and a second switching means which are arranged in parallel and divided by first and second switching means which are electrically controlled to be connected and disconnected independently by first and second control signals, respectively. A pair of complementary bit lines, a word line arranged orthogonally to the first and second complementary bit line pairs, and an intersection of one and the other bit lines of the first complementary bit line pair with the word line. A first memory cell array in which memory cells each composed of a capacitive element and an address selection gate are arranged in a lattice pattern, and an intersection of one of the second complementary bit line pairs and the other bit line and a word line, respectively. A second memory cell array in which memory cells each composed of a capacitive element and an address selection gate are arranged in a grid, and a third memory cell array in which connection and release are electrically controlled independently by third and fourth control signals. A first sense amplifier in which a complementary input signal terminal pair is connected to the first complementary bit line pair via third and fourth switching means; and a fifth and sixth control signal, which are electrically independent of each other. And a second sense amplifier in which a complementary input signal terminal pair is connected to the second complementary bit line pair via fifth and sixth switching means for controlling connection and disconnection. Storage device.