JP2576032B2 - Television signal receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television signal receiving apparatus for displaying one image on a screen constituted by a plurality of displays.

[0003]

[0002]

[0004]

2. Description of the Related Art The current television broadcasting standard in Japan is the NTSC system. On the other hand, in order to obtain a higher-quality image, it has been proposed to change the broadcasting system to a high-vision system.

[0005] Since the TV signal of the HDTV system is different from the TV signal of the NTSC system, the TV signal of the conventional NTSC system is used.
It cannot be received by the V receiver as it is.

Therefore, the high-vision TV signal is converted to NT signal.
It has been proposed that the signal be converted into an SC TV signal and received by an NTSC TV receiver.

[0007]

[0003]

[0008]

However, such a conventional proposal proposes that a high-definition TV signal be transmitted to one NTS.
Since the image is received by the C-type TV receiver, there is a disadvantage that only a high-quality image in the NTSC method can be obtained. Therefore, despite the fact that the source is of the high-vision type, the merits of the source were not utilized, and high-quality images could not be viewed.

[0009]

[0004] Therefore, the present invention is intended to display an image of the Hi-Vision system on a TV receiver of the NTSC system (including a projection TV or the like) while maintaining its high quality.

[0010]

[0005]

[0011]

A television signal receiving apparatus according to the present invention includes an A / D converter for A / D converting a high definition TV signal, and an A / D converted TV signal for at least one field. A memory for storing, and a high-definition TV signal stored in the memory,
A vertical filter that converts the five horizontal scanning lines at a ratio of seven horizontal scanning lines of the NTSC TV signal, and four filters in the horizontal direction and three in the vertical direction, and a total of 12 N filters are arranged.
A plurality of displays driven by TSC-type TV signals, wherein the TV signals converted into NTSC signals obtained by the vertical filter are displayed on the plurality of displays. The vertical filter includes a delay unit in which a plurality of 1H delay units for delaying a high definition TV signal stored in the memory for one horizontal scanning line period (1H) are connected in cascade, and an output of each 1H delay unit is Multiplication means comprising a plurality of coefficient circuits for multiplying a predetermined coefficient;
Adding means for adding the outputs of the coefficient circuits.

[0012]

[0006]

[0013]

[Function] There are four NTSC displays horizontally and three vertically.
One screen is configured by arranging a total of 12 units. The high definition TV signal is A / D converted by an A / D converter and stored in a memory. The data read from the memory is generated by increasing the number of horizontal scanning lines by generating seven NTSC horizontal scanning lines from five HDTV horizontal scanning lines by a vertical filter. The increased horizontal scanning line is divided into three in the vertical direction and further divided into four in the scanning direction, and supplied to each display.

Therefore, it is possible to display a high-vision image on an NTSC display without deteriorating its high quality.

[0015]

[0007]

[0016]

FIG. 2 schematically shows an NTSC TV screen. In this method, the aspect ratio of the screen is set to 4: 3, and the number of horizontal scanning lines in one frame is 525. Among them, the number of horizontal scanning lines of the effective screen appearing on the actual screen is, for example, 483. Also, when digitally processing an image, 1
When the sampling number of the horizontal scanning lines is 360,
The sampling number of the effective screen portion is, for example, 297.

[0017]

FIG. 3 schematically shows a high-definition TV screen. In this system, the aspect ratio of the screen is 16: 9, and the number of horizontal scanning lines of one frame is 112.
There are five. In the above example, the number of horizontal scanning lines on the effective screen is 1,035. When the sampling number of one horizontal scanning line is 1440, the sampling number of the effective screen portion is 1188.

[0018]

FIG. 4 shows the structure of a screen according to the present invention. In the present invention, a total of twelve CRTs (which may be liquid crystal displays or the like) 11 to 34 as NTSC display devices are arranged in a horizontal direction and three in a vertical direction.
One screen is configured. Since each CRT is set to have an aspect ratio of 4: 3 corresponding to the NTSC system,
When the RTs are arranged in this manner, the aspect ratio of the screen constituted by the 12 CRTs becomes 16: 9, and a screen that matches the aspect ratio of the HDTV system can be obtained.

[0019]

However, since the number of horizontal scanning lines of each CRT is 525, displaying one image on the entire screen requires 1575 (= 525 × 3) horizontal scanning lines. Since the number of high-definition horizontal scanning lines is 1125, it is necessary to increase the number to 1575.
Since the least common multiple of both is 7875, the number may be increased by generating seven NTSC horizontal scanning lines from five HDTV horizontal scanning lines.

[0020]

The first 525 of the 1,575 horizontal scanning lines generated in this manner are replaced with the four upper CRTs 11.
To the CRTs 21 to 24, and the next 525 to the middle CRTs 21 to 24, and the last 525 to the lower CRTs 31 to 34.
, Each CRT is scanned by 525 horizontal scanning lines as in the case of the normal NTSC system.

However, since four CRTs are arranged in the horizontal direction, the horizontal scanning line is divided into four equal parts in the horizontal direction,
Signals of 1/4 of the original length are sequentially supplied to Tn1 to n4.

[0022]

In this way, one image can be displayed on 12 CRTs.

FIG. 5 is a block diagram of a television signal receiving apparatus according to the present invention. In FIG. 1, reference numeral 1 denotes a high-vision television camera, which outputs a high-vision television (TV) signal. Of course, the TV camera 1 can be replaced with a high-definition television tuner, VTR, or the like.

[0024]

Reference numeral 2 denotes an A / D converter, which receives an input TV.
A / D-convert the signal. 3 is a frame memory;
The / D converted TV signal is stored for one frame. Reference numeral 4 denotes a vertical filter, which changes the number of horizontal scanning lines. Reference numeral 5 denotes an NTSC-type CRT arranged as described above.

[0025]

FIG. 1 is a more detailed block diagram of the apparatus shown in FIG. The A / D converter 2 is, for example, 48.6 MHz.
The input HDTV signal is converted to A /
D-converted to 8-bit digital data. A / D
The output of the converter 2 is input to and latched by the latch circuits D1 and D2. The latch circuits D1 and D2 are operated at the negative edge and the positive edge of the 24.3 MHz clock, respectively.

[0026]

Corresponds to 1/3 of the horizontal scanning line of the first field of the output of the latch circuit D1.

The upper four bits of the data to be stored are stored in the memory MFMA1.

[Outside 1] U, its lower 4

The bit is the memory MFMA1

Are stored in L respectively. Of course, it is theoretically possible to configure these as one memory.

Similarly, data of the next 1/3 horizontal scanning line is stored in the memory MFMA2.

[Outside 1] U,

2

In the L, the last 1/3 of the data is stored in the memory MFMA
3

[Outside 1] U, 3

Are stored in L respectively. A negative edge of 24.3 MHz is used as a write clock for these memories.

[0031]

On the other hand, the data of the same field output from latch circuit D2 are similarly stored in memories MFMA1QU,
QL, 2QL, 2QL, 3QL, and 3QL.
The write clock for these memories is 24.3
MHz positive edge is used.

[0032]

Thus, one field of data is stored in these memories.

However, as will be described later, a new one horizontal scanning line is generated by performing arithmetic processing on seven consecutive horizontal scanning lines H. Therefore, the upper memory MF
MA

1 QUA, 1 QL, 1

[Outside 1] U, 1

[1] For the last 3H written to L

The data is stored in the middle memory MFMA2QU,
2QL, 2

[Outside 1] U, 2

Is written to L at the same time. The same goes for the middle memory and the lower memory, and the lower memory and the upper memory.

[0036]

[0018]

In the same manner as described above, data for the next one field is stored in the memory MFMB1.

[Outside 1]

U, 1

[Outside 1] L, 2

[Outside 1] U, 2

[Outside 1] L, 3

[Outside 1] U, 3

[1] L, 1 QL, 1 QL, 2 QL, 2 QL, 3 Q
U and 3QL, respectively.

Thus, the memory MFMA1

The data for one frame is stored in the frame memory 3 composed of U to MFMB3QL.

[0040]

[0019]

Upper memory MFMA of one field
1

[Outside 1] U, 1

The data written in L, 1 QUA, and 1 QL are 1
The data is read at the negative edge and the positive edge of the 1.3 MHz clock, and is latched by the latch circuits D31 and D41. The data latched by the latch circuits D31 and D41 is 22.7.
The signal is input to a latch circuit D51 operating with a clock of MHz and is integrated. The data output from the latch circuit 51 is input to the vertical filter 41. The memory MFMB1 in the upper stage of the other field

[0042]

[Outside 1] U, 1

The data stored in L, 1 KU, and 1 QL are also input to the vertical filter 41.

[0043]

[0020]

Similarly, the memory MFMA2 in the middle stage of the two fields

[Outside 1] U, 2

[0045]

[Outside 1] L, 2QL, 2QL, MFMB2

[Outside 1] U, 2

The data of L, 2 QUA, and 2 QL are stored in the latch circuit D.
32, 42, 52 to the vertical filter 42

The lower memory MFMA3

[Outside 1] U, 3

[Outside 1] L, 3QL, 3QL, M

FMB3

[Outside 1] U, 3

The data of L, 3KU, and 3QL are stored in the latch circuit D.
The signals are input to the vertical filter 43 via 33, 43 and 53, respectively.

[0048]

FIG. 6 shows the configuration of the vertical filter 41 (the same applies to the vertical filters 42 and 43). The vertical filter 41 includes 1H memories H1 to H7 as delay means for delaying an input signal by 1H, coefficient circuits K1 to K7 such as PROMs for multiplying a predetermined coefficient, addition circuits A11 to A16, and latch circuits D61 to 67 , 71 to 77, 81, and 82.

These circuits are driven by a 22.68 MHz clock. The coefficient circuits K1 to K7 change coefficients in 7H cycles.

[0050]

The 1H memories H1 to H7 are connected in cascade, and their outputs are multiplied by predetermined coefficients by coefficient circuits K1 to K7. The outputs of the coefficient circuits K1 to K7 are added by adders A11 to A16.

[0051]

In the vertical filter, in a certain 1H section, a signal output from a certain 1H memory is Qn, a signal output from the memory in the next 1H section is Qn + 1, and an output of the vertical filter is Pi. The equation holds.

[0052]

(Equation 1)

[0053]

Here, hn is an impulse response of the filter, and hn = hn.

In this way, a new one horizontal scanning line is generated by adding a product obtained by multiplying each of the seven consecutive horizontal scanning lines by a predetermined coefficient.

This processing is executed at the timing shown in FIG. That is, each 1H memory sequentially transfers the first 2H section data, but does not transfer data in the next 1H section, transfers the next 3H section data, and transfers the next 1H section data.
Stop the section data transfer. However, during this time, the constant of each coefficient circuit is changed for each H, and the output is calculated and generated for each H. As a result, new horizontal scanning lines are generated at a rate of seven out of five horizontal scanning lines.

[0056]

The first quarter of the 1H data output from the vertical filter 41 is a 1H memory OHM11.
In the following, the next 以下 data is the memory OHM12, the third デ ー タ data is the memory OHM13, the last １ ／
Are written into the OHM 14 with a clock of 22.7 MHz. The data written in each memory is read out at a clock of 5.67 MHz, D / A converted by D / A converters DA11 to DA14, and output to CRTs (monitors) 11 to 14 arranged in a horizontal direction. You.
Each of the memories OHM11 to OHM14 incorporates two 1H memories, and when data is written to one of the memories, the operation of reading from the other is performed alternately.

[0057]

Similarly, the data output from the vertical filter 42 is transferred to the middle CRTs 21 to 24 via the memories OHM21 to OHM24 and the D / A converters DA21 to DA24.
Supplied to The data output from the vertical filter 43 is stored in the memories OHM31 to OHM31 and the D / A converter DA3.
The signals are supplied to lower CRTs 31 to 34 via 1 to 34. In this manner, one image is displayed by the 12 CRTs.

[0058]

The same operation can be performed even if the vertical filter 4 is arranged at the preceding stage of the frame memory 3. However, doing so not only complicates the configuration of the vertical filter 4 but also increases the number of input terminals to the frame memory 3.

[0059]

In the above description, the horizontal scanning lines constituting one screen (field) are divided into three in the vertical direction.
Although the data is stored in the memory of the stage, it is also possible to divide the data into four in the horizontal direction and store the data in the memory of the four stages. However, doing so increases the capacity of the frame memory.

[0060]

[0029]

[0061]

As described above, according to the present invention, a total of twelve NTSC-type CRTs are arranged in four horizontal units and three vertical units, so that
Screen, and 7 horizontal scanning lines of HDTV system
Since the power supply is increased by a factor of / 5 and divided and supplied to each CRT, a high-quality image can be displayed using an NTSC CRT.

[Brief description of the drawings]

FIG. 1 is a more detailed block diagram of the apparatus of FIG.

FIG. 2 is an explanatory diagram of the NTSC system.

FIG. 3 is an explanatory diagram of a high vision system.

FIG. 4 is an explanatory diagram of a CRT according to the present invention.

FIG. 5 is a block diagram of a television signal receiving device of the present invention.

FIG. 6 is a block diagram of a vertical filter in FIG. 1;

FIG. 7 is a timing chart of a vertical filter.

[Explanation of symbols]

 Reference Signs List 1 TV camera 2 A / D converter 3 Frame memory 4 Vertical filter 5 CRT

Claims (1)

(57) [Claims] 1. An A / D converter for A / D converting a Hi-Vision TV signal, a memory for storing at least one field of the A / D converted TV signal, and a Hi-Vision system stored in the memory. The TV signal is read out, and the five horizontal scanning lines are set to NTSC TV.
A vertical filter for converting a signal at a ratio of seven horizontal scanning lines, and a plurality of display units driven by NTSC TV signals, arranged four in the horizontal direction and three in the vertical direction, a total of twelve. A television signal receiving apparatus configured to display a TV signal converted into an NTSC signal obtained by the vertical filter on the plurality of displays, wherein the vertical filter is stored in the memory. Delay means for cascading a plurality of 1H delayers for delaying the high definition TV signal by one horizontal scanning line period (1H); and a plurality of coefficient circuits for multiplying the outputs of the respective 1H delays by predetermined coefficients. A television signal receiving apparatus, comprising: a multiplying means; and an adding means for adding outputs of the coefficient circuits.