JP2571592B2 - Optical scanning device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an optical scanning device that does not use an fθ lens.

(Prior Art) An optical scanning device is known as a device for writing optical information or reading image information by scanning a scanned surface with a light beam.

In such an optical scanning device, the light beam is generally deflected at a constant angular velocity by a rotary deflector such as a polygon mirror or a holographic scanner. In general, in order to keep the scanning speed on the surface to be scanned constant. Uses an fθ lens. However, since the fθ lens is a special lens with high cost, there is a demand that the fθ lens should not be used if possible. Recently, a polygon mirror in which the scanning angular velocity of a light beam is not constant has been proposed (Japanese Patent Application No.
In such a case, even if an fθ lens is used, the scanning speed is not constant, and in such a case, the fθ lens cannot be used.

The image scanning clock is a clock signal for turning on / off the scanning light beam during optical scanning, and has a frequency fk
Is given by 1 / T, where T is the time allotted for reading or writing information of one pixel. If the fθ lens is not used, the scanning speed of the surface to be scanned by the scanning light beam will not be constant.Therefore, if the frequency fk of the image scanning clock is kept constant, distortion occurs in writing and reading of information. Become.

For example, in FIG. 7, reference numeral 30 denotes a photoconductive photoreceptor as an object to be scanned, reference numeral 32 denotes a polygon mirror for deflecting the light beam L at a constant angular velocity, and reference numeral 34 denotes a light beam L to be scanned. 5 shows a condenser lens for focusing on a scanning plane. The light beam L is generally laser light from a gas laser or a semiconductor laser. If the distances l and h are selected as shown in FIG. 7, h = l · tan θ If the angle of the polygon mirror 32 is ωo (constant), the angular velocity of the scanning light beam Therefore, the scanning speed dh / dt is Becomes Assuming that the scanning area length is 2H as shown in the figure and H + h = h ', It is. Now, assuming that this scanning region length 2H has pixels 2n _o, scanning speed Vn at n-th pixel counted from the scanning start side of the left scanning region of Figure 7 is It is. Here, d is one pixel width. By definition, the frequency fk of the image scanning clock is Vn / d in this case, Becomes Therefore, if the image scanning clock frequency fk is changed for each pixel according to the equation (1), optical scanning can be realized without causing distortion in reading and writing of information without using an fθ lens. However, since the scanning speed by the polygon mirror 32 is not constant, the exposure amount of the scanning area is flat in the scanning direction, and uneven exposure occurs.

Therefore, an optical scanning device that scans a surface to be scanned by a rotary deflector with modulated light from a semiconductor laser and does not use an fθ lens, and in which image scanning in which the frequency continuously changes according to a change in the scanning speed of the surface to be scanned. An image scanning clock generator for generating a clock, a digital value setting circuit for generating a digital value for changing the output intensity of the semiconductor laser according to a change in the scanning speed of the surface to be scanned, and a digital value setting circuit. A digital / analog converter for converting an output value to an analog value and changing the current of the semiconductor laser according to the analog value, wherein the gain of the output of the digital / analog converter is adjusted to the digital / analog value. A method has been proposed to adjust the change in the output intensity of the semiconductor laser according to the output value of the analog converter so as to be optimal. And that (JP 62-30466 JP).

To explain an example of an optical scanning device to which this method is applied, an image scanning clock generator in this example includes an oscillator, a first frequency divider, an up / down counter, a control circuit, and a phase locked loop circuit. Have. The phase locked loop circuit is abbreviated as PLL below.

The oscillator generates a reference clock. The frequency of this reference clock is hereinafter referred to as fo. fo is, of course, a constant.

The first frequency divider divides the frequency of the reference clock to generate a position control clock.

An up / down counter (hereinafter abbreviated as U / D counter) switches the frequency division ratio N of the first frequency divider.
N is, of course, a natural number.

The control circuit has the following functions. The scanning area is
It is divided into K blocks BLi (i = 1 to K) in advance, and a predetermined finite sequence Mi (i = 1 to K)
In the i-th block BLi (i = 1 to K), the U / D counter is driven for each Mi pulse of the position control clock to divide N i in the entire scanning area.
Is realized in a stepwise manner. That is, if the dividing ratio N
If the initial value of No. is No, the frequency of the position control block is initially fo / No. However, when the position control block is counted by M1 pulses in the first block BLi, the control circuit sets the U / D counter to The frequency division ratio of the first frequency divider is switched from No to N ₁ (= No + ΔN). Then, the frequency of the position control clock becomes fo / N _1. The clock of this frequency becomes the M1 pulse. The new frequency of the clock M1 pulses, when the count further from dividing ratio N ₁ to N ₂ Setsu換Ru, that is repeated n1 times. Subsequently, in the second block BL2, the position control block M2
Switching the frequency division ratio for each pulse is repeated n2 times. This process is performed for each block. In the i-th block BLi, the frequency division ratio is switched ni times for each Mi pulse of the position control clock.

The PLL circuit includes a phase detection circuit, a low-pass filter, a second frequency divider, and a voltage controlled oscillator. The second divider has a fixed division factor M.

This PLL circuit generates an image scanning clock whose frequency changes continuously according to the stepwise change of the frequency of the position control clock.

Hereinafter, this image scanning clock generator will be described with reference to the drawings.

In FIG. 5, a phase detection circuit 18, a low-pass filter 20, a voltage controlled oscillator 22, and a second frequency divider 24 constitute a PLL circuit.

The reference clock of the frequency fo generated from the oscillator 10 is frequency-divided by the first frequency divider 12 to generate the frequency fo / N of the frequency fo / N.
It becomes a position control clock and is input to the control circuit 16 and the phase detection circuit 18 of the PLL circuit.

The phase detection circuit 18 compares the phase of the position control clock with the phase of the clock CLA input from the frequency divider 24, and outputs the phase difference to the low-pass filter 20 as a pulse signal. When the information on the phase difference is input to the voltage-controlled oscillator 22 via the low-pass filter 20, the oscillator 22 outputs a clock having a frequency corresponding to the output voltage of the low-pass filter 20. This clock becomes the image scanning clock. The image scanning clock is frequency-divided by the frequency divider 24, applied to the phase detection circuit 18 as the clock CLA, and compared in phase with the position control clock.

By the way, in the PLL circuit, the frequency of the clock generated from the voltage controlled oscillator 22 does not change when there is no change in the phase difference between the clock CLA whose phase is compared by the phase detection circuit 18 and the position control clock. Such a state will be referred to as an equilibrium state of the PLL circuit.

For example, if the frequency of the position control clock is fo / N in the balanced state of the PLL circuit, then the clock CLA
Is also fo / N, and in this state, fk of the clock generated from the voltage controlled oscillator 22 is It is. In this state, when the frequency division ratio of the frequency divider 12 is switched from N to N ', the frequency of the position control clock becomes And a phase difference occurs with the clock CLA. Accordingly, the output clock frequency fk of the voltage controlled oscillator 22 also changes in accordance with this, but this change in the frequency fk occurs continuously, and the frequency fk becomes Changes continuously and monotonically.

Therefore, the frequency fk of the image scanning clock can be changed continuously by changing the frequency dividing ratio N of the frequency divider 12 stepwise.

Now, the control circuit 16 outputs a clock CK for causing the U / D counter 14 to output the preset value of the division ratio in the frequency divider 12, and a signal E that enables the U / D counter 14 to count.
N, issue signal U / D to determine up / down mode.

The up / down mode is a signal U / D that switches from the up mode (or down mode) to the down mode (or up mode) near the extreme of the scanning speed.
Occurs.

When the clock CK is input, the U / D counter 14 updates the preset value and switches the frequency division ratio of the frequency divider 12.

As described above, the generation of the clock CK is performed in each block.
A finite sequence Mi (i = 1 to K) for each BLi (i = 1 to K)
It is performed based on That is, for each block,
Mi and ni are preset, and the i-th block BLi
Then, every time the position control clock inputs Mi pulse,
A clock CK is generated from the control circuit 16, and this clock CK
CK occurs ni times in this block BLi.

The number of blocks K and the values of Mi and ni are set so that the frequency fk of the image scanning clock generated from the voltage controlled oscillator 22 changes well with the change in scanning speed, for example, the equation (1). This is determined experimentally or theoretically according to the design conditions.

FIG. 8 shows an example of a stepwise change of the clock f'k due to the change of the ideal image scanning clock fk (curve 4-1) and the switching of the frequency division ratio. The numbers 5, 6, 10, and 16 below the stepped frequency variation correspond to M1, M2, M3, and M4, respectively, with the right end of the figure as the scanning start side. As can be seen from the figure, n1 = 6, n2 = 9, n3 = 3, n4 = 5. This figure shows only the right half of the symmetric figure, M5 = 10, n5 = 3, M6 = 6, n
6 = 9, M7 = 5, n7 = 6. As you can see from this figure,
The block BLi is a region where a continuous curve of the frequency fk is linearly approximated, and the width of the step is equal in each block. The clock f'k is the position control clock M
Equivalent to double. The clock f'k itself changes stepwise, but the frequency of the actual image scanning clock changes continuously due to the operation of the PLL circuit, and approximates the curve 4-1 well.

FIG. 6 shows an illustrative timing diagram of the device shown in FIG. In order from the top, a synchronization signal, a scanning speed, a frequency division ratio N, and a frequency fo / N of the position control clock are shown. Since the up / down mode of the U / D counter 14 is switched near the extreme value of the scanning speed, the dividing ratio N,
Both fo / N and fk are symmetrical with respect to the position near the extreme value.

The synchronization signal is the output of the optical sensor indicated by reference numeral 36 in FIG. 7, and the first frequency divider 12 is initialized by the synchronization signal. The synchronization signal is also applied to the control circuit 16.

The signal EN causes the counter operation to be performed with a delay of a predetermined time Ta after receiving the synchronization signal.
The counter operation ends after a delay of time. At the end of the counter operation, the frequency division ratio N is fixed to the initial value.

 FIG. 4 shows this circuit configuration.

The digital value setting circuit 41 changes the output intensity of the semiconductor laser 42 according to the change in the scanning speed of the light beam on the surface to be scanned, and generates a digital value for eliminating exposure unevenness. Is used. This U
As shown in FIG. 9A, the / D counter 41 receives the clock CK from the control circuit 16 to the U / D counter 14, the enable signal EN, and the up / down mode signal U / D in the image scanning clock generator 43. The added U / D count is performed,
A digital value is generated according to the change in the light beam scanning speed. The digital value setting circuit 41 uses an adder (or subtractor) as shown in FIG. 9 (b) to add (subtract) the output of the U / D counter 14 and a predetermined value set in advance. You may. The output of the digital value setting circuit 41 is converted to an analog value by the digital / analog converter 44, and becomes a value corresponding to the change of the light beam scanning speed as shown in FIG.

On the other hand, the laser beam emitted from the semiconductor laser 42 is condensed by the condensing lens 34, deflected by the polygon mirror 32, and condensed on the charged surface of the photoreceptor 30, as shown in FIG. The imaged spot is repeatedly moved by the rotation of the polygon mirror 32, and at the same time, the photoconductor 30 is rotated. The optical sensor 36 is provided outside the information writing area and detects a laser beam deflected by the polygon mirror 32 to generate a synchronization signal. The semiconductor laser drive circuit 45 receives a modulation signal in synchronization with the image scanning clock and drives the semiconductor laser 42 with the modulation signal.
Therefore, the photoconductor 30 is irradiated with the laser beam modulated by the modulation signal to form an electrostatic latent image. This electrostatic latent image is developed by a developing device and transferred to paper or the like by a transfer device.

The laser beam emitted backward from the semiconductor laser 42 enters a photodetector 46 composed of a photodiode, and the photodiode 46 outputs a current proportional to the intensity of the laser beam. This current is converted into a voltage by an amplifier 47 and compared with a reference voltage Vref by a comparator 48. Comparator
The output voltage of 48 becomes high level or low level depending on the magnitude relation of both input voltages of the comparator 48. Up / down counter
Control 49 count modes.

For example, when the intensity of the laser beam from the semiconductor laser 42 is weaker than the reference value, the output of the comparator 48 becomes low, and the up / down counter 49 operates as an up counter. The edge detection circuit 50 detects a rising edge of the frame synchronization signal FSYNC which becomes low level in the recording mode. The detection signal passes through an OR circuit 51 and is ANDed with the frame synchronization signal FSYNC by an AND circuit 52. The flip-flop 53 is set at the beginning of the standby mode by the output signal of the AND circuit 52 to generate an output signal, and this output signal is ANDed with the non-photoconductor scanning signal from the signal processing circuit by the AND circuit 54. and/
The down counter 49 is enabled by the output signal of the AND circuit 54, and counts up / down the clock pulse from the clock pulse generator 55. The count output of this up / down counter 49 is digital /
It is converted to an analog quantity by the analog converter 56, and is an arithmetic unit
It is applied to the semiconductor laser drive circuit 45 via 57. The semiconductor laser drive circuit 45 drives the semiconductor laser 42 according to the modulation signal from the signal processing circuit, and changes the drive current according to the output of the digital / analog converter 56. Therefore, as the count value of the up / down counter 49 gradually increases, the intensity of the laser beam from the semiconductor laser 42 gradually increases, and the output voltage of the multiplier 47 increases. When scanning the photoreceptor, the non-photoreceptor scanning signal is lost and the AND circuit 54 is turned off and the up / down counter
49 is disabled and the semiconductor laser 42
Are not driven during the photoconductor scanning in the standby state, and the power setting of the semiconductor laser 42 is interrupted if not completed.
Then, at the time of non-photoconductor scanning, the power setting of the semiconductor laser 42 is restarted again. Thereafter, when the output of the comparator 48 is inverted from the low level to the high level, the edge detection circuit 58 detects the rising edge of the output of the comparator 48, resets the flip-flop 53 via the OR circuit 60, and sets the up / down counter. 49 is returned to the disabled state. Therefore, the up / down counter 49 holds the count value, and accordingly, the magnitude of the drive current of the semiconductor laser 42 is held as it is. When the up / down counter 49 is enabled by the output signal of the AND circuit 54, the comparator 48
Is high level (if the output intensity of the semiconductor laser is high), the up / down counter 49 operates as a down counter, and the count value is decreased by the clock signal from the clock pulse generator 55. Therefore, the output of the digital / analog converter 56 decreases, the drive current of the semiconductor laser 42 decreases, and the output of the amplifier 47 decreases.
When the output of the amplifier 47 becomes smaller than the reference voltage Vref and the output of the comparator 48 is inverted from a high level to a low level,
The edge detection circuit 58 detects the rising edge of the output of the comparator 48, resets the flip-flop 53, and returns the up / down counter 49 to the disabled state. Therefore, the up / down counter 49 holds the count value, and the magnitude of the drive current of the semiconductor laser 42 is held as it is. Here, the edge detection circuit 58 is a comparator
If the up / down counter 49 is disabled only when the output of 48 is inverted from low to high, the output of the comparator 48 is low and the up / down counter 49 is enabled. Comparator
When the output of 48 is inverted from a low level to a high level, the up / down counter 49 is disabled and holds the count value. Output of comparator 48 rises at high level /
When the output of the comparator 48 changes from the high level to the low level while the down counter 49 is in the enabled state, the up / down counter 49 operates as the up counter by the output of the comparator 48 with the disabled state being released. When the drive current of the semiconductor laser 42 increases and the output of the comparator 48 is inverted from low level to high level, the edge detection circuit 58 detects the rising edge and sets the up / down counter 49 to the disabled state.
The count value is held.

The output control timing generator 61 outputs a frame synchronization signal.
By operating in the standby mode by FSYNC, an output control timing signal is generated at a constant period T and output to the OR circuit 51, whereby the power setting of the semiconductor laser 42 is performed at a constant period.

The up / down counter 49 operates as a down counter when the output of the comparator 48 is low and operates as an up / down counter when the output of the comparator 48 is high. The current may be inversely proportional.

The output of the digital / analog converter 44 is amplified by an amplifier 59 and applied to a semiconductor laser drive circuit 45 via an arithmetic unit 57. The semiconductor laser drive circuit 45 generates a drive current of the semiconductor laser 42 according to an output signal of the arithmetic unit 57. Change.
In the image scanning clock generator 43, the control circuit 16 uses the output signal of the flip-flop 53 to perform digital / analog conversion when the power of the semiconductor laser 42 is set.
The digital value setting circuit 41 is controlled so that the output of 44 does not contribute to the semiconductor laser driving circuit 45. When the power setting of the semiconductor laser 42 is not performed, the output of the digital / analog converter 56 is held and the digital / analog conversion is performed. The drive current of the semiconductor laser 42 changes according to the change of the scanning speed by the output of the analog converter 44. Semiconductor laser
The output intensity of 42 is controlled to a constant value by the power set, and the value can be adjusted by changing the reference signal Vref. In addition, if the output intensity of the semiconductor laser 42 due to the output of the digital value setting circuit 41 is appropriate, exposure unevenness due to the change in scanning speed is eliminated. At the time of production, for example, an operator turns on the switch 62 to set the semiconductor laser output intensity modulation mode, and increases the output value of the semiconductor laser 42 to the analog value of the digital / analog converter 44 by the output of the digital value setting circuit 41. The semiconductor laser drive circuit 45 drives the semiconductor laser with a drive current corresponding to a value calculated by the calculator 57 between the output value held by the down counter 49 and the analog value of the digital / analog converter 56 output.
The output intensity of the semiconductor laser is measured with a power meter, and the gain is adjusted by varying the gain of the amplifier 59 so that the maximum value becomes an appropriate value. In this case, the control circuit 16 in the image scanning clock generator 43 forcibly resets the flip-flop 53 via the OR circuit 60 in response to the ON signal from the switch 62, and sets the up / down counter 49 to the disabled state. Therefore, the count value of the up / down counter 49 is held, and the output intensity of the semiconductor laser 42 is calculated from the intensity corresponding to the count value by the digital value setting circuit.
It decreases corresponding to the output of 41.

In this optical scanning device, the output power P of the semiconductor laser 42
11 and 12 show the relationship between the change width ΔP and the change width ΔI of the drive current I of the semiconductor laser 42 and the image height,
Since the semiconductor laser 42 has significantly different IP characteristics, the ΔI is varied by adjusting the output gain of the digital / analog converter 44 (gain of the amplifier 59) to vary the output value of the digital / analog converter 44. The change in the output intensity of the semiconductor laser 42 is adjusted to be optimal. However, before this adjustment, the output power P of the semiconductor laser 42 with respect to the end and the center of the surface to be scanned is respectively set.
Let P _A and P _B be the output powers P of the semiconductor laser 42 with respect to the edge and the center of the scanned surface after the adjustment, respectively.
Assuming that P _A ′ and P ′ _B , the reference voltage Vref is adjusted to adjust the output power of the semiconductor laser 42 after adjusting the gain of the output of the digital / analog converter, and P _{A is set} to P _A ′. As shown in FIG. 14 and FIG. 14, ΔI is ΔI ′ (≠ ΔI)
become And uneven light quantity occurs. Therefore, by manually adjusting the gain of the digital / analog converter to vary ΔI ′, And must be.

(Object) It is an object of the present invention to improve the above-mentioned drawbacks and to provide an optical scanning device which does not require manual adjustment of the gain of a digital / analog converter output after varying the output power of a semiconductor laser.

(Constitution) The present invention is an optical scanning device which scans a surface to be scanned by a rotary deflector with modulated light from a semiconductor laser and does not use an fθ lens, comprising an image scanning clock generator, a digital value setting circuit, It has an analog converter and a gain adjustment unit. The image scanning clock generator generates an image scanning clock whose frequency changes continuously according to the change in the scanning speed of the surface to be scanned, and the digital value setting circuit operates the semiconductor laser according to the change in the scanning speed of the surface to be scanned. Generates a digital value for varying the output intensity of The digital / analog converter converts the output value of the digital value setting circuit into an analog value and changes the current of the semiconductor laser according to the analog value, and the gain adjustment section generates the gain of the digital / analog converter to generate a reference voltage. Adjust according to the output of the vessel.

 Next, examples of the present invention will be described.

FIG. 1 shows an embodiment of the present invention, and the same parts as those in FIG. 4 are denoted by the same reference numerals.

In this embodiment, the main circuit operation is the same as that of FIG. 4, and the output of the digital / analog converter 44 is
Sent to The reference voltage generator 63 compares the reference voltage Vref
The signal is sent to the gain adjustment unit 64 and the gain adjustment unit 64, and the gain adjustment unit 64 adjusts the gain of the digital / analog converter 44 according to the reference voltage Vref. Further, the gain adjusting unit 64 adjusts the gain of the digital / analog converter 44 by manual operation when the switch 62 is turned on so that the change in the output intensity of the semiconductor laser 42 due to the output value of the digital / analog converter 44 is optimized. Instead of directly adjusting the gain of the digital / analog converter 44 directly, an amplifier is provided after the digital / analog converter 44, and the gain of this amplifier is manually adjusted when the switch 62 is turned on, so that the digital / analog converter 44 The change in the output intensity of the semiconductor laser 42 according to the output value of 44 may be optimized, and this case is also included in the present invention.

When adjusting the image density, the operator must use Vref
The variable signal is applied to the reference voltage generator 63 by a device (not shown), and the reference voltage generator 63 varies the reference voltage Vref according to the Vref variable signal. By applying the variable reference voltage Vref to the comparator 48, the output power P of the semiconductor laser 42 is varied, and the density of the image density is adjusted. At the same time, the gain adjuster 64 adjusts the gain of the digital / analog converter 44 according to the variable reference voltage Vref from the reference voltage generator 63. Is adjusted so that the light amount unevenness does not occur.

The gain adjuster 64 is composed of, for example, a variable resistor VR, resistors R1 and R2 and a capacitor C as shown in FIG. 2, and converts an output voltage from the reference voltage generator 63 according to the reference voltage Vref into a digital / analog converter. Output to 44 to set the gain.

The output of the variable resistor VR is adjusted by manually adjusting the variable resistor VR when the switch 46 is turned on, and the gain of the digital / analog converter 44 is adjusted. The reference voltage generator 63 is composed of, for example, a digital / analog converter as shown in FIG. 2, and converts a Vref variable signal from a device (not shown) from digital to analog to a comparator 48 as a reference voltage Vref.
And output to the gain adjustment unit 64. This reference voltage generator 63
Is an example in which the reference voltage Vref is varied in a plurality of steps (for example, 46 steps). For example, when adjusting the output power of the semiconductor laser 42 to 1.2 times the initial light emission power, the reference voltage Vref
Should be multiplied by 1.2.

When varying the reference voltage Vref in three stages, the reference voltage generator 63 may be constituted by open-collector buffers A1 and A2, resistors R3 to R6, and a buffer A3 as shown in FIG. In this case, the reference voltage Vref is a Vref variable signal input from a device not shown through buffers A1 and A2,
And the power supply voltage Vcc and are generated by resistors R3 to R6 and output via a buffer A3. For example, when the Vref variable signal is off When the Vref variable signal is on and the Vref variable signal is off, When the Vref variable signal is off and the Vref variable signal is on, Becomes Here, RiRj indicates a resistance value of a circuit in which the resistors Rj and Rj are connected in parallel.

(Effects) As described above, according to the present invention, there is provided an optical scanning device that scans a surface to be scanned by a rotary deflector with modulated light from a semiconductor laser and does not use an fθ lens, and a change in scanning speed of the surface to be scanned And a digital value for changing the output intensity of the semiconductor laser according to the change in the scanning speed of the surface to be scanned. A digital value setting circuit; and a digital / analog converter for converting an output value of the digital value setting circuit into an analog value and changing the current of the semiconductor laser according to the analog value. Light for adjusting the gain of the output of the semiconductor laser so that the change in the output intensity of the semiconductor laser according to the output value of the digital / analog converter is optimized. In the inspection apparatus, since the gain of the digital / analog converter is adjusted according to the output of the reference voltage generator, the gain of the output of the digital / analog converter is changed after the output power of the semiconductor laser is varied. There is no need to manually re-adjust, and the provision of the reference voltage generator allows the output power of the semiconductor laser to be easily varied.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of one embodiment of the present invention, FIG. 2 is a block diagram showing a part of the embodiment, and FIG. 3 is a block diagram showing a part of another embodiment of the present invention. FIG. 4 is a block diagram showing a circuit configuration of a conventional optical scanning device.
FIG. 6 is a block diagram showing an image scanning clock generator in the device, FIG. 6 is a timing chart of the device, FIG. 7 is a plan view showing the optical scanning device, and FIG. 8 is a diagram for explaining the device. 9 (a) and 9 (b) are block diagrams showing examples of a digital value setting circuit, FIG. 10 is a timing chart of the device, and FIGS. 11 to 14 are diagrams showing characteristics of the device. is there. 41: Digital value setting circuit, 43: Image scanning clock generator, 44: Digital / analog converter, 63: Reference voltage generator, 64: Gain adjustment unit.

Claims (1)

(57) [Claims] An optical scanning device which scans a surface to be scanned with modulated light from a semiconductor laser by a rotary deflector and does not use an fθ lens, wherein the frequency is continuously changed according to a change in scanning speed of the surface to be scanned. An image scanning clock generator for generating a changing image scanning clock; a digital value setting circuit for generating a digital value for changing the output intensity of the semiconductor laser in accordance with a change in the scanning speed of the surface to be scanned; A digital / analog converter for converting an output value of the value setting circuit into an analog value and changing the current of the semiconductor laser according to the analog value, wherein the gain of the output of the digital / analog converter is set to the digital value. In an optical scanning device for adjusting the change in the output intensity of the semiconductor laser according to the output value of the analog converter to an optimum value, Optical scanning apparatus characterized by comprising a gain adjustment section that adjusts accordingly the gain of the digital / analog converter to the output of the reference voltage generator.