JP2567152B2 - CMOS logic circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to CMOS logic circuits.

[0002]

2. Description of the Related Art A conventional CMOS logic circuit has a P output circuit connected in series as a CMOS output circuit 20 as shown in FIG.
The gates G ₈ and G ₉ of the MOS output transistor 8 and the NMOS output transistor 9 are simultaneously driven by the output signal of the inverter of the input buffer 1, and the output transistors 8 and 9 of the CMOS output circuit are connected from the output terminal T ₀ to the next terminal. The transistor size is made large so that a large amount of current can be supplied to the stage, and the inverter 12 is made small in size in order to speed up and highly integrate the IC.

[0003]

DISCLOSURE OF THE INVENTION The conventional CMO described above
Since the S logic circuit drives the PMOS output transistor and the NMOS output transistor at the same time when switching the PMOS output transistor and the NMOS output transistor by the output signal of the inverter, the two output transistors become conductive for a moment and the size of the two output transistors is large. Since the on resistance of the transistor is small, a large through current flows from the high potential side to the low potential side of the power supply terminal.

Therefore, there is a problem that noise is generated in the wiring of the power supply terminal, the circuit malfunctions, and the power consumption of the CMOS logic circuit itself increases.

[0005]

In a CMOS logic circuit of the present invention, a source terminal receives an input signal and a drain terminal outputs a first output signal, and a first inverter is connected to a gate terminal of a PMOS transistor via a first inverter. Input the inverted signal of
And a second transfer gate for receiving the input signal at the source end, outputting a second output signal from the drain end, and inputting the first inverted signal to the gate end of the NMOS transistor via the second inverter. And the first output signal is input to the gate terminal of the PMOS transistor of the second transfer gate, and the second output signal is NM of the first transfer gate.
A gate delay circuit for inputting to the gate terminal of the OS transistor, and a gate terminal for inputting the first inverted signal, a source terminal connected to a high potential power source, and a drain terminal connected to an output terminal.
A CMOS output circuit having a MOS output transistor and an NMOS output transistor having a gate terminal to which the second inverted signal is input, a source terminal connected to a low potential power source, and a drain terminal connected to the output terminal. ing.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a CMOS logic circuit according to an embodiment of the present invention.

The PMOS transistor 2 and the NMOS transistor 3 which form the first transfer gate TG1
Has a commonly connected source S connected to an input terminal T _i , and a commonly connected drain D has an input threshold voltage V _T1.
Is connected to the input of the first inverter 6 and the gate of the PMOS transistor 4 of the _second transfer gate TG ₂ , and the output of the inverter 6 is of the gate of the PMOS transistor 2 and the PMOS output transistor 8 of the gate threshold voltage V _TP . It is connected to the gate G ₈ .

PMO of the second transfer gate TG ₂
Similarly, in the S transistor 4 and the NMOS transistor 5, the commonly connected sources are connected to the input terminal T _i , and the commonly connected drains are the input of the second inverter 7 having the input threshold voltage V _T2 and the PMOS transistor 3. The output of the inverter 7 is connected to the gate of the CMOS output circuit 20.
And the gate threshold voltage V _{TN of} the NMOS transistor 5 and the gate G of the NMOS output transistor 9
Connected to ₉ .

The PMOS output transistor 8 and the NMOS output transistor 9 are connected in series, and the commonly connected drain outputs T ₀ are connected to output an output signal.

Next, the operation of the circuit diagram of FIG. 1 will be described with reference to the voltage waveform diagram of FIG. Input terminal T of the gate delay circuit 10
input signal V _i to change from a low level to a high level in the _i
Is input, the output voltage V ₁ of the drain D is near the low level, and the output voltage V ₄ of the second inverter 7 is P
The MOS transistor 4 and the NMOS transistor 5 immediately become conductive, and the drain output voltage V ₂ thereof changes from low level to high level with a waveform as shown in FIG.

On the other hand, the PMOS transistor 2 becomes non-conductive because the output voltage V ₃ of the first inverter 6 is at the level of V _DD , and the NMOS transistor 3 has the drain output voltage V ₂ exceeding its gate threshold voltage. Since it becomes conductive at that time, the output voltage V ₁ of the drain DG changes from the low level to the high level with a waveform as shown in FIG. 2 with a little delay from the drain voltage V 2.

Further, the output voltage V ₁ of the drain D is the output voltage V ₃ of the inverter 6 is voltage rises only on resistance of the NMOS transistor 3 from V _DD level to be changed to the GND level, the drain output voltage V ₂ It takes time to increase the voltage compared to the change. If this time almost equal the input threshold voltage V _T2 of the input threshold voltage V _T1 and the second inverter 7 of the first inverter 6, the output voltage V ₃ of the inverter 6, as shown in FIG. 2 Changes with a delay of time τ ₁ compared with the change of the output voltage V ₄ of the inverter 7.

The operation of the CMOS output circuit 20 begins with the switching operation of the PMOS output transistor 8 in the non-conducting state and the NMOS output transistor 9 in the conducting state, so that the output voltage V ₄ of the second inverter 7 is the NMOS output transistor 9 gate threshold voltage V _TN from lower time t ₃ becomes nonconductive NMOS output transistor 9 from a conductive state, then the gate threshold of the output voltage V ₃ is the PMOS output transistor 8 of the first inverter 6 At time t ₄ when lower than the value voltage V _TP, PMOS output transistor 9 is turned on.

Next, when the input signal V _i changing from the high level to the low level is input to the input terminal T _i , the drain output voltage V ₂ is in the vicinity of the high level and the output voltage V ₃ of the inverting amplifier 6 is GND. Since it is a level, PMOS
The transistor 2 and the NMOS transistor 3 immediately become conductive, and the drain output voltage V ₁ changes from the high level to the low level with the waveform shown in FIG.

On the other hand, the NMOS transistor 5 becomes non-conductive because the output voltage V ₄ of the inverter 7 is at the GND level, and the PMOS transistor 4 becomes conductive when the drain output voltage V ₁ exceeds its gate threshold voltage. As a result, the drain output voltage V ₂ changes from the high level to the low level with a waveform as shown in FIG. 2 with a slight delay as compared with the drain voltage V ₁ .

Further, the drain output voltage V ₂ is the inverter 7
Until the output voltage V ₄ of the above changes from the GND level to the V _DD level, the voltage drops only by the on-resistance of the PMOS transistor 4, and therefore it takes longer time than the change of the drain output voltage V ₁ . At this time, the input threshold voltage V _T1 of the inverter 6 and the input threshold voltage V _T2 of the inverting amplifier 7 cause an output voltage V _T of the inverter 7 as shown in FIG.
The change of ₄ changes with a delay of time τ ₂ compared with the change of the output voltage V ₃ of the inverter 6.

As a result, in the CMOS output circuit 20, the switching operation of the PMOS output transistor 8 in the conducting state and the NMOS output transistor 9 in the non-conducting state at the beginning is such that the output voltage V ₃ of the inverter 6 is the gate threshold of the PMOS output transistor 8. At time t ₅ when the voltage becomes higher than the value voltage V _TP , the PMOS output transistor 9 changes from the conductive state to the non-conductive state, and then the output voltage V _{4 of the} inverter 7 becomes NM.
At time t ₆ when the voltage becomes higher than the gate threshold voltage V _TN of the OS output transistor 9, the PMOS output transistor 9 becomes conductive.

Thus, the PM of the CMOS output circuit 20
OS output transistor 8 and NMOS output transistor 9
Since the switching operation of is always performed after a time during which both the PMOS output transistor 8 and the NMOS output transistor 9 become non-conductive, such as between time t ₃ and time t ₄ or between time t ₅ and time t _6. It does not become conductive.

[0019]

As described above, according to the CMOS logic circuit of the present invention, by providing the gate delay circuit and separately driving the PMOS output transistor and the NMOS output transistor at the time of switching, the two output transistors become conductive at the same time. Since there is no time to be in a state, a large through current from the high potential side to the low potential side of the power supply terminal does not flow, noise on the wiring of the power supply terminal does not occur due to it, and circuit malfunction does not occur, Also, CMOS
This has the effect that the power consumption of the logic circuit itself does not increase.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a waveform diagram of each voltage shown for explaining the operation of the circuit of FIG.

FIG. 3 is a circuit diagram of an example of a conventional CMOS logic circuit.

[Explanation of symbols]

2,4 PMOS transistor 3,5 NMOS transistor 6,7,12 Inverter 8,13 PMOS output transistor 9,14 NMOS output transistor 10 Gate delay circuit 20 Output circuit T _i input terminal T ₀ output terminal TG ₂ Second transfer gate V _i input signal V ₀ output signal V ₁ , V ₂ drain output voltage V ₃ , V ₄ inverting amplifier output voltage V _T1 , _VT2 inverting amplifier input threshold voltage V _TP PMOS gate threshold voltage of output transistor V _TN NMOS output transistor gate threshold voltage τ ₁ V ₃ delay time for V ₄ change delay time τ ₂ V ₄ change time for V ₃ change delay time t ₃ NMOS output transistor becomes non-conductive time t ₅ PMOS output transistor non-conductive to time t ₄ PMOS output transistor is conducting Time to time t ₆ NMOS output transistor to become a state is turned on

Claims (2)

(57) [Claims] 1. A source terminal receives an input signal, a drain terminal outputs a first output signal, and a first inverter outputs a P signal.
A first transfer gate for inputting the first inverted signal to the gate terminal of the MOS transistor, and a second output signal from the drain terminal for receiving the input signal at the source terminal and outputting a second output signal at the second terminal.
A second transfer gate for inputting the first inverted signal to the gate terminal of the NMOS transistor via the inverter of the second transfer gate, and the first output signal is input to the gate terminal of the PMOS transistor of the second transfer gate. And a gate delay circuit for inputting the second output signal to the gate terminal of the NMOS transistor of the first transfer gate, and a gate terminal for inputting the first inverted signal and a source terminal for connecting to a high potential power source. A PMOS output transistor having a drain terminal connected to the output terminal, and a gate terminal having the second terminal
And a CMOS output circuit having an NMOS output transistor whose source end is connected to a low-potential power supply and whose drain end is connected to the output terminal. 2. The CMOS logic circuit according to claim 1, wherein the gate delay circuit and the CMOS circuit are formed on a semiconductor chip.