JP2560800B2 - Logical circuit verification device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a logic circuit verification device, and particularly when a gate level circuit is manually designed from a function level circuit description,
The present invention relates to a device for comparing the function of this gate level circuit with the above-mentioned function level description and verifying that there is no error.

[Conventional technology]

Conventionally, in this type of device, the functional level circuit description and the gate level circuit description of the combinational circuit are compared to confirm the equivalence. This makes it possible to verify that the function of the designed gate level circuit is correct.

Conventionally, when a gate level circuit is designed in this way, the equivalence has been confirmed by comparing the function level circuit description and the gate circuit description for verification. In that case, first, The functional level circuit description is automatically converted into a gate level circuit description by the conversion program. Next, the two gate-level circuit descriptions are converted into Boolean expressions, and then the equivalence is confirmed by the boolean comparison method (reference; Smith et al .: “Boolean”).
Comparison of Hardware and Flowcharts}, IBM Journal of Research and Development, January 1982 (Smith, et a
l., “Boolean Comparis on of Hardware and Flowchart
s ", IBM Journal of Research and Development, January
1982)].

[Problems to be Solved by the Invention]

However, the Boolean Comparison method has a problem in terms of processing time. That is, in the above-mentioned conventional apparatus, when confirming the equivalence of Boolean expressions, the input data signal (input In the worst case, the combination of the data signal and the control signal) is exponentially proportional to the increase in the total number of bits of the input signal, and it takes a long processing time. The larger the number of combinations to be compared, the longer the time required for the processing, and this cannot be met when quick verification is required.

An object of the present invention is to provide a logic circuit verification device capable of shortening the processing time when it is determined whether the function level circuit description and the gate level circuit description match and the function verification is performed. .

[Means for solving the problem]

The logic circuit verification device of the present invention includes a function level description analysis device that generates a combination of a circuit operation and a control signal corresponding to each circuit operation from a circuit description of a function level of a logic circuit to be verified, and a function level description. Control signal combination compressor for compressing the combination of control signals passed from the analyzer to the minimum combination of control signals required for functional verification, and each combination of control signals passed from the control signal combination compressor and the gate of the circuit. Corresponding to each combination of the control signals passed from the gate level circuit operation extracting device for extracting the circuit operation corresponding to each combination of the control signals from the level circuit description and the function level description analyzing device and the gate level circuit operation extracting device A pair of circuit operations are compared, and a result indicating whether the functional level circuit description and the gate level circuit description of the circuit match is output. And a motion comparison device.

[Action]

In the present invention, the functional level description analysis device, the control signal combination compression device, the gate level circuit operation extraction device, and the operation comparison device are used for functional verification. Compress the combination of control signals from the functional level description analyzer into the minimum combination of control signals required for functional verification in the compressor, and obtain both the circuit operation obtained by the gate level circuit operation extractor and the circuit operation from the analyzer. The configuration in which the function level circuit description and the gate level circuit description are compared to determine whether or not they match with each other is such that the combination to be compared increases exponentially depending on the total number of bits of the input signal as in the conventional case. To be able to avoid.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the logic circuit verification device of the present invention. As shown in FIG. 1, the logic circuit verification device includes a function level description analysis device 11, a control signal combination compression device 12,
It has a gate level circuit operation extraction device 13 and an operation comparison device 14.

The function level description analysis device 11 is a device for generating a combination of a circuit operation and a control signal corresponding to each circuit operation from a circuit description (function level description) a of a function level of a logic circuit to be verified, The operation comparison device 14 is provided with the operation list d obtained by the analysis device 11, and the control signal combination compression device 12 is provided with the control signal combination list b.

The control signal combination compressing device 12 is a device for compressing the control signal combination list b based on the control signal combination list b into the minimum combination of control signals required for functional verification, and the control signal combination list c obtained by the compression is a gate level circuit. It is adapted to be given to the motion extracting device 13. A gate level circuit description (gate level description) e is also input to the gate level circuit operation extraction device 13. Gate level circuit operation extraction device 13
Is an apparatus for extracting the circuit operation corresponding to each combination of control signals from the above-mentioned two kinds of inputs, and the obtained operation list f is passed to the operation comparison apparatus 14.

Since the action list d is passed to the action comparison device 14, the action list d and the action list f are passed, and the action comparison device 14 uses these two lists to combine each of the control signals. By comparing a pair of circuit operations corresponding to, it is determined whether the target functional level circuit description and the gate level circuit description match, and the result is output from the operation comparison device 14. .

As described above, according to the embodiment of the present invention, the function level description analysis for generating the operation d of the circuit and the control signal combination b corresponding to each circuit operation from the circuit description a of the function level of the logic circuit to be verified. Device 11, a control signal combination compression device 12 for compressing the control signal combination b passed from the analysis device 11 into a combination of control signals minimum required for functional verification, and each of the control signals passed from the compression device 12. From the gate level circuit operation extraction device 13, which extracts the circuit operation corresponding to each combination of the control signals from the combination c and the gate level circuit description e of the circuit, the function level description analysis device 11 and the gate level circuit operation extraction device 13. A pair of circuit operations corresponding to each combination of the control signals passed are compared, and a result indicating whether the functional level circuit description and the gate level circuit description of the circuit match is output. And a operation comparison unit 14.

The function level circuit description input to the function level description analysis device 11 is a hardware function description language, for example, the following documents: Kato, Sasaki: "FD
Elle: Structural Behavior Description Langege, Computer Hardware Description and There Applications, Uehara, Barbachi (Editors), North Holland, 1983 (Kato and Sasaki, “FDL: A Structuial Beh
aviour Description Language, "Computer Hard ware De
description Languages and their Applications, T.Uehar
a and M. Barbacci (editors), North-Holland, 1983)
May be the expression shown in. This functional level description analysis device 11 analyzes an input circuit description,
An operation list d of the circuit and a combination list b of control signals for each operation to occur are created. The device 11 compares the operation list d with the operation comparison device 14 as described above.
On the other hand, the control signal combination list b is output to the control signal combination compressor 12.

In the created combination list b, for each operation, a control signal that does not affect that operation is considered redundant. By setting this redundant control signal to the X value in this list b, the list b is set to the control signal combination compressor 12
Compress with. A specific example of this compression method is shown below.

M = IF A.AND.B THEN W ELSE IF B.AND.C THEN X BLSE IF B THEN Y ELSE Z Control signal: A, B, C Operation: W, X, Y, Z Control signal combination list [Before compression ] Operation W: A = 1, B = 1, C = 0 A = 1, B = 1, C = 1 Operation X: A = 0, B = 1, C = 1 Operation Y: A = 0, B = 1 , C = 0 operation Z: A = 0, B = 0, C = 0 A = 1, B = 0, C = 0 A = 0, B = 0, C = 1 A = 1, B = 0, C = 1 [After compression] Operation W: A = 1, B = 1, C = X Operation X: A = 0, B = 1, C = 1 Operation Y: A = 0, B = 1, C = 0 Operation Z: A = X, B = 0, C = X In the above example, for example, the operation of W is A
This means that this holds true (regardless of C) in the case of = 1 and B = 1, and the same applies to other operations. Therefore, for example, regarding the operation Z, before compression, A = 0, B = 0, C = 0, A = 1, B = 0, C = 0, A =
There are four combinations of 0, B = 0, C = 1, A = 1, B = 0, C = 1.

However, in this compression example, four combinations of control signals that cause such Z operation are one combination of A = X, B = 0, C = X as shown in the list after compression. Represent Similarly, the operation of W is also compressed,
Before compression, the combination of A = 1, B = 1, C = 0 and A = 1, B = 1, C = 1 was used, but after compression, A = 1, B = 1, C = X.
Will be represented by one combination.

The list compressed by the above method is a list of combinations of control signals which are the minimum necessary for functional verification of the circuit, and the device 12 outputs the list to the gate level circuit operation extracting device 13 as a control signal combination list c.

The gate level circuit operation extraction device 13 receives the gate level circuit description e of the target circuit and the control signal combination list c passed from the control signal combination compression device 12 described above. This device 13 gives a value of a combination of one control signal to the control input of the gate level circuit and gives the symbol of the signal name to the other input signal (input data signal) to perform symbol simulation. The expression that appears in the output of the gate level circuit in this simulation is the circuit operation corresponding to the combination of the control signals input to the gate level circuit. The gate level circuit operation extracting device 13 performs a symbolic simulation of a gate level circuit for each combination of control signals, and outputs a list f of circuit operations obtained as a result of the simulation to the operation comparing device 14.

To the behavior comparison device 14, the behavior list d passed from the function level description analysis device 11 and the behavior list f passed from the gate level circuit behavior extraction device 13 are input. This operation comparison device 14 compares both lists d and f and confirms whether the operations for each combination of control signals are equivalent. For all combinations, if the function level circuit description of the target circuit and the gate level circuit description match if they are equivalent,
The result is output.

Further, the operation of this embodiment will be specifically described with reference to FIG. First, the function level circuit description a of the target circuit is input to the function level description analysis device 11, while the gate level description e of the circuit is input to the gate level circuit behavior extraction device 13.

As described above, the circuit description a at the function level is expressed in the hardware function description language and describes all the operations under the input conditions. The control signal expresses this condition. Each operation of the circuit is represented by an expression including the input data signal name. Therefore, the signals related to the circuit are classified into three groups of control signals, input data signals and output data signals. Since the input / output signal names of the functional level circuit description a and the gate level circuit description e match,
Signals related to gate level circuits can be classified in the same manner as functional levels.

FIG. 2 is an explanatory view of the above classification. In the example of FIG. 2, if there is an input of A or B, in the presence of the signal S,
It means that C is output.

The function level description analysis device 11 analyzes the input circuit description, and creates a circuit operation list d and a control signal combination list b for causing each operation. The created action list d is output to the action comparison device 14. On the other hand, the control signal combination list b is passed to the control signal combination compressor 12, where it is compressed into a list of the minimum combinations required for functional verification of each operation according to the compression method described above, and the gate level circuit operation is performed. Pass it to the extraction device 13. The gate level circuit operation extracting device 13 extracts the circuit operation corresponding to each combination of control signals, and passes each circuit operation to the operation (function) comparing device 14. The operation comparison device 14 compares a pair of circuit operations corresponding to respective combinations of the control signals passed from the function level description analysis device 11 and the gate level circuit operation extraction device 13. If the operations match for all combinations of control signals, it is found that the functional level circuit description and the gate level circuit description of the target circuit match, and the operation comparison device 14 outputs the result. .

When the functional level circuit description and the gate level circuit description are compared in the case of performing the functional verification of the logic circuit by the above-described processing, the processing required for the verification does not cause an increase in processing time as in the conventional device. The time can be shortened. The control signal combination list b from the function level description analysis device 11 is compressed by the compression device 12, and based on this, the operation list f obtained by the gate level circuit operation extraction device 13 and the operation list d obtained by the analysis device 11 are compressed. And the method of checking whether or not the operation for each combination of control signals is the same, it is possible to avoid that the combination to be compared depends on the total number of bits of the input signal as in the past. Therefore, it is possible to prevent the number of compared combinations from increasing.

〔The invention's effect〕

As described above, according to the present invention, since the combination to be compared depends on the number of bits of the control signal, it is possible to significantly reduce the processing time.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram for explaining classification of gate level or function level. 11 …… Function level description analyzer 12 …… Control signal combination compressor 13 …… Gate level circuit operation extractor 14 …… Operation comparison device

Claims (1)

(57) [Claims] Claim: What is claimed is: 1. A function level description analysis device for generating a combination of a circuit operation and a control signal corresponding to each circuit operation from a circuit description of a function level of a logic circuit to be verified, and a function level description analysis device. The control signal combination compressor for compressing the control signal combinations to be the minimum required control signal combination for functional verification, each combination of the control signals passed from the control signal combination compressor, and the gate level circuit description of the circuit. A gate level circuit operation extraction device for extracting a circuit operation corresponding to each combination of control signals, and a pair of circuit operations corresponding to each combination of control signals passed from the function level description analysis device and the gate level circuit operation extraction device And a behavior comparison device that outputs a result indicating whether the functional level circuit description of the circuit matches the gate level circuit description. Logic circuit verification apparatus characterized by.